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Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_EntryData_8( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie6_is32_oe5_os11( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [7:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [32:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [16:0] io_out // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire roundingMode_near_even = io_roundingMode == 3'h0; // @[RoundAnyRawFNToRecFN.scala:90:53] wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; // @[RoundAnyRawFNToRecFN.scala:92:53, :93:53, :98:{27,42,63,66}] wire [8:0] sAdjustedExp = {io_in_sExp[7], io_in_sExp} - 9'h20; // @[RoundAnyRawFNToRecFN.scala:110:24] wire [1:0] _GEN = {io_in_sig[20], |(io_in_sig[19:0])}; // @[RoundAnyRawFNToRecFN.scala:116:66, :117:{26,60}, :164:56, :165:62, :166:36] wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire [12:0] roundedSig = _overflow_roundMagUp_T & io_in_sig[20] | roundMagUp & (|_GEN) ? {1'h0, io_in_sig[32:21]} + 13'h1 & {12'hFFF, ~(roundingMode_near_even & io_in_sig[20] & ~(|(io_in_sig[19:0])))} : {1'h0, io_in_sig[32:22], io_in_sig[21] | io_roundingMode == 3'h6 & (|_GEN)}; // @[RoundAnyRawFNToRecFN.scala:90:53, :95:53, :98:42, :116:66, :117:{26,60}, :164:{40,56}, :165:62, :166:36, :169:{38,67}, :170:31, :171:29, :173:16, :174:{49,57}, :175:{21,25,49,64}, :176:30, :180:47, :181:42] wire [9:0] sRoundedExp = {sAdjustedExp[8], sAdjustedExp} + {8'h0, roundedSig[12:11]}; // @[RoundAnyRawFNToRecFN.scala:110:24, :173:16, :185:{40,54}] wire overflow = ~io_in_isZero & $signed(sRoundedExp[9:4]) > 6'sh2; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:{30,50}, :237:64, :238:32] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :169:38, :243:60] wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] assign io_out = {io_in_sign, sRoundedExp[5:0] & ~(io_in_isZero ? 6'h38 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} & {2'h3, ~_notNaN_isInfOut_T, 3'h7} | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (_notNaN_isInfOut_T ? 6'h30 : 6'h0), (io_in_isZero ? 10'h0 : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}}; // @[RoundAnyRawFNToRecFN.scala:48:5, :173:16, :185:40, :187:37, :191:27, :246:39, :248:45, :252:24, :253:{14,18}, :260:17, :261:{14,18}, :264:17, :265:{14,18}, :272:15, :273:16, :276:15, :277:16, :280:12, :283:11, :284:13, :286:33] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }
module dataMems_452( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_6( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [7:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [32:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [7:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [32:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire [9:0] _sAdjustedExp_T = {{2{io_in_sExp_0[7]}}, io_in_sExp_0} + 10'hC0; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [25:0] _adjustedSig_T = io_in_sig_0[32:7]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [6:0] _adjustedSig_T_1 = io_in_sig_0[6:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [7:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [31:0] inflight_1; // @[Monitor.scala:726:35] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File SinkX.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ class SinkXRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val address = UInt(params.inner.bundle.addressBits.W) } class SinkX(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Decoupled(new FullRequest(params)) val x = Flipped(Decoupled(new SinkXRequest(params))) }) val x = Queue(io.x, 1) val (tag, set, offset) = params.parseAddress(x.bits.address) x.ready := io.req.ready io.req.valid := x.valid params.ccover(x.valid && !x.ready, "SINKX_STALL", "Backpressure when accepting a control message") io.req.bits.prio := VecInit(1.U(3.W).asBools) // same prio as A io.req.bits.control:= true.B io.req.bits.opcode := 0.U io.req.bits.param := 0.U io.req.bits.size := params.offsetBits.U // The source does not matter, because a flush command never allocates a way. // However, it must be a legal source, otherwise assertions might spuriously fire. io.req.bits.source := params.inner.client.clients.map(_.sourceId.start).min.U io.req.bits.offset := 0.U io.req.bits.set := set io.req.bits.tag := tag io.req.bits.put := 0.U }
module SinkX( // @[SinkX.scala:28:7] input clock, // @[SinkX.scala:28:7] input reset, // @[SinkX.scala:28:7] input io_req_ready, // @[SinkX.scala:30:14] output io_req_valid, // @[SinkX.scala:30:14] output [12:0] io_req_bits_tag, // @[SinkX.scala:30:14] output [9:0] io_req_bits_set, // @[SinkX.scala:30:14] output io_x_ready, // @[SinkX.scala:30:14] input io_x_valid, // @[SinkX.scala:30:14] input [31:0] io_x_bits_address // @[SinkX.scala:30:14] ); wire [31:0] _x_q_io_deq_bits_address; // @[Decoupled.scala:362:21] Queue1_SinkXRequest x_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (io_x_ready), .io_enq_valid (io_x_valid), .io_enq_bits_address (io_x_bits_address), .io_deq_ready (io_req_ready), .io_deq_valid (io_req_valid), .io_deq_bits_address (_x_q_io_deq_bits_address) ); // @[Decoupled.scala:362:21] assign io_req_bits_tag = {_x_q_io_deq_bits_address[31], _x_q_io_deq_bits_address[27:16]}; // @[Decoupled.scala:362:21] assign io_req_bits_set = _x_q_io_deq_bits_address[15:6]; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module TLXbar_ccbus1_in_i0_o0_a1d8s1k1z1u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset // @[Xbar.scala:74:9] ); endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } } File common.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ object consts { /*------------------------------------------------------------------------ | For rounding to integer values, rounding mode 'odd' rounds to minimum | magnitude instead, same as 'minMag'. *------------------------------------------------------------------------*/ def round_near_even = "b000".U(3.W) def round_minMag = "b001".U(3.W) def round_min = "b010".U(3.W) def round_max = "b011".U(3.W) def round_near_maxMag = "b100".U(3.W) def round_odd = "b110".U(3.W) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def tininess_beforeRounding = 0.U def tininess_afterRounding = 1.U /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def flRoundOpt_sigMSBitAlwaysZero = 1 def flRoundOpt_subnormsAlwaysExact = 2 def flRoundOpt_neverUnderflows = 4 def flRoundOpt_neverOverflows = 8 /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def divSqrtOpt_twoBitsPerCycle = 16 } class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle { val isNaN: Bool = Bool() // overrides all other fields val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig' val isZero: Bool = Bool() // overrides 'sExp' and 'sig' val sign: Bool = Bool() val sExp: SInt = SInt((expWidth + 2).W) val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0 } //*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS: object isSigNaNRawFloat { def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2) }
module MulAddRecFNToRaw_preMul_e8_s24_2( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:71:7, :74:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - 12'h2B; // @[MulAddRecFN.scala:106:42] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }
module dataMems_425( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops }
module BranchKillableQueue_20( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty, // @[util.scala:463:14] output [3:0] io_count // @[util.scala:463:14] ); wire [130:0] _ram_ext_R0_data; // @[util.scala:503:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _do_enq_T_4 = 1'h1; // @[util.scala:514:42] wire _do_enq_T_7 = 1'h1; // @[util.scala:514:102] wire _valids_0_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_0_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_1_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_1_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_2_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_2_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_3_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_3_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_4_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_4_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_5_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_5_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_6_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_6_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_7_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_7_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_8_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_8_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_9_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_9_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_10_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_10_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_11_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_11_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_12_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_12_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_13_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_13_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_14_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_14_T_6 = 1'h1; // @[util.scala:520:83] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34] wire _do_enq_T_2 = 1'h0; // @[util.scala:126:59] wire _do_enq_T_3 = 1'h0; // @[util.scala:61:61] wire _do_enq_T_6 = 1'h0; // @[util.scala:514:113] wire _valids_0_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_0_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_0_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_1_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_1_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_1_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_2_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_2_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_2_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_3_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_3_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_3_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_4_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_4_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_4_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_5_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_5_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_5_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_6_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_6_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_6_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_7_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_7_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_7_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_8_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_8_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_8_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_9_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_9_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_9_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_10_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_10_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_10_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_11_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_11_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_11_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_12_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_12_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_12_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_13_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_13_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_13_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_14_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_14_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_14_T_5 = 1'h0; // @[util.scala:520:94] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:458:7] wire [3:0] _do_enq_T_1 = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:126:51] wire _io_enq_ready_T; // @[util.scala:543:21] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:93:25, :458:7] wire _io_deq_valid_T_1; // @[util.scala:548:42] wire [31:0] out_uop_inst; // @[util.scala:545:19] wire [31:0] out_uop_debug_inst; // @[util.scala:545:19] wire out_uop_is_rvc; // @[util.scala:545:19] wire [33:0] out_uop_debug_pc; // @[util.scala:545:19] wire out_uop_iq_type_0; // @[util.scala:545:19] wire out_uop_iq_type_1; // @[util.scala:545:19] wire out_uop_iq_type_2; // @[util.scala:545:19] wire out_uop_iq_type_3; // @[util.scala:545:19] wire out_uop_fu_code_0; // @[util.scala:545:19] wire out_uop_fu_code_1; // @[util.scala:545:19] wire out_uop_fu_code_2; // @[util.scala:545:19] wire out_uop_fu_code_3; // @[util.scala:545:19] wire out_uop_fu_code_4; // @[util.scala:545:19] wire out_uop_fu_code_5; // @[util.scala:545:19] wire out_uop_fu_code_6; // @[util.scala:545:19] wire out_uop_fu_code_7; // @[util.scala:545:19] wire out_uop_fu_code_8; // @[util.scala:545:19] wire out_uop_fu_code_9; // @[util.scala:545:19] wire out_uop_iw_issued; // @[util.scala:545:19] wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19] wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19] wire out_uop_iw_p1_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p2_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19] wire out_uop_dis_col_sel; // @[util.scala:545:19] wire [3:0] out_uop_br_mask; // @[util.scala:545:19] wire [1:0] out_uop_br_tag; // @[util.scala:545:19] wire [3:0] out_uop_br_type; // @[util.scala:545:19] wire out_uop_is_sfb; // @[util.scala:545:19] wire out_uop_is_fence; // @[util.scala:545:19] wire out_uop_is_fencei; // @[util.scala:545:19] wire out_uop_is_sfence; // @[util.scala:545:19] wire out_uop_is_amo; // @[util.scala:545:19] wire out_uop_is_eret; // @[util.scala:545:19] wire out_uop_is_sys_pc2epc; // @[util.scala:545:19] wire out_uop_is_rocc; // @[util.scala:545:19] wire out_uop_is_mov; // @[util.scala:545:19] wire [3:0] out_uop_ftq_idx; // @[util.scala:545:19] wire out_uop_edge_inst; // @[util.scala:545:19] wire [5:0] out_uop_pc_lob; // @[util.scala:545:19] wire out_uop_taken; // @[util.scala:545:19] wire out_uop_imm_rename; // @[util.scala:545:19] wire [2:0] out_uop_imm_sel; // @[util.scala:545:19] wire [4:0] out_uop_pimm; // @[util.scala:545:19] wire [19:0] out_uop_imm_packed; // @[util.scala:545:19] wire [1:0] out_uop_op1_sel; // @[util.scala:545:19] wire [2:0] out_uop_op2_sel; // @[util.scala:545:19] wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19] wire out_uop_fp_ctrl_wen; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19] wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19] wire out_uop_fp_ctrl_toint; // @[util.scala:545:19] wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19] wire out_uop_fp_ctrl_fma; // @[util.scala:545:19] wire out_uop_fp_ctrl_div; // @[util.scala:545:19] wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19] wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19] wire out_uop_fp_ctrl_vec; // @[util.scala:545:19] wire [4:0] out_uop_rob_idx; // @[util.scala:545:19] wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19] wire [3:0] out_uop_stq_idx; // @[util.scala:545:19] wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19] wire [5:0] out_uop_pdst; // @[util.scala:545:19] wire [5:0] out_uop_prs1; // @[util.scala:545:19] wire [5:0] out_uop_prs2; // @[util.scala:545:19] wire [5:0] out_uop_prs3; // @[util.scala:545:19] wire [3:0] out_uop_ppred; // @[util.scala:545:19] wire out_uop_prs1_busy; // @[util.scala:545:19] wire out_uop_prs2_busy; // @[util.scala:545:19] wire out_uop_prs3_busy; // @[util.scala:545:19] wire out_uop_ppred_busy; // @[util.scala:545:19] wire [5:0] out_uop_stale_pdst; // @[util.scala:545:19] wire out_uop_exception; // @[util.scala:545:19] wire [63:0] out_uop_exc_cause; // @[util.scala:545:19] wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19] wire [1:0] out_uop_mem_size; // @[util.scala:545:19] wire out_uop_mem_signed; // @[util.scala:545:19] wire out_uop_uses_ldq; // @[util.scala:545:19] wire out_uop_uses_stq; // @[util.scala:545:19] wire out_uop_is_unique; // @[util.scala:545:19] wire out_uop_flush_on_commit; // @[util.scala:545:19] wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19] wire out_uop_ldst_is_rs1; // @[util.scala:545:19] wire [5:0] out_uop_ldst; // @[util.scala:545:19] wire [5:0] out_uop_lrs1; // @[util.scala:545:19] wire [5:0] out_uop_lrs2; // @[util.scala:545:19] wire [5:0] out_uop_lrs3; // @[util.scala:545:19] wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19] wire out_uop_frs3_en; // @[util.scala:545:19] wire out_uop_fcn_dw; // @[util.scala:545:19] wire [4:0] out_uop_fcn_op; // @[util.scala:545:19] wire out_uop_fp_val; // @[util.scala:545:19] wire [2:0] out_uop_fp_rm; // @[util.scala:545:19] wire [1:0] out_uop_fp_typ; // @[util.scala:545:19] wire out_uop_xcpt_pf_if; // @[util.scala:545:19] wire out_uop_xcpt_ae_if; // @[util.scala:545:19] wire out_uop_xcpt_ma_if; // @[util.scala:545:19] wire out_uop_bp_debug_if; // @[util.scala:545:19] wire out_uop_bp_xcpt_if; // @[util.scala:545:19] wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19] wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19] wire [33:0] out_addr; // @[util.scala:545:19] wire [63:0] out_data; // @[util.scala:545:19] wire out_is_hella; // @[util.scala:545:19] wire out_tag_match; // @[util.scala:545:19] wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19] wire [21:0] out_old_meta_tag; // @[util.scala:545:19] wire [1:0] out_way_en; // @[util.scala:545:19] wire [4:0] out_sdq_id; // @[util.scala:545:19] wire _io_empty_T_1; // @[util.scala:512:27] wire [3:0] _io_count_T_5; // @[util.scala:556:22] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count_0; // @[util.scala:458:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:503:22, :545:19] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:503:22, :545:19] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:503:22, :545:19] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:503:22, :545:19] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:503:22, :545:19] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:503:22, :545:19] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:503:22, :545:19] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:503:22, :545:19] reg valids_0; // @[util.scala:504:26] wire _valids_0_T_4 = valids_0; // @[util.scala:504:26, :520:31] reg valids_1; // @[util.scala:504:26] wire _valids_1_T_4 = valids_1; // @[util.scala:504:26, :520:31] reg valids_2; // @[util.scala:504:26] wire _valids_2_T_4 = valids_2; // @[util.scala:504:26, :520:31] reg valids_3; // @[util.scala:504:26] wire _valids_3_T_4 = valids_3; // @[util.scala:504:26, :520:31] reg valids_4; // @[util.scala:504:26] wire _valids_4_T_4 = valids_4; // @[util.scala:504:26, :520:31] reg valids_5; // @[util.scala:504:26] wire _valids_5_T_4 = valids_5; // @[util.scala:504:26, :520:31] reg valids_6; // @[util.scala:504:26] wire _valids_6_T_4 = valids_6; // @[util.scala:504:26, :520:31] reg valids_7; // @[util.scala:504:26] wire _valids_7_T_4 = valids_7; // @[util.scala:504:26, :520:31] reg valids_8; // @[util.scala:504:26] wire _valids_8_T_4 = valids_8; // @[util.scala:504:26, :520:31] reg valids_9; // @[util.scala:504:26] wire _valids_9_T_4 = valids_9; // @[util.scala:504:26, :520:31] reg valids_10; // @[util.scala:504:26] wire _valids_10_T_4 = valids_10; // @[util.scala:504:26, :520:31] reg valids_11; // @[util.scala:504:26] wire _valids_11_T_4 = valids_11; // @[util.scala:504:26, :520:31] reg valids_12; // @[util.scala:504:26] wire _valids_12_T_4 = valids_12; // @[util.scala:504:26, :520:31] reg valids_13; // @[util.scala:504:26] wire _valids_13_T_4 = valids_13; // @[util.scala:504:26, :520:31] reg valids_14; // @[util.scala:504:26] wire _valids_14_T_4 = valids_14; // @[util.scala:504:26, :520:31] reg [31:0] uops_0_inst; // @[util.scala:505:22] reg [31:0] uops_0_debug_inst; // @[util.scala:505:22] reg uops_0_is_rvc; // @[util.scala:505:22] reg [33:0] uops_0_debug_pc; // @[util.scala:505:22] reg uops_0_iq_type_0; // @[util.scala:505:22] reg uops_0_iq_type_1; // @[util.scala:505:22] reg uops_0_iq_type_2; // @[util.scala:505:22] reg uops_0_iq_type_3; // @[util.scala:505:22] reg uops_0_fu_code_0; // @[util.scala:505:22] reg uops_0_fu_code_1; // @[util.scala:505:22] reg uops_0_fu_code_2; // @[util.scala:505:22] reg uops_0_fu_code_3; // @[util.scala:505:22] reg uops_0_fu_code_4; // @[util.scala:505:22] reg uops_0_fu_code_5; // @[util.scala:505:22] reg uops_0_fu_code_6; // @[util.scala:505:22] reg uops_0_fu_code_7; // @[util.scala:505:22] reg uops_0_fu_code_8; // @[util.scala:505:22] reg uops_0_fu_code_9; // @[util.scala:505:22] reg uops_0_iw_issued; // @[util.scala:505:22] reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_0_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_0_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_0_br_mask; // @[util.scala:505:22] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_0_br_tag; // @[util.scala:505:22] reg [3:0] uops_0_br_type; // @[util.scala:505:22] reg uops_0_is_sfb; // @[util.scala:505:22] reg uops_0_is_fence; // @[util.scala:505:22] reg uops_0_is_fencei; // @[util.scala:505:22] reg uops_0_is_sfence; // @[util.scala:505:22] reg uops_0_is_amo; // @[util.scala:505:22] reg uops_0_is_eret; // @[util.scala:505:22] reg uops_0_is_sys_pc2epc; // @[util.scala:505:22] reg uops_0_is_rocc; // @[util.scala:505:22] reg uops_0_is_mov; // @[util.scala:505:22] reg [3:0] uops_0_ftq_idx; // @[util.scala:505:22] reg uops_0_edge_inst; // @[util.scala:505:22] reg [5:0] uops_0_pc_lob; // @[util.scala:505:22] reg uops_0_taken; // @[util.scala:505:22] reg uops_0_imm_rename; // @[util.scala:505:22] reg [2:0] uops_0_imm_sel; // @[util.scala:505:22] reg [4:0] uops_0_pimm; // @[util.scala:505:22] reg [19:0] uops_0_imm_packed; // @[util.scala:505:22] reg [1:0] uops_0_op1_sel; // @[util.scala:505:22] reg [2:0] uops_0_op2_sel; // @[util.scala:505:22] reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_0_fp_ctrl_wen; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_0_fp_ctrl_toint; // @[util.scala:505:22] reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_0_fp_ctrl_fma; // @[util.scala:505:22] reg uops_0_fp_ctrl_div; // @[util.scala:505:22] reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_0_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_0_rob_idx; // @[util.scala:505:22] reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_0_stq_idx; // @[util.scala:505:22] reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_0_pdst; // @[util.scala:505:22] reg [5:0] uops_0_prs1; // @[util.scala:505:22] reg [5:0] uops_0_prs2; // @[util.scala:505:22] reg [5:0] uops_0_prs3; // @[util.scala:505:22] reg [3:0] uops_0_ppred; // @[util.scala:505:22] reg uops_0_prs1_busy; // @[util.scala:505:22] reg uops_0_prs2_busy; // @[util.scala:505:22] reg uops_0_prs3_busy; // @[util.scala:505:22] reg uops_0_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_0_stale_pdst; // @[util.scala:505:22] reg uops_0_exception; // @[util.scala:505:22] reg [63:0] uops_0_exc_cause; // @[util.scala:505:22] reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_0_mem_size; // @[util.scala:505:22] reg uops_0_mem_signed; // @[util.scala:505:22] reg uops_0_uses_ldq; // @[util.scala:505:22] reg uops_0_uses_stq; // @[util.scala:505:22] reg uops_0_is_unique; // @[util.scala:505:22] reg uops_0_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22] reg uops_0_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_0_ldst; // @[util.scala:505:22] reg [5:0] uops_0_lrs1; // @[util.scala:505:22] reg [5:0] uops_0_lrs2; // @[util.scala:505:22] reg [5:0] uops_0_lrs3; // @[util.scala:505:22] reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22] reg uops_0_frs3_en; // @[util.scala:505:22] reg uops_0_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_0_fcn_op; // @[util.scala:505:22] reg uops_0_fp_val; // @[util.scala:505:22] reg [2:0] uops_0_fp_rm; // @[util.scala:505:22] reg [1:0] uops_0_fp_typ; // @[util.scala:505:22] reg uops_0_xcpt_pf_if; // @[util.scala:505:22] reg uops_0_xcpt_ae_if; // @[util.scala:505:22] reg uops_0_xcpt_ma_if; // @[util.scala:505:22] reg uops_0_bp_debug_if; // @[util.scala:505:22] reg uops_0_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_1_inst; // @[util.scala:505:22] reg [31:0] uops_1_debug_inst; // @[util.scala:505:22] reg uops_1_is_rvc; // @[util.scala:505:22] reg [33:0] uops_1_debug_pc; // @[util.scala:505:22] reg uops_1_iq_type_0; // @[util.scala:505:22] reg uops_1_iq_type_1; // @[util.scala:505:22] reg uops_1_iq_type_2; // @[util.scala:505:22] reg uops_1_iq_type_3; // @[util.scala:505:22] reg uops_1_fu_code_0; // @[util.scala:505:22] reg uops_1_fu_code_1; // @[util.scala:505:22] reg uops_1_fu_code_2; // @[util.scala:505:22] reg uops_1_fu_code_3; // @[util.scala:505:22] reg uops_1_fu_code_4; // @[util.scala:505:22] reg uops_1_fu_code_5; // @[util.scala:505:22] reg uops_1_fu_code_6; // @[util.scala:505:22] reg uops_1_fu_code_7; // @[util.scala:505:22] reg uops_1_fu_code_8; // @[util.scala:505:22] reg uops_1_fu_code_9; // @[util.scala:505:22] reg uops_1_iw_issued; // @[util.scala:505:22] reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_1_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_1_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_1_br_mask; // @[util.scala:505:22] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_1_br_tag; // @[util.scala:505:22] reg [3:0] uops_1_br_type; // @[util.scala:505:22] reg uops_1_is_sfb; // @[util.scala:505:22] reg uops_1_is_fence; // @[util.scala:505:22] reg uops_1_is_fencei; // @[util.scala:505:22] reg uops_1_is_sfence; // @[util.scala:505:22] reg uops_1_is_amo; // @[util.scala:505:22] reg uops_1_is_eret; // @[util.scala:505:22] reg uops_1_is_sys_pc2epc; // @[util.scala:505:22] reg uops_1_is_rocc; // @[util.scala:505:22] reg uops_1_is_mov; // @[util.scala:505:22] reg [3:0] uops_1_ftq_idx; // @[util.scala:505:22] reg uops_1_edge_inst; // @[util.scala:505:22] reg [5:0] uops_1_pc_lob; // @[util.scala:505:22] reg uops_1_taken; // @[util.scala:505:22] reg uops_1_imm_rename; // @[util.scala:505:22] reg [2:0] uops_1_imm_sel; // @[util.scala:505:22] reg [4:0] uops_1_pimm; // @[util.scala:505:22] reg [19:0] uops_1_imm_packed; // @[util.scala:505:22] reg [1:0] uops_1_op1_sel; // @[util.scala:505:22] reg [2:0] uops_1_op2_sel; // @[util.scala:505:22] reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_1_fp_ctrl_wen; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_1_fp_ctrl_toint; // @[util.scala:505:22] reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_1_fp_ctrl_fma; // @[util.scala:505:22] reg uops_1_fp_ctrl_div; // @[util.scala:505:22] reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_1_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_1_rob_idx; // @[util.scala:505:22] reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_1_stq_idx; // @[util.scala:505:22] reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_1_pdst; // @[util.scala:505:22] reg [5:0] uops_1_prs1; // @[util.scala:505:22] reg [5:0] uops_1_prs2; // @[util.scala:505:22] reg [5:0] uops_1_prs3; // @[util.scala:505:22] reg [3:0] uops_1_ppred; // @[util.scala:505:22] reg uops_1_prs1_busy; // @[util.scala:505:22] reg uops_1_prs2_busy; // @[util.scala:505:22] reg uops_1_prs3_busy; // @[util.scala:505:22] reg uops_1_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_1_stale_pdst; // @[util.scala:505:22] reg uops_1_exception; // @[util.scala:505:22] reg [63:0] uops_1_exc_cause; // @[util.scala:505:22] reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_1_mem_size; // @[util.scala:505:22] reg uops_1_mem_signed; // @[util.scala:505:22] reg uops_1_uses_ldq; // @[util.scala:505:22] reg uops_1_uses_stq; // @[util.scala:505:22] reg uops_1_is_unique; // @[util.scala:505:22] reg uops_1_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22] reg uops_1_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_1_ldst; // @[util.scala:505:22] reg [5:0] uops_1_lrs1; // @[util.scala:505:22] reg [5:0] uops_1_lrs2; // @[util.scala:505:22] reg [5:0] uops_1_lrs3; // @[util.scala:505:22] reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22] reg uops_1_frs3_en; // @[util.scala:505:22] reg uops_1_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_1_fcn_op; // @[util.scala:505:22] reg uops_1_fp_val; // @[util.scala:505:22] reg [2:0] uops_1_fp_rm; // @[util.scala:505:22] reg [1:0] uops_1_fp_typ; // @[util.scala:505:22] reg uops_1_xcpt_pf_if; // @[util.scala:505:22] reg uops_1_xcpt_ae_if; // @[util.scala:505:22] reg uops_1_xcpt_ma_if; // @[util.scala:505:22] reg uops_1_bp_debug_if; // @[util.scala:505:22] reg uops_1_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_2_inst; // @[util.scala:505:22] reg [31:0] uops_2_debug_inst; // @[util.scala:505:22] reg uops_2_is_rvc; // @[util.scala:505:22] reg [33:0] uops_2_debug_pc; // @[util.scala:505:22] reg uops_2_iq_type_0; // @[util.scala:505:22] reg uops_2_iq_type_1; // @[util.scala:505:22] reg uops_2_iq_type_2; // @[util.scala:505:22] reg uops_2_iq_type_3; // @[util.scala:505:22] reg uops_2_fu_code_0; // @[util.scala:505:22] reg uops_2_fu_code_1; // @[util.scala:505:22] reg uops_2_fu_code_2; // @[util.scala:505:22] reg uops_2_fu_code_3; // @[util.scala:505:22] reg uops_2_fu_code_4; // @[util.scala:505:22] reg uops_2_fu_code_5; // @[util.scala:505:22] reg uops_2_fu_code_6; // @[util.scala:505:22] reg uops_2_fu_code_7; // @[util.scala:505:22] reg uops_2_fu_code_8; // @[util.scala:505:22] reg uops_2_fu_code_9; // @[util.scala:505:22] reg uops_2_iw_issued; // @[util.scala:505:22] reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_2_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_2_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_2_br_mask; // @[util.scala:505:22] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_2_br_tag; // @[util.scala:505:22] reg [3:0] uops_2_br_type; // @[util.scala:505:22] reg uops_2_is_sfb; // @[util.scala:505:22] reg uops_2_is_fence; // @[util.scala:505:22] reg uops_2_is_fencei; // @[util.scala:505:22] reg uops_2_is_sfence; // @[util.scala:505:22] reg uops_2_is_amo; // @[util.scala:505:22] reg uops_2_is_eret; // @[util.scala:505:22] reg uops_2_is_sys_pc2epc; // @[util.scala:505:22] reg uops_2_is_rocc; // @[util.scala:505:22] reg uops_2_is_mov; // @[util.scala:505:22] reg [3:0] uops_2_ftq_idx; // @[util.scala:505:22] reg uops_2_edge_inst; // @[util.scala:505:22] reg [5:0] uops_2_pc_lob; // @[util.scala:505:22] reg uops_2_taken; // @[util.scala:505:22] reg uops_2_imm_rename; // @[util.scala:505:22] reg [2:0] uops_2_imm_sel; // @[util.scala:505:22] reg [4:0] uops_2_pimm; // @[util.scala:505:22] reg [19:0] uops_2_imm_packed; // @[util.scala:505:22] reg [1:0] uops_2_op1_sel; // @[util.scala:505:22] reg [2:0] uops_2_op2_sel; // @[util.scala:505:22] reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_2_fp_ctrl_wen; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_2_fp_ctrl_toint; // @[util.scala:505:22] reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_2_fp_ctrl_fma; // @[util.scala:505:22] reg uops_2_fp_ctrl_div; // @[util.scala:505:22] reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_2_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_2_rob_idx; // @[util.scala:505:22] reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_2_stq_idx; // @[util.scala:505:22] reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_2_pdst; // @[util.scala:505:22] reg [5:0] uops_2_prs1; // @[util.scala:505:22] reg [5:0] uops_2_prs2; // @[util.scala:505:22] reg [5:0] uops_2_prs3; // @[util.scala:505:22] reg [3:0] uops_2_ppred; // @[util.scala:505:22] reg uops_2_prs1_busy; // @[util.scala:505:22] reg uops_2_prs2_busy; // @[util.scala:505:22] reg uops_2_prs3_busy; // @[util.scala:505:22] reg uops_2_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_2_stale_pdst; // @[util.scala:505:22] reg uops_2_exception; // @[util.scala:505:22] reg [63:0] uops_2_exc_cause; // @[util.scala:505:22] reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_2_mem_size; // @[util.scala:505:22] reg uops_2_mem_signed; // @[util.scala:505:22] reg uops_2_uses_ldq; // @[util.scala:505:22] reg uops_2_uses_stq; // @[util.scala:505:22] reg uops_2_is_unique; // @[util.scala:505:22] reg uops_2_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22] reg uops_2_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_2_ldst; // @[util.scala:505:22] reg [5:0] uops_2_lrs1; // @[util.scala:505:22] reg [5:0] uops_2_lrs2; // @[util.scala:505:22] reg [5:0] uops_2_lrs3; // @[util.scala:505:22] reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22] reg uops_2_frs3_en; // @[util.scala:505:22] reg uops_2_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_2_fcn_op; // @[util.scala:505:22] reg uops_2_fp_val; // @[util.scala:505:22] reg [2:0] uops_2_fp_rm; // @[util.scala:505:22] reg [1:0] uops_2_fp_typ; // @[util.scala:505:22] reg uops_2_xcpt_pf_if; // @[util.scala:505:22] reg uops_2_xcpt_ae_if; // @[util.scala:505:22] reg uops_2_xcpt_ma_if; // @[util.scala:505:22] reg uops_2_bp_debug_if; // @[util.scala:505:22] reg uops_2_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_3_inst; // @[util.scala:505:22] reg [31:0] uops_3_debug_inst; // @[util.scala:505:22] reg uops_3_is_rvc; // @[util.scala:505:22] reg [33:0] uops_3_debug_pc; // @[util.scala:505:22] reg uops_3_iq_type_0; // @[util.scala:505:22] reg uops_3_iq_type_1; // @[util.scala:505:22] reg uops_3_iq_type_2; // @[util.scala:505:22] reg uops_3_iq_type_3; // @[util.scala:505:22] reg uops_3_fu_code_0; // @[util.scala:505:22] reg uops_3_fu_code_1; // @[util.scala:505:22] reg uops_3_fu_code_2; // @[util.scala:505:22] reg uops_3_fu_code_3; // @[util.scala:505:22] reg uops_3_fu_code_4; // @[util.scala:505:22] reg uops_3_fu_code_5; // @[util.scala:505:22] reg uops_3_fu_code_6; // @[util.scala:505:22] reg uops_3_fu_code_7; // @[util.scala:505:22] reg uops_3_fu_code_8; // @[util.scala:505:22] reg uops_3_fu_code_9; // @[util.scala:505:22] reg uops_3_iw_issued; // @[util.scala:505:22] reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_3_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_3_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_3_br_mask; // @[util.scala:505:22] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_3_br_tag; // @[util.scala:505:22] reg [3:0] uops_3_br_type; // @[util.scala:505:22] reg uops_3_is_sfb; // @[util.scala:505:22] reg uops_3_is_fence; // @[util.scala:505:22] reg uops_3_is_fencei; // @[util.scala:505:22] reg uops_3_is_sfence; // @[util.scala:505:22] reg uops_3_is_amo; // @[util.scala:505:22] reg uops_3_is_eret; // @[util.scala:505:22] reg uops_3_is_sys_pc2epc; // @[util.scala:505:22] reg uops_3_is_rocc; // @[util.scala:505:22] reg uops_3_is_mov; // @[util.scala:505:22] reg [3:0] uops_3_ftq_idx; // @[util.scala:505:22] reg uops_3_edge_inst; // @[util.scala:505:22] reg [5:0] uops_3_pc_lob; // @[util.scala:505:22] reg uops_3_taken; // @[util.scala:505:22] reg uops_3_imm_rename; // @[util.scala:505:22] reg [2:0] uops_3_imm_sel; // @[util.scala:505:22] reg [4:0] uops_3_pimm; // @[util.scala:505:22] reg [19:0] uops_3_imm_packed; // @[util.scala:505:22] reg [1:0] uops_3_op1_sel; // @[util.scala:505:22] reg [2:0] uops_3_op2_sel; // @[util.scala:505:22] reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_3_fp_ctrl_wen; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_3_fp_ctrl_toint; // @[util.scala:505:22] reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_3_fp_ctrl_fma; // @[util.scala:505:22] reg uops_3_fp_ctrl_div; // @[util.scala:505:22] reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_3_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_3_rob_idx; // @[util.scala:505:22] reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_3_stq_idx; // @[util.scala:505:22] reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_3_pdst; // @[util.scala:505:22] reg [5:0] uops_3_prs1; // @[util.scala:505:22] reg [5:0] uops_3_prs2; // @[util.scala:505:22] reg [5:0] uops_3_prs3; // @[util.scala:505:22] reg [3:0] uops_3_ppred; // @[util.scala:505:22] reg uops_3_prs1_busy; // @[util.scala:505:22] reg uops_3_prs2_busy; // @[util.scala:505:22] reg uops_3_prs3_busy; // @[util.scala:505:22] reg uops_3_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_3_stale_pdst; // @[util.scala:505:22] reg uops_3_exception; // @[util.scala:505:22] reg [63:0] uops_3_exc_cause; // @[util.scala:505:22] reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_3_mem_size; // @[util.scala:505:22] reg uops_3_mem_signed; // @[util.scala:505:22] reg uops_3_uses_ldq; // @[util.scala:505:22] reg uops_3_uses_stq; // @[util.scala:505:22] reg uops_3_is_unique; // @[util.scala:505:22] reg uops_3_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22] reg uops_3_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_3_ldst; // @[util.scala:505:22] reg [5:0] uops_3_lrs1; // @[util.scala:505:22] reg [5:0] uops_3_lrs2; // @[util.scala:505:22] reg [5:0] uops_3_lrs3; // @[util.scala:505:22] reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22] reg uops_3_frs3_en; // @[util.scala:505:22] reg uops_3_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_3_fcn_op; // @[util.scala:505:22] reg uops_3_fp_val; // @[util.scala:505:22] reg [2:0] uops_3_fp_rm; // @[util.scala:505:22] reg [1:0] uops_3_fp_typ; // @[util.scala:505:22] reg uops_3_xcpt_pf_if; // @[util.scala:505:22] reg uops_3_xcpt_ae_if; // @[util.scala:505:22] reg uops_3_xcpt_ma_if; // @[util.scala:505:22] reg uops_3_bp_debug_if; // @[util.scala:505:22] reg uops_3_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_4_inst; // @[util.scala:505:22] reg [31:0] uops_4_debug_inst; // @[util.scala:505:22] reg uops_4_is_rvc; // @[util.scala:505:22] reg [33:0] uops_4_debug_pc; // @[util.scala:505:22] reg uops_4_iq_type_0; // @[util.scala:505:22] reg uops_4_iq_type_1; // @[util.scala:505:22] reg uops_4_iq_type_2; // @[util.scala:505:22] reg uops_4_iq_type_3; // @[util.scala:505:22] reg uops_4_fu_code_0; // @[util.scala:505:22] reg uops_4_fu_code_1; // @[util.scala:505:22] reg uops_4_fu_code_2; // @[util.scala:505:22] reg uops_4_fu_code_3; // @[util.scala:505:22] reg uops_4_fu_code_4; // @[util.scala:505:22] reg uops_4_fu_code_5; // @[util.scala:505:22] reg uops_4_fu_code_6; // @[util.scala:505:22] reg uops_4_fu_code_7; // @[util.scala:505:22] reg uops_4_fu_code_8; // @[util.scala:505:22] reg uops_4_fu_code_9; // @[util.scala:505:22] reg uops_4_iw_issued; // @[util.scala:505:22] reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_4_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_4_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_4_br_mask; // @[util.scala:505:22] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_4_br_tag; // @[util.scala:505:22] reg [3:0] uops_4_br_type; // @[util.scala:505:22] reg uops_4_is_sfb; // @[util.scala:505:22] reg uops_4_is_fence; // @[util.scala:505:22] reg uops_4_is_fencei; // @[util.scala:505:22] reg uops_4_is_sfence; // @[util.scala:505:22] reg uops_4_is_amo; // @[util.scala:505:22] reg uops_4_is_eret; // @[util.scala:505:22] reg uops_4_is_sys_pc2epc; // @[util.scala:505:22] reg uops_4_is_rocc; // @[util.scala:505:22] reg uops_4_is_mov; // @[util.scala:505:22] reg [3:0] uops_4_ftq_idx; // @[util.scala:505:22] reg uops_4_edge_inst; // @[util.scala:505:22] reg [5:0] uops_4_pc_lob; // @[util.scala:505:22] reg uops_4_taken; // @[util.scala:505:22] reg uops_4_imm_rename; // @[util.scala:505:22] reg [2:0] uops_4_imm_sel; // @[util.scala:505:22] reg [4:0] uops_4_pimm; // @[util.scala:505:22] reg [19:0] uops_4_imm_packed; // @[util.scala:505:22] reg [1:0] uops_4_op1_sel; // @[util.scala:505:22] reg [2:0] uops_4_op2_sel; // @[util.scala:505:22] reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_4_fp_ctrl_wen; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_4_fp_ctrl_toint; // @[util.scala:505:22] reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_4_fp_ctrl_fma; // @[util.scala:505:22] reg uops_4_fp_ctrl_div; // @[util.scala:505:22] reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_4_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_4_rob_idx; // @[util.scala:505:22] reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_4_stq_idx; // @[util.scala:505:22] reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_4_pdst; // @[util.scala:505:22] reg [5:0] uops_4_prs1; // @[util.scala:505:22] reg [5:0] uops_4_prs2; // @[util.scala:505:22] reg [5:0] uops_4_prs3; // @[util.scala:505:22] reg [3:0] uops_4_ppred; // @[util.scala:505:22] reg uops_4_prs1_busy; // @[util.scala:505:22] reg uops_4_prs2_busy; // @[util.scala:505:22] reg uops_4_prs3_busy; // @[util.scala:505:22] reg uops_4_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_4_stale_pdst; // @[util.scala:505:22] reg uops_4_exception; // @[util.scala:505:22] reg [63:0] uops_4_exc_cause; // @[util.scala:505:22] reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_4_mem_size; // @[util.scala:505:22] reg uops_4_mem_signed; // @[util.scala:505:22] reg uops_4_uses_ldq; // @[util.scala:505:22] reg uops_4_uses_stq; // @[util.scala:505:22] reg uops_4_is_unique; // @[util.scala:505:22] reg uops_4_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22] reg uops_4_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_4_ldst; // @[util.scala:505:22] reg [5:0] uops_4_lrs1; // @[util.scala:505:22] reg [5:0] uops_4_lrs2; // @[util.scala:505:22] reg [5:0] uops_4_lrs3; // @[util.scala:505:22] reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22] reg uops_4_frs3_en; // @[util.scala:505:22] reg uops_4_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_4_fcn_op; // @[util.scala:505:22] reg uops_4_fp_val; // @[util.scala:505:22] reg [2:0] uops_4_fp_rm; // @[util.scala:505:22] reg [1:0] uops_4_fp_typ; // @[util.scala:505:22] reg uops_4_xcpt_pf_if; // @[util.scala:505:22] reg uops_4_xcpt_ae_if; // @[util.scala:505:22] reg uops_4_xcpt_ma_if; // @[util.scala:505:22] reg uops_4_bp_debug_if; // @[util.scala:505:22] reg uops_4_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_5_inst; // @[util.scala:505:22] reg [31:0] uops_5_debug_inst; // @[util.scala:505:22] reg uops_5_is_rvc; // @[util.scala:505:22] reg [33:0] uops_5_debug_pc; // @[util.scala:505:22] reg uops_5_iq_type_0; // @[util.scala:505:22] reg uops_5_iq_type_1; // @[util.scala:505:22] reg uops_5_iq_type_2; // @[util.scala:505:22] reg uops_5_iq_type_3; // @[util.scala:505:22] reg uops_5_fu_code_0; // @[util.scala:505:22] reg uops_5_fu_code_1; // @[util.scala:505:22] reg uops_5_fu_code_2; // @[util.scala:505:22] reg uops_5_fu_code_3; // @[util.scala:505:22] reg uops_5_fu_code_4; // @[util.scala:505:22] reg uops_5_fu_code_5; // @[util.scala:505:22] reg uops_5_fu_code_6; // @[util.scala:505:22] reg uops_5_fu_code_7; // @[util.scala:505:22] reg uops_5_fu_code_8; // @[util.scala:505:22] reg uops_5_fu_code_9; // @[util.scala:505:22] reg uops_5_iw_issued; // @[util.scala:505:22] reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_5_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_5_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_5_br_mask; // @[util.scala:505:22] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_5_br_tag; // @[util.scala:505:22] reg [3:0] uops_5_br_type; // @[util.scala:505:22] reg uops_5_is_sfb; // @[util.scala:505:22] reg uops_5_is_fence; // @[util.scala:505:22] reg uops_5_is_fencei; // @[util.scala:505:22] reg uops_5_is_sfence; // @[util.scala:505:22] reg uops_5_is_amo; // @[util.scala:505:22] reg uops_5_is_eret; // @[util.scala:505:22] reg uops_5_is_sys_pc2epc; // @[util.scala:505:22] reg uops_5_is_rocc; // @[util.scala:505:22] reg uops_5_is_mov; // @[util.scala:505:22] reg [3:0] uops_5_ftq_idx; // @[util.scala:505:22] reg uops_5_edge_inst; // @[util.scala:505:22] reg [5:0] uops_5_pc_lob; // @[util.scala:505:22] reg uops_5_taken; // @[util.scala:505:22] reg uops_5_imm_rename; // @[util.scala:505:22] reg [2:0] uops_5_imm_sel; // @[util.scala:505:22] reg [4:0] uops_5_pimm; // @[util.scala:505:22] reg [19:0] uops_5_imm_packed; // @[util.scala:505:22] reg [1:0] uops_5_op1_sel; // @[util.scala:505:22] reg [2:0] uops_5_op2_sel; // @[util.scala:505:22] reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_5_fp_ctrl_wen; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_5_fp_ctrl_toint; // @[util.scala:505:22] reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_5_fp_ctrl_fma; // @[util.scala:505:22] reg uops_5_fp_ctrl_div; // @[util.scala:505:22] reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_5_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_5_rob_idx; // @[util.scala:505:22] reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_5_stq_idx; // @[util.scala:505:22] reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_5_pdst; // @[util.scala:505:22] reg [5:0] uops_5_prs1; // @[util.scala:505:22] reg [5:0] uops_5_prs2; // @[util.scala:505:22] reg [5:0] uops_5_prs3; // @[util.scala:505:22] reg [3:0] uops_5_ppred; // @[util.scala:505:22] reg uops_5_prs1_busy; // @[util.scala:505:22] reg uops_5_prs2_busy; // @[util.scala:505:22] reg uops_5_prs3_busy; // @[util.scala:505:22] reg uops_5_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_5_stale_pdst; // @[util.scala:505:22] reg uops_5_exception; // @[util.scala:505:22] reg [63:0] uops_5_exc_cause; // @[util.scala:505:22] reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_5_mem_size; // @[util.scala:505:22] reg uops_5_mem_signed; // @[util.scala:505:22] reg uops_5_uses_ldq; // @[util.scala:505:22] reg uops_5_uses_stq; // @[util.scala:505:22] reg uops_5_is_unique; // @[util.scala:505:22] reg uops_5_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22] reg uops_5_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_5_ldst; // @[util.scala:505:22] reg [5:0] uops_5_lrs1; // @[util.scala:505:22] reg [5:0] uops_5_lrs2; // @[util.scala:505:22] reg [5:0] uops_5_lrs3; // @[util.scala:505:22] reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22] reg uops_5_frs3_en; // @[util.scala:505:22] reg uops_5_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_5_fcn_op; // @[util.scala:505:22] reg uops_5_fp_val; // @[util.scala:505:22] reg [2:0] uops_5_fp_rm; // @[util.scala:505:22] reg [1:0] uops_5_fp_typ; // @[util.scala:505:22] reg uops_5_xcpt_pf_if; // @[util.scala:505:22] reg uops_5_xcpt_ae_if; // @[util.scala:505:22] reg uops_5_xcpt_ma_if; // @[util.scala:505:22] reg uops_5_bp_debug_if; // @[util.scala:505:22] reg uops_5_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_6_inst; // @[util.scala:505:22] reg [31:0] uops_6_debug_inst; // @[util.scala:505:22] reg uops_6_is_rvc; // @[util.scala:505:22] reg [33:0] uops_6_debug_pc; // @[util.scala:505:22] reg uops_6_iq_type_0; // @[util.scala:505:22] reg uops_6_iq_type_1; // @[util.scala:505:22] reg uops_6_iq_type_2; // @[util.scala:505:22] reg uops_6_iq_type_3; // @[util.scala:505:22] reg uops_6_fu_code_0; // @[util.scala:505:22] reg uops_6_fu_code_1; // @[util.scala:505:22] reg uops_6_fu_code_2; // @[util.scala:505:22] reg uops_6_fu_code_3; // @[util.scala:505:22] reg uops_6_fu_code_4; // @[util.scala:505:22] reg uops_6_fu_code_5; // @[util.scala:505:22] reg uops_6_fu_code_6; // @[util.scala:505:22] reg uops_6_fu_code_7; // @[util.scala:505:22] reg uops_6_fu_code_8; // @[util.scala:505:22] reg uops_6_fu_code_9; // @[util.scala:505:22] reg uops_6_iw_issued; // @[util.scala:505:22] reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_6_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_6_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_6_br_mask; // @[util.scala:505:22] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_6_br_tag; // @[util.scala:505:22] reg [3:0] uops_6_br_type; // @[util.scala:505:22] reg uops_6_is_sfb; // @[util.scala:505:22] reg uops_6_is_fence; // @[util.scala:505:22] reg uops_6_is_fencei; // @[util.scala:505:22] reg uops_6_is_sfence; // @[util.scala:505:22] reg uops_6_is_amo; // @[util.scala:505:22] reg uops_6_is_eret; // @[util.scala:505:22] reg uops_6_is_sys_pc2epc; // @[util.scala:505:22] reg uops_6_is_rocc; // @[util.scala:505:22] reg uops_6_is_mov; // @[util.scala:505:22] reg [3:0] uops_6_ftq_idx; // @[util.scala:505:22] reg uops_6_edge_inst; // @[util.scala:505:22] reg [5:0] uops_6_pc_lob; // @[util.scala:505:22] reg uops_6_taken; // @[util.scala:505:22] reg uops_6_imm_rename; // @[util.scala:505:22] reg [2:0] uops_6_imm_sel; // @[util.scala:505:22] reg [4:0] uops_6_pimm; // @[util.scala:505:22] reg [19:0] uops_6_imm_packed; // @[util.scala:505:22] reg [1:0] uops_6_op1_sel; // @[util.scala:505:22] reg [2:0] uops_6_op2_sel; // @[util.scala:505:22] reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_6_fp_ctrl_wen; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_6_fp_ctrl_toint; // @[util.scala:505:22] reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_6_fp_ctrl_fma; // @[util.scala:505:22] reg uops_6_fp_ctrl_div; // @[util.scala:505:22] reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_6_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_6_rob_idx; // @[util.scala:505:22] reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_6_stq_idx; // @[util.scala:505:22] reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_6_pdst; // @[util.scala:505:22] reg [5:0] uops_6_prs1; // @[util.scala:505:22] reg [5:0] uops_6_prs2; // @[util.scala:505:22] reg [5:0] uops_6_prs3; // @[util.scala:505:22] reg [3:0] uops_6_ppred; // @[util.scala:505:22] reg uops_6_prs1_busy; // @[util.scala:505:22] reg uops_6_prs2_busy; // @[util.scala:505:22] reg uops_6_prs3_busy; // @[util.scala:505:22] reg uops_6_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_6_stale_pdst; // @[util.scala:505:22] reg uops_6_exception; // @[util.scala:505:22] reg [63:0] uops_6_exc_cause; // @[util.scala:505:22] reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_6_mem_size; // @[util.scala:505:22] reg uops_6_mem_signed; // @[util.scala:505:22] reg uops_6_uses_ldq; // @[util.scala:505:22] reg uops_6_uses_stq; // @[util.scala:505:22] reg uops_6_is_unique; // @[util.scala:505:22] reg uops_6_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22] reg uops_6_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_6_ldst; // @[util.scala:505:22] reg [5:0] uops_6_lrs1; // @[util.scala:505:22] reg [5:0] uops_6_lrs2; // @[util.scala:505:22] reg [5:0] uops_6_lrs3; // @[util.scala:505:22] reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22] reg uops_6_frs3_en; // @[util.scala:505:22] reg uops_6_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_6_fcn_op; // @[util.scala:505:22] reg uops_6_fp_val; // @[util.scala:505:22] reg [2:0] uops_6_fp_rm; // @[util.scala:505:22] reg [1:0] uops_6_fp_typ; // @[util.scala:505:22] reg uops_6_xcpt_pf_if; // @[util.scala:505:22] reg uops_6_xcpt_ae_if; // @[util.scala:505:22] reg uops_6_xcpt_ma_if; // @[util.scala:505:22] reg uops_6_bp_debug_if; // @[util.scala:505:22] reg uops_6_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_7_inst; // @[util.scala:505:22] reg [31:0] uops_7_debug_inst; // @[util.scala:505:22] reg uops_7_is_rvc; // @[util.scala:505:22] reg [33:0] uops_7_debug_pc; // @[util.scala:505:22] reg uops_7_iq_type_0; // @[util.scala:505:22] reg uops_7_iq_type_1; // @[util.scala:505:22] reg uops_7_iq_type_2; // @[util.scala:505:22] reg uops_7_iq_type_3; // @[util.scala:505:22] reg uops_7_fu_code_0; // @[util.scala:505:22] reg uops_7_fu_code_1; // @[util.scala:505:22] reg uops_7_fu_code_2; // @[util.scala:505:22] reg uops_7_fu_code_3; // @[util.scala:505:22] reg uops_7_fu_code_4; // @[util.scala:505:22] reg uops_7_fu_code_5; // @[util.scala:505:22] reg uops_7_fu_code_6; // @[util.scala:505:22] reg uops_7_fu_code_7; // @[util.scala:505:22] reg uops_7_fu_code_8; // @[util.scala:505:22] reg uops_7_fu_code_9; // @[util.scala:505:22] reg uops_7_iw_issued; // @[util.scala:505:22] reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_7_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_7_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_7_br_mask; // @[util.scala:505:22] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_7_br_tag; // @[util.scala:505:22] reg [3:0] uops_7_br_type; // @[util.scala:505:22] reg uops_7_is_sfb; // @[util.scala:505:22] reg uops_7_is_fence; // @[util.scala:505:22] reg uops_7_is_fencei; // @[util.scala:505:22] reg uops_7_is_sfence; // @[util.scala:505:22] reg uops_7_is_amo; // @[util.scala:505:22] reg uops_7_is_eret; // @[util.scala:505:22] reg uops_7_is_sys_pc2epc; // @[util.scala:505:22] reg uops_7_is_rocc; // @[util.scala:505:22] reg uops_7_is_mov; // @[util.scala:505:22] reg [3:0] uops_7_ftq_idx; // @[util.scala:505:22] reg uops_7_edge_inst; // @[util.scala:505:22] reg [5:0] uops_7_pc_lob; // @[util.scala:505:22] reg uops_7_taken; // @[util.scala:505:22] reg uops_7_imm_rename; // @[util.scala:505:22] reg [2:0] uops_7_imm_sel; // @[util.scala:505:22] reg [4:0] uops_7_pimm; // @[util.scala:505:22] reg [19:0] uops_7_imm_packed; // @[util.scala:505:22] reg [1:0] uops_7_op1_sel; // @[util.scala:505:22] reg [2:0] uops_7_op2_sel; // @[util.scala:505:22] reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_7_fp_ctrl_wen; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_7_fp_ctrl_toint; // @[util.scala:505:22] reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_7_fp_ctrl_fma; // @[util.scala:505:22] reg uops_7_fp_ctrl_div; // @[util.scala:505:22] reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_7_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_7_rob_idx; // @[util.scala:505:22] reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_7_stq_idx; // @[util.scala:505:22] reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_7_pdst; // @[util.scala:505:22] reg [5:0] uops_7_prs1; // @[util.scala:505:22] reg [5:0] uops_7_prs2; // @[util.scala:505:22] reg [5:0] uops_7_prs3; // @[util.scala:505:22] reg [3:0] uops_7_ppred; // @[util.scala:505:22] reg uops_7_prs1_busy; // @[util.scala:505:22] reg uops_7_prs2_busy; // @[util.scala:505:22] reg uops_7_prs3_busy; // @[util.scala:505:22] reg uops_7_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_7_stale_pdst; // @[util.scala:505:22] reg uops_7_exception; // @[util.scala:505:22] reg [63:0] uops_7_exc_cause; // @[util.scala:505:22] reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_7_mem_size; // @[util.scala:505:22] reg uops_7_mem_signed; // @[util.scala:505:22] reg uops_7_uses_ldq; // @[util.scala:505:22] reg uops_7_uses_stq; // @[util.scala:505:22] reg uops_7_is_unique; // @[util.scala:505:22] reg uops_7_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22] reg uops_7_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_7_ldst; // @[util.scala:505:22] reg [5:0] uops_7_lrs1; // @[util.scala:505:22] reg [5:0] uops_7_lrs2; // @[util.scala:505:22] reg [5:0] uops_7_lrs3; // @[util.scala:505:22] reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22] reg uops_7_frs3_en; // @[util.scala:505:22] reg uops_7_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_7_fcn_op; // @[util.scala:505:22] reg uops_7_fp_val; // @[util.scala:505:22] reg [2:0] uops_7_fp_rm; // @[util.scala:505:22] reg [1:0] uops_7_fp_typ; // @[util.scala:505:22] reg uops_7_xcpt_pf_if; // @[util.scala:505:22] reg uops_7_xcpt_ae_if; // @[util.scala:505:22] reg uops_7_xcpt_ma_if; // @[util.scala:505:22] reg uops_7_bp_debug_if; // @[util.scala:505:22] reg uops_7_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_8_inst; // @[util.scala:505:22] reg [31:0] uops_8_debug_inst; // @[util.scala:505:22] reg uops_8_is_rvc; // @[util.scala:505:22] reg [33:0] uops_8_debug_pc; // @[util.scala:505:22] reg uops_8_iq_type_0; // @[util.scala:505:22] reg uops_8_iq_type_1; // @[util.scala:505:22] reg uops_8_iq_type_2; // @[util.scala:505:22] reg uops_8_iq_type_3; // @[util.scala:505:22] reg uops_8_fu_code_0; // @[util.scala:505:22] reg uops_8_fu_code_1; // @[util.scala:505:22] reg uops_8_fu_code_2; // @[util.scala:505:22] reg uops_8_fu_code_3; // @[util.scala:505:22] reg uops_8_fu_code_4; // @[util.scala:505:22] reg uops_8_fu_code_5; // @[util.scala:505:22] reg uops_8_fu_code_6; // @[util.scala:505:22] reg uops_8_fu_code_7; // @[util.scala:505:22] reg uops_8_fu_code_8; // @[util.scala:505:22] reg uops_8_fu_code_9; // @[util.scala:505:22] reg uops_8_iw_issued; // @[util.scala:505:22] reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_8_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_8_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_8_br_mask; // @[util.scala:505:22] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_8_br_tag; // @[util.scala:505:22] reg [3:0] uops_8_br_type; // @[util.scala:505:22] reg uops_8_is_sfb; // @[util.scala:505:22] reg uops_8_is_fence; // @[util.scala:505:22] reg uops_8_is_fencei; // @[util.scala:505:22] reg uops_8_is_sfence; // @[util.scala:505:22] reg uops_8_is_amo; // @[util.scala:505:22] reg uops_8_is_eret; // @[util.scala:505:22] reg uops_8_is_sys_pc2epc; // @[util.scala:505:22] reg uops_8_is_rocc; // @[util.scala:505:22] reg uops_8_is_mov; // @[util.scala:505:22] reg [3:0] uops_8_ftq_idx; // @[util.scala:505:22] reg uops_8_edge_inst; // @[util.scala:505:22] reg [5:0] uops_8_pc_lob; // @[util.scala:505:22] reg uops_8_taken; // @[util.scala:505:22] reg uops_8_imm_rename; // @[util.scala:505:22] reg [2:0] uops_8_imm_sel; // @[util.scala:505:22] reg [4:0] uops_8_pimm; // @[util.scala:505:22] reg [19:0] uops_8_imm_packed; // @[util.scala:505:22] reg [1:0] uops_8_op1_sel; // @[util.scala:505:22] reg [2:0] uops_8_op2_sel; // @[util.scala:505:22] reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_8_fp_ctrl_wen; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_8_fp_ctrl_toint; // @[util.scala:505:22] reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_8_fp_ctrl_fma; // @[util.scala:505:22] reg uops_8_fp_ctrl_div; // @[util.scala:505:22] reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_8_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_8_rob_idx; // @[util.scala:505:22] reg [3:0] uops_8_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_8_stq_idx; // @[util.scala:505:22] reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_8_pdst; // @[util.scala:505:22] reg [5:0] uops_8_prs1; // @[util.scala:505:22] reg [5:0] uops_8_prs2; // @[util.scala:505:22] reg [5:0] uops_8_prs3; // @[util.scala:505:22] reg [3:0] uops_8_ppred; // @[util.scala:505:22] reg uops_8_prs1_busy; // @[util.scala:505:22] reg uops_8_prs2_busy; // @[util.scala:505:22] reg uops_8_prs3_busy; // @[util.scala:505:22] reg uops_8_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_8_stale_pdst; // @[util.scala:505:22] reg uops_8_exception; // @[util.scala:505:22] reg [63:0] uops_8_exc_cause; // @[util.scala:505:22] reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_8_mem_size; // @[util.scala:505:22] reg uops_8_mem_signed; // @[util.scala:505:22] reg uops_8_uses_ldq; // @[util.scala:505:22] reg uops_8_uses_stq; // @[util.scala:505:22] reg uops_8_is_unique; // @[util.scala:505:22] reg uops_8_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22] reg uops_8_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_8_ldst; // @[util.scala:505:22] reg [5:0] uops_8_lrs1; // @[util.scala:505:22] reg [5:0] uops_8_lrs2; // @[util.scala:505:22] reg [5:0] uops_8_lrs3; // @[util.scala:505:22] reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22] reg uops_8_frs3_en; // @[util.scala:505:22] reg uops_8_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_8_fcn_op; // @[util.scala:505:22] reg uops_8_fp_val; // @[util.scala:505:22] reg [2:0] uops_8_fp_rm; // @[util.scala:505:22] reg [1:0] uops_8_fp_typ; // @[util.scala:505:22] reg uops_8_xcpt_pf_if; // @[util.scala:505:22] reg uops_8_xcpt_ae_if; // @[util.scala:505:22] reg uops_8_xcpt_ma_if; // @[util.scala:505:22] reg uops_8_bp_debug_if; // @[util.scala:505:22] reg uops_8_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_9_inst; // @[util.scala:505:22] reg [31:0] uops_9_debug_inst; // @[util.scala:505:22] reg uops_9_is_rvc; // @[util.scala:505:22] reg [33:0] uops_9_debug_pc; // @[util.scala:505:22] reg uops_9_iq_type_0; // @[util.scala:505:22] reg uops_9_iq_type_1; // @[util.scala:505:22] reg uops_9_iq_type_2; // @[util.scala:505:22] reg uops_9_iq_type_3; // @[util.scala:505:22] reg uops_9_fu_code_0; // @[util.scala:505:22] reg uops_9_fu_code_1; // @[util.scala:505:22] reg uops_9_fu_code_2; // @[util.scala:505:22] reg uops_9_fu_code_3; // @[util.scala:505:22] reg uops_9_fu_code_4; // @[util.scala:505:22] reg uops_9_fu_code_5; // @[util.scala:505:22] reg uops_9_fu_code_6; // @[util.scala:505:22] reg uops_9_fu_code_7; // @[util.scala:505:22] reg uops_9_fu_code_8; // @[util.scala:505:22] reg uops_9_fu_code_9; // @[util.scala:505:22] reg uops_9_iw_issued; // @[util.scala:505:22] reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_9_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_9_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_9_br_mask; // @[util.scala:505:22] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_9_br_tag; // @[util.scala:505:22] reg [3:0] uops_9_br_type; // @[util.scala:505:22] reg uops_9_is_sfb; // @[util.scala:505:22] reg uops_9_is_fence; // @[util.scala:505:22] reg uops_9_is_fencei; // @[util.scala:505:22] reg uops_9_is_sfence; // @[util.scala:505:22] reg uops_9_is_amo; // @[util.scala:505:22] reg uops_9_is_eret; // @[util.scala:505:22] reg uops_9_is_sys_pc2epc; // @[util.scala:505:22] reg uops_9_is_rocc; // @[util.scala:505:22] reg uops_9_is_mov; // @[util.scala:505:22] reg [3:0] uops_9_ftq_idx; // @[util.scala:505:22] reg uops_9_edge_inst; // @[util.scala:505:22] reg [5:0] uops_9_pc_lob; // @[util.scala:505:22] reg uops_9_taken; // @[util.scala:505:22] reg uops_9_imm_rename; // @[util.scala:505:22] reg [2:0] uops_9_imm_sel; // @[util.scala:505:22] reg [4:0] uops_9_pimm; // @[util.scala:505:22] reg [19:0] uops_9_imm_packed; // @[util.scala:505:22] reg [1:0] uops_9_op1_sel; // @[util.scala:505:22] reg [2:0] uops_9_op2_sel; // @[util.scala:505:22] reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_9_fp_ctrl_wen; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_9_fp_ctrl_toint; // @[util.scala:505:22] reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_9_fp_ctrl_fma; // @[util.scala:505:22] reg uops_9_fp_ctrl_div; // @[util.scala:505:22] reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_9_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_9_rob_idx; // @[util.scala:505:22] reg [3:0] uops_9_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_9_stq_idx; // @[util.scala:505:22] reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_9_pdst; // @[util.scala:505:22] reg [5:0] uops_9_prs1; // @[util.scala:505:22] reg [5:0] uops_9_prs2; // @[util.scala:505:22] reg [5:0] uops_9_prs3; // @[util.scala:505:22] reg [3:0] uops_9_ppred; // @[util.scala:505:22] reg uops_9_prs1_busy; // @[util.scala:505:22] reg uops_9_prs2_busy; // @[util.scala:505:22] reg uops_9_prs3_busy; // @[util.scala:505:22] reg uops_9_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_9_stale_pdst; // @[util.scala:505:22] reg uops_9_exception; // @[util.scala:505:22] reg [63:0] uops_9_exc_cause; // @[util.scala:505:22] reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_9_mem_size; // @[util.scala:505:22] reg uops_9_mem_signed; // @[util.scala:505:22] reg uops_9_uses_ldq; // @[util.scala:505:22] reg uops_9_uses_stq; // @[util.scala:505:22] reg uops_9_is_unique; // @[util.scala:505:22] reg uops_9_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22] reg uops_9_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_9_ldst; // @[util.scala:505:22] reg [5:0] uops_9_lrs1; // @[util.scala:505:22] reg [5:0] uops_9_lrs2; // @[util.scala:505:22] reg [5:0] uops_9_lrs3; // @[util.scala:505:22] reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22] reg uops_9_frs3_en; // @[util.scala:505:22] reg uops_9_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_9_fcn_op; // @[util.scala:505:22] reg uops_9_fp_val; // @[util.scala:505:22] reg [2:0] uops_9_fp_rm; // @[util.scala:505:22] reg [1:0] uops_9_fp_typ; // @[util.scala:505:22] reg uops_9_xcpt_pf_if; // @[util.scala:505:22] reg uops_9_xcpt_ae_if; // @[util.scala:505:22] reg uops_9_xcpt_ma_if; // @[util.scala:505:22] reg uops_9_bp_debug_if; // @[util.scala:505:22] reg uops_9_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_10_inst; // @[util.scala:505:22] reg [31:0] uops_10_debug_inst; // @[util.scala:505:22] reg uops_10_is_rvc; // @[util.scala:505:22] reg [33:0] uops_10_debug_pc; // @[util.scala:505:22] reg uops_10_iq_type_0; // @[util.scala:505:22] reg uops_10_iq_type_1; // @[util.scala:505:22] reg uops_10_iq_type_2; // @[util.scala:505:22] reg uops_10_iq_type_3; // @[util.scala:505:22] reg uops_10_fu_code_0; // @[util.scala:505:22] reg uops_10_fu_code_1; // @[util.scala:505:22] reg uops_10_fu_code_2; // @[util.scala:505:22] reg uops_10_fu_code_3; // @[util.scala:505:22] reg uops_10_fu_code_4; // @[util.scala:505:22] reg uops_10_fu_code_5; // @[util.scala:505:22] reg uops_10_fu_code_6; // @[util.scala:505:22] reg uops_10_fu_code_7; // @[util.scala:505:22] reg uops_10_fu_code_8; // @[util.scala:505:22] reg uops_10_fu_code_9; // @[util.scala:505:22] reg uops_10_iw_issued; // @[util.scala:505:22] reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_10_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_10_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_10_br_mask; // @[util.scala:505:22] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_10_br_tag; // @[util.scala:505:22] reg [3:0] uops_10_br_type; // @[util.scala:505:22] reg uops_10_is_sfb; // @[util.scala:505:22] reg uops_10_is_fence; // @[util.scala:505:22] reg uops_10_is_fencei; // @[util.scala:505:22] reg uops_10_is_sfence; // @[util.scala:505:22] reg uops_10_is_amo; // @[util.scala:505:22] reg uops_10_is_eret; // @[util.scala:505:22] reg uops_10_is_sys_pc2epc; // @[util.scala:505:22] reg uops_10_is_rocc; // @[util.scala:505:22] reg uops_10_is_mov; // @[util.scala:505:22] reg [3:0] uops_10_ftq_idx; // @[util.scala:505:22] reg uops_10_edge_inst; // @[util.scala:505:22] reg [5:0] uops_10_pc_lob; // @[util.scala:505:22] reg uops_10_taken; // @[util.scala:505:22] reg uops_10_imm_rename; // @[util.scala:505:22] reg [2:0] uops_10_imm_sel; // @[util.scala:505:22] reg [4:0] uops_10_pimm; // @[util.scala:505:22] reg [19:0] uops_10_imm_packed; // @[util.scala:505:22] reg [1:0] uops_10_op1_sel; // @[util.scala:505:22] reg [2:0] uops_10_op2_sel; // @[util.scala:505:22] reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_10_fp_ctrl_wen; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_10_fp_ctrl_toint; // @[util.scala:505:22] reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_10_fp_ctrl_fma; // @[util.scala:505:22] reg uops_10_fp_ctrl_div; // @[util.scala:505:22] reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_10_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_10_rob_idx; // @[util.scala:505:22] reg [3:0] uops_10_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_10_stq_idx; // @[util.scala:505:22] reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_10_pdst; // @[util.scala:505:22] reg [5:0] uops_10_prs1; // @[util.scala:505:22] reg [5:0] uops_10_prs2; // @[util.scala:505:22] reg [5:0] uops_10_prs3; // @[util.scala:505:22] reg [3:0] uops_10_ppred; // @[util.scala:505:22] reg uops_10_prs1_busy; // @[util.scala:505:22] reg uops_10_prs2_busy; // @[util.scala:505:22] reg uops_10_prs3_busy; // @[util.scala:505:22] reg uops_10_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_10_stale_pdst; // @[util.scala:505:22] reg uops_10_exception; // @[util.scala:505:22] reg [63:0] uops_10_exc_cause; // @[util.scala:505:22] reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_10_mem_size; // @[util.scala:505:22] reg uops_10_mem_signed; // @[util.scala:505:22] reg uops_10_uses_ldq; // @[util.scala:505:22] reg uops_10_uses_stq; // @[util.scala:505:22] reg uops_10_is_unique; // @[util.scala:505:22] reg uops_10_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22] reg uops_10_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_10_ldst; // @[util.scala:505:22] reg [5:0] uops_10_lrs1; // @[util.scala:505:22] reg [5:0] uops_10_lrs2; // @[util.scala:505:22] reg [5:0] uops_10_lrs3; // @[util.scala:505:22] reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22] reg uops_10_frs3_en; // @[util.scala:505:22] reg uops_10_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_10_fcn_op; // @[util.scala:505:22] reg uops_10_fp_val; // @[util.scala:505:22] reg [2:0] uops_10_fp_rm; // @[util.scala:505:22] reg [1:0] uops_10_fp_typ; // @[util.scala:505:22] reg uops_10_xcpt_pf_if; // @[util.scala:505:22] reg uops_10_xcpt_ae_if; // @[util.scala:505:22] reg uops_10_xcpt_ma_if; // @[util.scala:505:22] reg uops_10_bp_debug_if; // @[util.scala:505:22] reg uops_10_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_11_inst; // @[util.scala:505:22] reg [31:0] uops_11_debug_inst; // @[util.scala:505:22] reg uops_11_is_rvc; // @[util.scala:505:22] reg [33:0] uops_11_debug_pc; // @[util.scala:505:22] reg uops_11_iq_type_0; // @[util.scala:505:22] reg uops_11_iq_type_1; // @[util.scala:505:22] reg uops_11_iq_type_2; // @[util.scala:505:22] reg uops_11_iq_type_3; // @[util.scala:505:22] reg uops_11_fu_code_0; // @[util.scala:505:22] reg uops_11_fu_code_1; // @[util.scala:505:22] reg uops_11_fu_code_2; // @[util.scala:505:22] reg uops_11_fu_code_3; // @[util.scala:505:22] reg uops_11_fu_code_4; // @[util.scala:505:22] reg uops_11_fu_code_5; // @[util.scala:505:22] reg uops_11_fu_code_6; // @[util.scala:505:22] reg uops_11_fu_code_7; // @[util.scala:505:22] reg uops_11_fu_code_8; // @[util.scala:505:22] reg uops_11_fu_code_9; // @[util.scala:505:22] reg uops_11_iw_issued; // @[util.scala:505:22] reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_11_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_11_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_11_br_mask; // @[util.scala:505:22] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_11_br_tag; // @[util.scala:505:22] reg [3:0] uops_11_br_type; // @[util.scala:505:22] reg uops_11_is_sfb; // @[util.scala:505:22] reg uops_11_is_fence; // @[util.scala:505:22] reg uops_11_is_fencei; // @[util.scala:505:22] reg uops_11_is_sfence; // @[util.scala:505:22] reg uops_11_is_amo; // @[util.scala:505:22] reg uops_11_is_eret; // @[util.scala:505:22] reg uops_11_is_sys_pc2epc; // @[util.scala:505:22] reg uops_11_is_rocc; // @[util.scala:505:22] reg uops_11_is_mov; // @[util.scala:505:22] reg [3:0] uops_11_ftq_idx; // @[util.scala:505:22] reg uops_11_edge_inst; // @[util.scala:505:22] reg [5:0] uops_11_pc_lob; // @[util.scala:505:22] reg uops_11_taken; // @[util.scala:505:22] reg uops_11_imm_rename; // @[util.scala:505:22] reg [2:0] uops_11_imm_sel; // @[util.scala:505:22] reg [4:0] uops_11_pimm; // @[util.scala:505:22] reg [19:0] uops_11_imm_packed; // @[util.scala:505:22] reg [1:0] uops_11_op1_sel; // @[util.scala:505:22] reg [2:0] uops_11_op2_sel; // @[util.scala:505:22] reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_11_fp_ctrl_wen; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_11_fp_ctrl_toint; // @[util.scala:505:22] reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_11_fp_ctrl_fma; // @[util.scala:505:22] reg uops_11_fp_ctrl_div; // @[util.scala:505:22] reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_11_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_11_rob_idx; // @[util.scala:505:22] reg [3:0] uops_11_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_11_stq_idx; // @[util.scala:505:22] reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_11_pdst; // @[util.scala:505:22] reg [5:0] uops_11_prs1; // @[util.scala:505:22] reg [5:0] uops_11_prs2; // @[util.scala:505:22] reg [5:0] uops_11_prs3; // @[util.scala:505:22] reg [3:0] uops_11_ppred; // @[util.scala:505:22] reg uops_11_prs1_busy; // @[util.scala:505:22] reg uops_11_prs2_busy; // @[util.scala:505:22] reg uops_11_prs3_busy; // @[util.scala:505:22] reg uops_11_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_11_stale_pdst; // @[util.scala:505:22] reg uops_11_exception; // @[util.scala:505:22] reg [63:0] uops_11_exc_cause; // @[util.scala:505:22] reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_11_mem_size; // @[util.scala:505:22] reg uops_11_mem_signed; // @[util.scala:505:22] reg uops_11_uses_ldq; // @[util.scala:505:22] reg uops_11_uses_stq; // @[util.scala:505:22] reg uops_11_is_unique; // @[util.scala:505:22] reg uops_11_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22] reg uops_11_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_11_ldst; // @[util.scala:505:22] reg [5:0] uops_11_lrs1; // @[util.scala:505:22] reg [5:0] uops_11_lrs2; // @[util.scala:505:22] reg [5:0] uops_11_lrs3; // @[util.scala:505:22] reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22] reg uops_11_frs3_en; // @[util.scala:505:22] reg uops_11_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_11_fcn_op; // @[util.scala:505:22] reg uops_11_fp_val; // @[util.scala:505:22] reg [2:0] uops_11_fp_rm; // @[util.scala:505:22] reg [1:0] uops_11_fp_typ; // @[util.scala:505:22] reg uops_11_xcpt_pf_if; // @[util.scala:505:22] reg uops_11_xcpt_ae_if; // @[util.scala:505:22] reg uops_11_xcpt_ma_if; // @[util.scala:505:22] reg uops_11_bp_debug_if; // @[util.scala:505:22] reg uops_11_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_12_inst; // @[util.scala:505:22] reg [31:0] uops_12_debug_inst; // @[util.scala:505:22] reg uops_12_is_rvc; // @[util.scala:505:22] reg [33:0] uops_12_debug_pc; // @[util.scala:505:22] reg uops_12_iq_type_0; // @[util.scala:505:22] reg uops_12_iq_type_1; // @[util.scala:505:22] reg uops_12_iq_type_2; // @[util.scala:505:22] reg uops_12_iq_type_3; // @[util.scala:505:22] reg uops_12_fu_code_0; // @[util.scala:505:22] reg uops_12_fu_code_1; // @[util.scala:505:22] reg uops_12_fu_code_2; // @[util.scala:505:22] reg uops_12_fu_code_3; // @[util.scala:505:22] reg uops_12_fu_code_4; // @[util.scala:505:22] reg uops_12_fu_code_5; // @[util.scala:505:22] reg uops_12_fu_code_6; // @[util.scala:505:22] reg uops_12_fu_code_7; // @[util.scala:505:22] reg uops_12_fu_code_8; // @[util.scala:505:22] reg uops_12_fu_code_9; // @[util.scala:505:22] reg uops_12_iw_issued; // @[util.scala:505:22] reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_12_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_12_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_12_br_mask; // @[util.scala:505:22] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_12_br_tag; // @[util.scala:505:22] reg [3:0] uops_12_br_type; // @[util.scala:505:22] reg uops_12_is_sfb; // @[util.scala:505:22] reg uops_12_is_fence; // @[util.scala:505:22] reg uops_12_is_fencei; // @[util.scala:505:22] reg uops_12_is_sfence; // @[util.scala:505:22] reg uops_12_is_amo; // @[util.scala:505:22] reg uops_12_is_eret; // @[util.scala:505:22] reg uops_12_is_sys_pc2epc; // @[util.scala:505:22] reg uops_12_is_rocc; // @[util.scala:505:22] reg uops_12_is_mov; // @[util.scala:505:22] reg [3:0] uops_12_ftq_idx; // @[util.scala:505:22] reg uops_12_edge_inst; // @[util.scala:505:22] reg [5:0] uops_12_pc_lob; // @[util.scala:505:22] reg uops_12_taken; // @[util.scala:505:22] reg uops_12_imm_rename; // @[util.scala:505:22] reg [2:0] uops_12_imm_sel; // @[util.scala:505:22] reg [4:0] uops_12_pimm; // @[util.scala:505:22] reg [19:0] uops_12_imm_packed; // @[util.scala:505:22] reg [1:0] uops_12_op1_sel; // @[util.scala:505:22] reg [2:0] uops_12_op2_sel; // @[util.scala:505:22] reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_12_fp_ctrl_wen; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_12_fp_ctrl_toint; // @[util.scala:505:22] reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_12_fp_ctrl_fma; // @[util.scala:505:22] reg uops_12_fp_ctrl_div; // @[util.scala:505:22] reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_12_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_12_rob_idx; // @[util.scala:505:22] reg [3:0] uops_12_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_12_stq_idx; // @[util.scala:505:22] reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_12_pdst; // @[util.scala:505:22] reg [5:0] uops_12_prs1; // @[util.scala:505:22] reg [5:0] uops_12_prs2; // @[util.scala:505:22] reg [5:0] uops_12_prs3; // @[util.scala:505:22] reg [3:0] uops_12_ppred; // @[util.scala:505:22] reg uops_12_prs1_busy; // @[util.scala:505:22] reg uops_12_prs2_busy; // @[util.scala:505:22] reg uops_12_prs3_busy; // @[util.scala:505:22] reg uops_12_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_12_stale_pdst; // @[util.scala:505:22] reg uops_12_exception; // @[util.scala:505:22] reg [63:0] uops_12_exc_cause; // @[util.scala:505:22] reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_12_mem_size; // @[util.scala:505:22] reg uops_12_mem_signed; // @[util.scala:505:22] reg uops_12_uses_ldq; // @[util.scala:505:22] reg uops_12_uses_stq; // @[util.scala:505:22] reg uops_12_is_unique; // @[util.scala:505:22] reg uops_12_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22] reg uops_12_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_12_ldst; // @[util.scala:505:22] reg [5:0] uops_12_lrs1; // @[util.scala:505:22] reg [5:0] uops_12_lrs2; // @[util.scala:505:22] reg [5:0] uops_12_lrs3; // @[util.scala:505:22] reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22] reg uops_12_frs3_en; // @[util.scala:505:22] reg uops_12_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_12_fcn_op; // @[util.scala:505:22] reg uops_12_fp_val; // @[util.scala:505:22] reg [2:0] uops_12_fp_rm; // @[util.scala:505:22] reg [1:0] uops_12_fp_typ; // @[util.scala:505:22] reg uops_12_xcpt_pf_if; // @[util.scala:505:22] reg uops_12_xcpt_ae_if; // @[util.scala:505:22] reg uops_12_xcpt_ma_if; // @[util.scala:505:22] reg uops_12_bp_debug_if; // @[util.scala:505:22] reg uops_12_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_13_inst; // @[util.scala:505:22] reg [31:0] uops_13_debug_inst; // @[util.scala:505:22] reg uops_13_is_rvc; // @[util.scala:505:22] reg [33:0] uops_13_debug_pc; // @[util.scala:505:22] reg uops_13_iq_type_0; // @[util.scala:505:22] reg uops_13_iq_type_1; // @[util.scala:505:22] reg uops_13_iq_type_2; // @[util.scala:505:22] reg uops_13_iq_type_3; // @[util.scala:505:22] reg uops_13_fu_code_0; // @[util.scala:505:22] reg uops_13_fu_code_1; // @[util.scala:505:22] reg uops_13_fu_code_2; // @[util.scala:505:22] reg uops_13_fu_code_3; // @[util.scala:505:22] reg uops_13_fu_code_4; // @[util.scala:505:22] reg uops_13_fu_code_5; // @[util.scala:505:22] reg uops_13_fu_code_6; // @[util.scala:505:22] reg uops_13_fu_code_7; // @[util.scala:505:22] reg uops_13_fu_code_8; // @[util.scala:505:22] reg uops_13_fu_code_9; // @[util.scala:505:22] reg uops_13_iw_issued; // @[util.scala:505:22] reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_13_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_13_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_13_br_mask; // @[util.scala:505:22] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_13_br_tag; // @[util.scala:505:22] reg [3:0] uops_13_br_type; // @[util.scala:505:22] reg uops_13_is_sfb; // @[util.scala:505:22] reg uops_13_is_fence; // @[util.scala:505:22] reg uops_13_is_fencei; // @[util.scala:505:22] reg uops_13_is_sfence; // @[util.scala:505:22] reg uops_13_is_amo; // @[util.scala:505:22] reg uops_13_is_eret; // @[util.scala:505:22] reg uops_13_is_sys_pc2epc; // @[util.scala:505:22] reg uops_13_is_rocc; // @[util.scala:505:22] reg uops_13_is_mov; // @[util.scala:505:22] reg [3:0] uops_13_ftq_idx; // @[util.scala:505:22] reg uops_13_edge_inst; // @[util.scala:505:22] reg [5:0] uops_13_pc_lob; // @[util.scala:505:22] reg uops_13_taken; // @[util.scala:505:22] reg uops_13_imm_rename; // @[util.scala:505:22] reg [2:0] uops_13_imm_sel; // @[util.scala:505:22] reg [4:0] uops_13_pimm; // @[util.scala:505:22] reg [19:0] uops_13_imm_packed; // @[util.scala:505:22] reg [1:0] uops_13_op1_sel; // @[util.scala:505:22] reg [2:0] uops_13_op2_sel; // @[util.scala:505:22] reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_13_fp_ctrl_wen; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_13_fp_ctrl_toint; // @[util.scala:505:22] reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_13_fp_ctrl_fma; // @[util.scala:505:22] reg uops_13_fp_ctrl_div; // @[util.scala:505:22] reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_13_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_13_rob_idx; // @[util.scala:505:22] reg [3:0] uops_13_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_13_stq_idx; // @[util.scala:505:22] reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_13_pdst; // @[util.scala:505:22] reg [5:0] uops_13_prs1; // @[util.scala:505:22] reg [5:0] uops_13_prs2; // @[util.scala:505:22] reg [5:0] uops_13_prs3; // @[util.scala:505:22] reg [3:0] uops_13_ppred; // @[util.scala:505:22] reg uops_13_prs1_busy; // @[util.scala:505:22] reg uops_13_prs2_busy; // @[util.scala:505:22] reg uops_13_prs3_busy; // @[util.scala:505:22] reg uops_13_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_13_stale_pdst; // @[util.scala:505:22] reg uops_13_exception; // @[util.scala:505:22] reg [63:0] uops_13_exc_cause; // @[util.scala:505:22] reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_13_mem_size; // @[util.scala:505:22] reg uops_13_mem_signed; // @[util.scala:505:22] reg uops_13_uses_ldq; // @[util.scala:505:22] reg uops_13_uses_stq; // @[util.scala:505:22] reg uops_13_is_unique; // @[util.scala:505:22] reg uops_13_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22] reg uops_13_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_13_ldst; // @[util.scala:505:22] reg [5:0] uops_13_lrs1; // @[util.scala:505:22] reg [5:0] uops_13_lrs2; // @[util.scala:505:22] reg [5:0] uops_13_lrs3; // @[util.scala:505:22] reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22] reg uops_13_frs3_en; // @[util.scala:505:22] reg uops_13_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_13_fcn_op; // @[util.scala:505:22] reg uops_13_fp_val; // @[util.scala:505:22] reg [2:0] uops_13_fp_rm; // @[util.scala:505:22] reg [1:0] uops_13_fp_typ; // @[util.scala:505:22] reg uops_13_xcpt_pf_if; // @[util.scala:505:22] reg uops_13_xcpt_ae_if; // @[util.scala:505:22] reg uops_13_xcpt_ma_if; // @[util.scala:505:22] reg uops_13_bp_debug_if; // @[util.scala:505:22] reg uops_13_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_14_inst; // @[util.scala:505:22] reg [31:0] uops_14_debug_inst; // @[util.scala:505:22] reg uops_14_is_rvc; // @[util.scala:505:22] reg [33:0] uops_14_debug_pc; // @[util.scala:505:22] reg uops_14_iq_type_0; // @[util.scala:505:22] reg uops_14_iq_type_1; // @[util.scala:505:22] reg uops_14_iq_type_2; // @[util.scala:505:22] reg uops_14_iq_type_3; // @[util.scala:505:22] reg uops_14_fu_code_0; // @[util.scala:505:22] reg uops_14_fu_code_1; // @[util.scala:505:22] reg uops_14_fu_code_2; // @[util.scala:505:22] reg uops_14_fu_code_3; // @[util.scala:505:22] reg uops_14_fu_code_4; // @[util.scala:505:22] reg uops_14_fu_code_5; // @[util.scala:505:22] reg uops_14_fu_code_6; // @[util.scala:505:22] reg uops_14_fu_code_7; // @[util.scala:505:22] reg uops_14_fu_code_8; // @[util.scala:505:22] reg uops_14_fu_code_9; // @[util.scala:505:22] reg uops_14_iw_issued; // @[util.scala:505:22] reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_14_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_14_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_14_br_mask; // @[util.scala:505:22] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_14_br_tag; // @[util.scala:505:22] reg [3:0] uops_14_br_type; // @[util.scala:505:22] reg uops_14_is_sfb; // @[util.scala:505:22] reg uops_14_is_fence; // @[util.scala:505:22] reg uops_14_is_fencei; // @[util.scala:505:22] reg uops_14_is_sfence; // @[util.scala:505:22] reg uops_14_is_amo; // @[util.scala:505:22] reg uops_14_is_eret; // @[util.scala:505:22] reg uops_14_is_sys_pc2epc; // @[util.scala:505:22] reg uops_14_is_rocc; // @[util.scala:505:22] reg uops_14_is_mov; // @[util.scala:505:22] reg [3:0] uops_14_ftq_idx; // @[util.scala:505:22] reg uops_14_edge_inst; // @[util.scala:505:22] reg [5:0] uops_14_pc_lob; // @[util.scala:505:22] reg uops_14_taken; // @[util.scala:505:22] reg uops_14_imm_rename; // @[util.scala:505:22] reg [2:0] uops_14_imm_sel; // @[util.scala:505:22] reg [4:0] uops_14_pimm; // @[util.scala:505:22] reg [19:0] uops_14_imm_packed; // @[util.scala:505:22] reg [1:0] uops_14_op1_sel; // @[util.scala:505:22] reg [2:0] uops_14_op2_sel; // @[util.scala:505:22] reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_14_fp_ctrl_wen; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_14_fp_ctrl_toint; // @[util.scala:505:22] reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_14_fp_ctrl_fma; // @[util.scala:505:22] reg uops_14_fp_ctrl_div; // @[util.scala:505:22] reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_14_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_14_rob_idx; // @[util.scala:505:22] reg [3:0] uops_14_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_14_stq_idx; // @[util.scala:505:22] reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_14_pdst; // @[util.scala:505:22] reg [5:0] uops_14_prs1; // @[util.scala:505:22] reg [5:0] uops_14_prs2; // @[util.scala:505:22] reg [5:0] uops_14_prs3; // @[util.scala:505:22] reg [3:0] uops_14_ppred; // @[util.scala:505:22] reg uops_14_prs1_busy; // @[util.scala:505:22] reg uops_14_prs2_busy; // @[util.scala:505:22] reg uops_14_prs3_busy; // @[util.scala:505:22] reg uops_14_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_14_stale_pdst; // @[util.scala:505:22] reg uops_14_exception; // @[util.scala:505:22] reg [63:0] uops_14_exc_cause; // @[util.scala:505:22] reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_14_mem_size; // @[util.scala:505:22] reg uops_14_mem_signed; // @[util.scala:505:22] reg uops_14_uses_ldq; // @[util.scala:505:22] reg uops_14_uses_stq; // @[util.scala:505:22] reg uops_14_is_unique; // @[util.scala:505:22] reg uops_14_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22] reg uops_14_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_14_ldst; // @[util.scala:505:22] reg [5:0] uops_14_lrs1; // @[util.scala:505:22] reg [5:0] uops_14_lrs2; // @[util.scala:505:22] reg [5:0] uops_14_lrs3; // @[util.scala:505:22] reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22] reg uops_14_frs3_en; // @[util.scala:505:22] reg uops_14_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_14_fcn_op; // @[util.scala:505:22] reg uops_14_fp_val; // @[util.scala:505:22] reg [2:0] uops_14_fp_rm; // @[util.scala:505:22] reg [1:0] uops_14_fp_typ; // @[util.scala:505:22] reg uops_14_xcpt_pf_if; // @[util.scala:505:22] reg uops_14_xcpt_ae_if; // @[util.scala:505:22] reg uops_14_xcpt_ma_if; // @[util.scala:505:22] reg uops_14_bp_debug_if; // @[util.scala:505:22] reg uops_14_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:509:29] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27] wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _do_enq_T_5 = _do_enq_T; // @[Decoupled.scala:51:35] wire _do_enq_T_8 = _do_enq_T_5; // @[util.scala:514:{39,99}] wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}] wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}] wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}] wire _valids_0_T_7 = _valids_0_T_4; // @[util.scala:520:{31,80}] wire _valids_1_T_7 = _valids_1_T_4; // @[util.scala:520:{31,80}] wire _valids_2_T_7 = _valids_2_T_4; // @[util.scala:520:{31,80}] wire _valids_3_T_7 = _valids_3_T_4; // @[util.scala:520:{31,80}] wire _valids_4_T_7 = _valids_4_T_4; // @[util.scala:520:{31,80}] wire _valids_5_T_7 = _valids_5_T_4; // @[util.scala:520:{31,80}] wire _valids_6_T_7 = _valids_6_T_4; // @[util.scala:520:{31,80}] wire _valids_7_T_7 = _valids_7_T_4; // @[util.scala:520:{31,80}] wire _valids_8_T_7 = _valids_8_T_4; // @[util.scala:520:{31,80}] wire _valids_9_T_7 = _valids_9_T_4; // @[util.scala:520:{31,80}] wire _valids_10_T_7 = _valids_10_T_4; // @[util.scala:520:{31,80}] wire _valids_11_T_7 = _valids_11_T_4; // @[util.scala:520:{31,80}] wire _valids_12_T_7 = _valids_12_T_4; // @[util.scala:520:{31,80}] wire _valids_13_T_7 = _valids_13_T_4; // @[util.scala:520:{31,80}] wire _valids_14_T_7 = _valids_14_T_4; // @[util.scala:520:{31,80}] wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19] assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19] wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21] assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21] assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21] assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21] assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21] assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21] assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21] assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21] assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21] assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21] assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21] assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21] assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21] assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21] assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32] assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42] wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34] wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26] wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26] wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12] assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22] wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:458:7] if (reset) begin // @[util.scala:458:7] valids_0 <= 1'h0; // @[util.scala:504:26] valids_1 <= 1'h0; // @[util.scala:504:26] valids_2 <= 1'h0; // @[util.scala:504:26] valids_3 <= 1'h0; // @[util.scala:504:26] valids_4 <= 1'h0; // @[util.scala:504:26] valids_5 <= 1'h0; // @[util.scala:504:26] valids_6 <= 1'h0; // @[util.scala:504:26] valids_7 <= 1'h0; // @[util.scala:504:26] valids_8 <= 1'h0; // @[util.scala:504:26] valids_9 <= 1'h0; // @[util.scala:504:26] valids_10 <= 1'h0; // @[util.scala:504:26] valids_11 <= 1'h0; // @[util.scala:504:26] valids_12 <= 1'h0; // @[util.scala:504:26] valids_13 <= 1'h0; // @[util.scala:504:26] valids_14 <= 1'h0; // @[util.scala:504:26] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:509:29] end else begin // @[util.scala:458:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 | _valids_0_T_7); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 | _valids_1_T_7); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 | _valids_2_T_7); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 | _valids_4_T_7); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 | _valids_5_T_7); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 | _valids_6_T_7); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 | _valids_8_T_7); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 | _valids_9_T_7); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 | _valids_10_T_7); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 | _valids_11_T_7); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 | _valids_12_T_7); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 | _valids_13_T_7); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 | _valids_14_T_7); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:514:26] enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:515:26] deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18] maybe_full <= do_enq; // @[util.scala:509:29, :514:26] end if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_0) // @[util.scala:504:26] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_1) // @[util.scala:504:26] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_2) // @[util.scala:504:26] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_3) // @[util.scala:504:26] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_4) // @[util.scala:504:26] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_5) // @[util.scala:504:26] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_6) // @[util.scala:504:26] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_7) // @[util.scala:504:26] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_8) // @[util.scala:504:26] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_9) // @[util.scala:504:26] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_10) // @[util.scala:504:26] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_11) // @[util.scala:504:26] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_12) // @[util.scala:504:26] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_13) // @[util.scala:504:26] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_14) // @[util.scala:504:26] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22] always @(posedge) ram_15x131 ram_ext ( // @[util.scala:503:22] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:514:26] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22] ); // @[util.scala:503:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] assign io_count = io_count_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr | (mask >> 1), ~(~addr | mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0) msbsLess || (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound || straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r || ignore) cur.cfg.w := aligned && (pmp.cfg.w || ignore) cur.cfg.x := aligned && (pmp.cfg.x || ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r || w || x || c || a || l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } }
module PTW( // @[PTW.scala:219:7] input clock, // @[PTW.scala:219:7] input reset, // @[PTW.scala:219:7] output io_requestor_0_req_ready, // @[PTW.scala:220:14] output io_requestor_0_resp_valid, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_0_status_debug, // @[PTW.scala:220:14] output io_requestor_0_status_cease, // @[PTW.scala:220:14] output io_requestor_0_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14] output io_requestor_0_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14] output io_requestor_0_status_v, // @[PTW.scala:220:14] output io_requestor_0_status_mpv, // @[PTW.scala:220:14] output io_requestor_0_status_gva, // @[PTW.scala:220:14] output io_requestor_0_status_tsr, // @[PTW.scala:220:14] output io_requestor_0_status_tw, // @[PTW.scala:220:14] output io_requestor_0_status_tvm, // @[PTW.scala:220:14] output io_requestor_0_status_mxr, // @[PTW.scala:220:14] output io_requestor_0_status_sum, // @[PTW.scala:220:14] output io_requestor_0_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14] output io_requestor_0_status_spp, // @[PTW.scala:220:14] output io_requestor_0_status_mpie, // @[PTW.scala:220:14] output io_requestor_0_status_spie, // @[PTW.scala:220:14] output io_requestor_0_status_mie, // @[PTW.scala:220:14] output io_requestor_0_status_sie, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_0_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_0_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_0_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_0_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_0_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_0_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_1_req_ready, // @[PTW.scala:220:14] output io_requestor_1_resp_valid, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_1_status_debug, // @[PTW.scala:220:14] output io_requestor_1_status_cease, // @[PTW.scala:220:14] output io_requestor_1_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_1_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14] output io_requestor_1_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14] output io_requestor_1_status_v, // @[PTW.scala:220:14] output io_requestor_1_status_mpv, // @[PTW.scala:220:14] output io_requestor_1_status_gva, // @[PTW.scala:220:14] output io_requestor_1_status_tsr, // @[PTW.scala:220:14] output io_requestor_1_status_tw, // @[PTW.scala:220:14] output io_requestor_1_status_tvm, // @[PTW.scala:220:14] output io_requestor_1_status_mxr, // @[PTW.scala:220:14] output io_requestor_1_status_sum, // @[PTW.scala:220:14] output io_requestor_1_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14] output io_requestor_1_status_spp, // @[PTW.scala:220:14] output io_requestor_1_status_mpie, // @[PTW.scala:220:14] output io_requestor_1_status_spie, // @[PTW.scala:220:14] output io_requestor_1_status_mie, // @[PTW.scala:220:14] output io_requestor_1_status_sie, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_1_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_1_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_1_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_1_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_1_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_1_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_2_req_ready, // @[PTW.scala:220:14] input io_requestor_2_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_2_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_2_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_2_resp_valid, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_2_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_2_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_2_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_2_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_2_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_2_status_debug, // @[PTW.scala:220:14] output io_requestor_2_status_cease, // @[PTW.scala:220:14] output io_requestor_2_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_2_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_dprv, // @[PTW.scala:220:14] output io_requestor_2_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_prv, // @[PTW.scala:220:14] output io_requestor_2_status_v, // @[PTW.scala:220:14] output io_requestor_2_status_mpv, // @[PTW.scala:220:14] output io_requestor_2_status_gva, // @[PTW.scala:220:14] output io_requestor_2_status_tsr, // @[PTW.scala:220:14] output io_requestor_2_status_tw, // @[PTW.scala:220:14] output io_requestor_2_status_tvm, // @[PTW.scala:220:14] output io_requestor_2_status_mxr, // @[PTW.scala:220:14] output io_requestor_2_status_sum, // @[PTW.scala:220:14] output io_requestor_2_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_mpp, // @[PTW.scala:220:14] output io_requestor_2_status_spp, // @[PTW.scala:220:14] output io_requestor_2_status_mpie, // @[PTW.scala:220:14] output io_requestor_2_status_spie, // @[PTW.scala:220:14] output io_requestor_2_status_mie, // @[PTW.scala:220:14] output io_requestor_2_status_sie, // @[PTW.scala:220:14] output io_requestor_2_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_2_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_2_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_2_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_2_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_2_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_2_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_2_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_2_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_2_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_2_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_2_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_2_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_2_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_2_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_2_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_2_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_2_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_2_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_3_req_ready, // @[PTW.scala:220:14] input io_requestor_3_req_valid, // @[PTW.scala:220:14] input io_requestor_3_req_bits_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_3_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_3_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_3_resp_valid, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_3_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_3_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_3_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_3_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_3_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_3_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_3_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_3_status_debug, // @[PTW.scala:220:14] output io_requestor_3_status_cease, // @[PTW.scala:220:14] output io_requestor_3_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_3_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_3_status_dprv, // @[PTW.scala:220:14] output io_requestor_3_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_3_status_prv, // @[PTW.scala:220:14] output io_requestor_3_status_v, // @[PTW.scala:220:14] output io_requestor_3_status_mpv, // @[PTW.scala:220:14] output io_requestor_3_status_gva, // @[PTW.scala:220:14] output io_requestor_3_status_tsr, // @[PTW.scala:220:14] output io_requestor_3_status_tw, // @[PTW.scala:220:14] output io_requestor_3_status_tvm, // @[PTW.scala:220:14] output io_requestor_3_status_mxr, // @[PTW.scala:220:14] output io_requestor_3_status_sum, // @[PTW.scala:220:14] output io_requestor_3_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_3_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_3_status_mpp, // @[PTW.scala:220:14] output io_requestor_3_status_spp, // @[PTW.scala:220:14] output io_requestor_3_status_mpie, // @[PTW.scala:220:14] output io_requestor_3_status_spie, // @[PTW.scala:220:14] output io_requestor_3_status_mie, // @[PTW.scala:220:14] output io_requestor_3_status_sie, // @[PTW.scala:220:14] output io_requestor_3_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_3_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_3_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_3_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_3_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_3_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_3_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_3_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_3_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_3_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_3_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_3_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_3_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_3_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_3_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_3_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_3_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_3_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_3_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_3_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_3_value, // @[PTW.scala:220:14] input io_mem_req_ready, // @[PTW.scala:220:14] output io_mem_req_valid, // @[PTW.scala:220:14] output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14] output io_mem_req_bits_dv, // @[PTW.scala:220:14] output io_mem_s1_kill, // @[PTW.scala:220:14] input io_mem_s2_nack, // @[PTW.scala:220:14] input io_mem_s2_nack_cause_raw, // @[PTW.scala:220:14] input io_mem_s2_uncached, // @[PTW.scala:220:14] input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14] input io_mem_resp_valid, // @[PTW.scala:220:14] input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14] input [7:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14] input [4:0] io_mem_resp_bits_cmd, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14] input io_mem_resp_bits_signed, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14] input io_mem_resp_bits_dv, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14] input [7:0] io_mem_resp_bits_mask, // @[PTW.scala:220:14] input io_mem_resp_bits_replay, // @[PTW.scala:220:14] input io_mem_resp_bits_has_data, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_store_data, // @[PTW.scala:220:14] input io_mem_replay_next, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14] input [39:0] io_mem_s2_gpa, // @[PTW.scala:220:14] input io_mem_ordered, // @[PTW.scala:220:14] input io_mem_store_pending, // @[PTW.scala:220:14] input io_mem_perf_acquire, // @[PTW.scala:220:14] input io_mem_perf_release, // @[PTW.scala:220:14] input io_mem_perf_grant, // @[PTW.scala:220:14] input io_mem_perf_tlbMiss, // @[PTW.scala:220:14] input io_mem_perf_blocked, // @[PTW.scala:220:14] input io_mem_perf_canAcceptStoreThenLoad, // @[PTW.scala:220:14] input io_mem_perf_canAcceptStoreThenRMW, // @[PTW.scala:220:14] input io_mem_perf_canAcceptLoadThenLoad, // @[PTW.scala:220:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[PTW.scala:220:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[PTW.scala:220:14] input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14] input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14] input io_dpath_sfence_valid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14] input [38:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14] input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14] input io_dpath_status_debug, // @[PTW.scala:220:14] input io_dpath_status_cease, // @[PTW.scala:220:14] input io_dpath_status_wfi, // @[PTW.scala:220:14] input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14] input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14] input io_dpath_status_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14] input io_dpath_status_v, // @[PTW.scala:220:14] input io_dpath_status_mpv, // @[PTW.scala:220:14] input io_dpath_status_gva, // @[PTW.scala:220:14] input io_dpath_status_tsr, // @[PTW.scala:220:14] input io_dpath_status_tw, // @[PTW.scala:220:14] input io_dpath_status_tvm, // @[PTW.scala:220:14] input io_dpath_status_mxr, // @[PTW.scala:220:14] input io_dpath_status_sum, // @[PTW.scala:220:14] input io_dpath_status_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14] input io_dpath_status_spp, // @[PTW.scala:220:14] input io_dpath_status_mpie, // @[PTW.scala:220:14] input io_dpath_status_spie, // @[PTW.scala:220:14] input io_dpath_status_mie, // @[PTW.scala:220:14] input io_dpath_status_sie, // @[PTW.scala:220:14] input io_dpath_hstatus_spvp, // @[PTW.scala:220:14] input io_dpath_hstatus_spv, // @[PTW.scala:220:14] input io_dpath_hstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_debug, // @[PTW.scala:220:14] input io_dpath_gstatus_cease, // @[PTW.scala:220:14] input io_dpath_gstatus_wfi, // @[PTW.scala:220:14] input [31:0] io_dpath_gstatus_isa, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_dprv, // @[PTW.scala:220:14] input io_dpath_gstatus_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_prv, // @[PTW.scala:220:14] input io_dpath_gstatus_v, // @[PTW.scala:220:14] input [22:0] io_dpath_gstatus_zero2, // @[PTW.scala:220:14] input io_dpath_gstatus_mpv, // @[PTW.scala:220:14] input io_dpath_gstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_mbe, // @[PTW.scala:220:14] input io_dpath_gstatus_sbe, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_sxl, // @[PTW.scala:220:14] input [7:0] io_dpath_gstatus_zero1, // @[PTW.scala:220:14] input io_dpath_gstatus_tsr, // @[PTW.scala:220:14] input io_dpath_gstatus_tw, // @[PTW.scala:220:14] input io_dpath_gstatus_tvm, // @[PTW.scala:220:14] input io_dpath_gstatus_mxr, // @[PTW.scala:220:14] input io_dpath_gstatus_sum, // @[PTW.scala:220:14] input io_dpath_gstatus_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_mpp, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_vs, // @[PTW.scala:220:14] input io_dpath_gstatus_spp, // @[PTW.scala:220:14] input io_dpath_gstatus_mpie, // @[PTW.scala:220:14] input io_dpath_gstatus_ube, // @[PTW.scala:220:14] input io_dpath_gstatus_spie, // @[PTW.scala:220:14] input io_dpath_gstatus_upie, // @[PTW.scala:220:14] input io_dpath_gstatus_mie, // @[PTW.scala:220:14] input io_dpath_gstatus_hie, // @[PTW.scala:220:14] input io_dpath_gstatus_sie, // @[PTW.scala:220:14] input io_dpath_gstatus_uie, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14] output io_dpath_perf_pte_miss, // @[PTW.scala:220:14] output io_dpath_perf_pte_hit, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_0_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_1_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_2_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_dpath_clock_enabled // @[PTW.scala:220:14] ); wire tmp_r; // @[PTW.scala:304:37] wire tmp_w; // @[PTW.scala:304:37] wire tmp_x; // @[PTW.scala:304:37] wire tmp_u; // @[PTW.scala:304:37] wire tmp_g; // @[PTW.scala:304:37] wire tmp_a; // @[PTW.scala:304:37] wire tmp_d; // @[PTW.scala:304:37] wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37] wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37] wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25] wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25] wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25] wire _r_pte_barrier_io_y_d; // @[package.scala:267:25] wire _r_pte_barrier_io_y_a; // @[package.scala:267:25] wire _r_pte_barrier_io_y_g; // @[package.scala:267:25] wire _r_pte_barrier_io_y_u; // @[package.scala:267:25] wire _r_pte_barrier_io_y_x; // @[package.scala:267:25] wire _r_pte_barrier_io_y_w; // @[package.scala:267:25] wire _r_pte_barrier_io_y_r; // @[package.scala:267:25] wire _r_pte_barrier_io_y_v; // @[package.scala:267:25] wire [2:0] _state_barrier_io_y; // @[package.scala:267:25] wire _arb_io_out_valid; // @[PTW.scala:236:19] wire _arb_io_out_bits_valid; // @[PTW.scala:236:19] wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19] wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19] wire [1:0] _arb_io_chosen; // @[PTW.scala:236:19] wire io_requestor_2_req_valid_0 = io_requestor_2_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_2_req_bits_bits_addr_0 = io_requestor_2_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_need_gpa_0 = io_requestor_2_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_3_req_valid_0 = io_requestor_3_req_valid; // @[PTW.scala:219:7] wire io_requestor_3_req_bits_valid_0 = io_requestor_3_req_bits_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_3_req_bits_bits_addr_0 = io_requestor_3_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_3_req_bits_bits_need_gpa_0 = io_requestor_3_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[PTW.scala:219:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[PTW.scala:219:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[PTW.scala:219:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[PTW.scala:219:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[PTW.scala:219:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7] wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[PTW.scala:219:7] wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[PTW.scala:219:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[PTW.scala:219:7] wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7] wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7] wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7] wire [38:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7] wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7] wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7] wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7] wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7] wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7] wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7] wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7] wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7] wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7] wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7] wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7] wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7] wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7] wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7] wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7] wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7] wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7] wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7] wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7] wire io_dpath_hstatus_spvp_0 = io_dpath_hstatus_spvp; // @[PTW.scala:219:7] wire io_dpath_hstatus_spv_0 = io_dpath_hstatus_spv; // @[PTW.scala:219:7] wire io_dpath_hstatus_gva_0 = io_dpath_hstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_debug_0 = io_dpath_gstatus_debug; // @[PTW.scala:219:7] wire io_dpath_gstatus_cease_0 = io_dpath_gstatus_cease; // @[PTW.scala:219:7] wire io_dpath_gstatus_wfi_0 = io_dpath_gstatus_wfi; // @[PTW.scala:219:7] wire [31:0] io_dpath_gstatus_isa_0 = io_dpath_gstatus_isa; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_dprv_0 = io_dpath_gstatus_dprv; // @[PTW.scala:219:7] wire io_dpath_gstatus_dv_0 = io_dpath_gstatus_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_prv_0 = io_dpath_gstatus_prv; // @[PTW.scala:219:7] wire io_dpath_gstatus_v_0 = io_dpath_gstatus_v; // @[PTW.scala:219:7] wire [22:0] io_dpath_gstatus_zero2_0 = io_dpath_gstatus_zero2; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpv_0 = io_dpath_gstatus_mpv; // @[PTW.scala:219:7] wire io_dpath_gstatus_gva_0 = io_dpath_gstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_mbe_0 = io_dpath_gstatus_mbe; // @[PTW.scala:219:7] wire io_dpath_gstatus_sbe_0 = io_dpath_gstatus_sbe; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_sxl_0 = io_dpath_gstatus_sxl; // @[PTW.scala:219:7] wire [7:0] io_dpath_gstatus_zero1_0 = io_dpath_gstatus_zero1; // @[PTW.scala:219:7] wire io_dpath_gstatus_tsr_0 = io_dpath_gstatus_tsr; // @[PTW.scala:219:7] wire io_dpath_gstatus_tw_0 = io_dpath_gstatus_tw; // @[PTW.scala:219:7] wire io_dpath_gstatus_tvm_0 = io_dpath_gstatus_tvm; // @[PTW.scala:219:7] wire io_dpath_gstatus_mxr_0 = io_dpath_gstatus_mxr; // @[PTW.scala:219:7] wire io_dpath_gstatus_sum_0 = io_dpath_gstatus_sum; // @[PTW.scala:219:7] wire io_dpath_gstatus_mprv_0 = io_dpath_gstatus_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_fs_0 = io_dpath_gstatus_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_mpp_0 = io_dpath_gstatus_mpp; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_vs_0 = io_dpath_gstatus_vs; // @[PTW.scala:219:7] wire io_dpath_gstatus_spp_0 = io_dpath_gstatus_spp; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpie_0 = io_dpath_gstatus_mpie; // @[PTW.scala:219:7] wire io_dpath_gstatus_ube_0 = io_dpath_gstatus_ube; // @[PTW.scala:219:7] wire io_dpath_gstatus_spie_0 = io_dpath_gstatus_spie; // @[PTW.scala:219:7] wire io_dpath_gstatus_upie_0 = io_dpath_gstatus_upie; // @[PTW.scala:219:7] wire io_dpath_gstatus_mie_0 = io_dpath_gstatus_mie; // @[PTW.scala:219:7] wire io_dpath_gstatus_hie_0 = io_dpath_gstatus_hie; // @[PTW.scala:219:7] wire io_dpath_gstatus_sie_0 = io_dpath_gstatus_sie; // @[PTW.scala:219:7] wire io_dpath_gstatus_uie_0 = io_dpath_gstatus_uie; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_3_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_3_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_3_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17] wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_3_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_3_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] hits_lo_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hits_hi_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hi_2 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] lo_2 = 4'h0; // @[OneHot.scala:31:18] wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_3_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_3_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113] wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19] wire io_requestor_0_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_1_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_2_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_3_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7] wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7] wire io_dpath_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire state_reg_set_left_older_9 = 1'h1; // @[Replacement.scala:196:33] wire state_reg_set_left_older_10 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_72 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_76 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_77 = 1'h1; // @[Replacement.scala:206:16] wire state_reg_set_left_older_11 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_83 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_87 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_88 = 1'h1; // @[Replacement.scala:206:16] wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60] wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_109 = 1'h1; // @[TLBPermissions.scala:87:22] wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28] wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56] wire _r_pte_T = 1'h1; // @[PTW.scala:670:19] wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_3_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_need_gpa = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_need_gpa = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7] wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_2 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_3 = 1'h0; // @[PTW.scala:242:35] wire _hits_T_9 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_10 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_11 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_12 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_13 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_14 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_15 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_16 = 1'h0; // @[PTW.scala:366:27] wire _hit_T_1 = 1'h0; // @[PTW.scala:367:20] wire stage2_pte_cache_hit = 1'h0; // @[PTW.scala:367:24] wire _state_reg_set_left_older_T_9 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_set_left_older_T_10 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_70 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_71 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_74 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_75 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_set_left_older_T_11 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_81 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_82 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_85 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_86 = 1'h0; // @[Replacement.scala:218:17] wire l2_pte_d = 1'h0; // @[PTW.scala:403:113] wire l2_pte_a = 1'h0; // @[PTW.scala:403:113] wire l2_pte_g = 1'h0; // @[PTW.scala:403:113] wire l2_pte_u = 1'h0; // @[PTW.scala:403:113] wire l2_pte_x = 1'h0; // @[PTW.scala:403:113] wire l2_pte_w = 1'h0; // @[PTW.scala:403:113] wire l2_pte_r = 1'h0; // @[PTW.scala:403:113] wire l2_pte_v = 1'h0; // @[PTW.scala:403:113] wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32] wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40] wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_2_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_3_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53] wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71] wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16] wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29] wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25] wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58] wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26] wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_3_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_tag = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] _hits_T_17 = 8'h0; // @[package.scala:45:27] wire [7:0] hits_1 = 8'h0; // @[PTW.scala:366:43] wire [1:0] io_requestor_0_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42] wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58] wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44] wire [1:0] hits_lo_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_lo_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hi_3 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] lo_3 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] _state_reg_T_69 = 2'h0; // @[package.scala:163:13] wire [1:0] _state_reg_T_80 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113] wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40] wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40] wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45] wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61] wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46] wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62] wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46] wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62] wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27] wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27] wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44] wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40] wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27] wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26] wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26] wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44] wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27] wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40] wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_2_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_3_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_2_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_3_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_2_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_3_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30] wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58] wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42] wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58] wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] state_reg_touch_way_sized_3 = 3'h0; // @[package.scala:163:13] wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45] wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61] wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46] wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62] wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46] wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62] wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44] wire [19:0] stage2_pte_cache_data = 20'h0; // @[Mux.scala:30:73] wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40] wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58] wire [26:0] io_requestor_0_req_bits_bits_addr = 27'h0; // @[PTW.scala:219:7] wire [26:0] io_requestor_1_req_bits_bits_addr = 27'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7] wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113] wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26] wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26] wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [39:0] tag_1 = 40'h8000000000; // @[PTW.scala:363:18] wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23] wire [38:0] _tag_T = 39'h0; // @[package.scala:138:15] wire [1:0] max_count; // @[PTW.scala:289:25] wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_3_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_3_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39] wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40] wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51] wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_3_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17] wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_3_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17] wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_2_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_3_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_2_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_3_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_2_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_3_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_3_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_2_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_3_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_2_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_3_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_3_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_3_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_3_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_3_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_3_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_3_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_3_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_3_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_3_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:394:57] wire io_requestor_0_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39] wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_2_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_2_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_2_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_3_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_3_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_3_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_3_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_valid_0; // @[PTW.scala:219:7] wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7] wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7] wire io_mem_req_valid_0; // @[PTW.scala:219:7] wire io_mem_s1_kill_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7] wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7] reg [2:0] state; // @[PTW.scala:233:22] wire l2_refill_wire; // @[PTW.scala:234:28] wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30] wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46] wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}] reg resp_valid_0; // @[PTW.scala:242:27] assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27] reg resp_valid_1; // @[PTW.scala:242:27] assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27] reg resp_valid_2; // @[PTW.scala:242:27] assign io_requestor_2_resp_valid_0 = resp_valid_2; // @[PTW.scala:219:7, :242:27] reg resp_valid_3; // @[PTW.scala:242:27] assign io_requestor_3_resp_valid_0 = resp_valid_3; // @[PTW.scala:219:7, :242:27] wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24] wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}] wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}] wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}] wire _clock_en_T_4 = io_dpath_customCSRs_csrs_0_value_0[0]; // @[CustomCSRs.scala:43:61] wire clock_en = _clock_en_T_3 | _clock_en_T_4; // @[CustomCSRs.scala:43:61] assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39] assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39] reg invalidated; // @[PTW.scala:251:24] reg [1:0] count; // @[PTW.scala:259:18] wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21] reg resp_ae_ptw; // @[PTW.scala:260:24] assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_2_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_3_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] reg resp_ae_final; // @[PTW.scala:261:26] assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_2_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_3_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] reg resp_pf; // @[PTW.scala:262:20] assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_2_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_3_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] reg resp_gf; // @[PTW.scala:263:20] assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_2_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_3_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] reg resp_hr; // @[PTW.scala:264:20] assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_2_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_3_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] reg resp_hw; // @[PTW.scala:265:20] assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_2_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_3_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] reg resp_hx; // @[PTW.scala:266:20] assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_2_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_3_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] reg resp_fragmented_superpage; // @[PTW.scala:267:38] reg [26:0] r_req_addr; // @[PTW.scala:270:18] reg r_req_need_gpa; // @[PTW.scala:270:18] assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_2_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_3_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] reg r_req_vstage1; // @[PTW.scala:270:18] reg r_req_stage2; // @[PTW.scala:270:18] reg [1:0] r_req_dest; // @[PTW.scala:272:23] reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] reg [43:0] r_pte_ppn; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] reg r_pte_d; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26] reg r_pte_a; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26] reg r_pte_g; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26] reg r_pte_u; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26] reg r_pte_x; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26] reg r_pte_w; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26] reg r_pte_r; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26] reg r_pte_v; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26] reg [3:0] r_hgatp_mode; // @[PTW.scala:276:20] reg [15:0] r_hgatp_asid; // @[PTW.scala:276:20] reg [43:0] r_hgatp_ppn; // @[PTW.scala:276:20] reg [1:0] aux_count; // @[PTW.scala:278:22] wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_2_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_3_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20] wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26] reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20] reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20] wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26] reg aux_pte_d; // @[PTW.scala:280:20] wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26] reg aux_pte_a; // @[PTW.scala:280:20] wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26] reg aux_pte_g; // @[PTW.scala:280:20] wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26] reg aux_pte_u; // @[PTW.scala:280:20] wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26] reg aux_pte_x; // @[PTW.scala:280:20] wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26] reg aux_pte_w; // @[PTW.scala:280:20] wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26] reg aux_pte_r; // @[PTW.scala:280:20] wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26] reg aux_pte_v; // @[PTW.scala:280:20] wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26] reg [11:0] gpa_pgoff; // @[PTW.scala:281:22] reg stage2; // @[PTW.scala:282:19] reg stage2_final; // @[PTW.scala:283:25] wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26] wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38] wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25] assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25] assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_2_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_3_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31] wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}] wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12] reg mem_resp_valid; // @[PTW.scala:292:31] reg [63:0] mem_resp_data; // @[PTW.scala:293:30] wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37] wire [9:0] _tmp_T_10; // @[PTW.scala:304:37] wire [43:0] _tmp_T_9; // @[PTW.scala:304:37] wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26] wire [1:0] _tmp_T_8; // @[PTW.scala:304:37] wire _tmp_T_7; // @[PTW.scala:304:37] wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26] wire _tmp_T_6; // @[PTW.scala:304:37] wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26] wire _tmp_T_5; // @[PTW.scala:304:37] wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26] wire _tmp_T_4; // @[PTW.scala:304:37] wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26] wire _tmp_T_3; // @[PTW.scala:304:37] wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26] wire _tmp_T_2; // @[PTW.scala:304:37] wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26] wire _tmp_T_1; // @[PTW.scala:304:37] wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26] wire _tmp_T; // @[PTW.scala:304:37] wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26] wire [43:0] tmp_ppn; // @[PTW.scala:304:37] wire tmp_v; // @[PTW.scala:304:37] assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37] assign tmp_v = _tmp_T; // @[PTW.scala:304:37] assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37] assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37] assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37] assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37] assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37] assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37] assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37] assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37] assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37] assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37] assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37] assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37] assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37] assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37] assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37] assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37] assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37] assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37] assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37] assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37] wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26] wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26] wire [43:0] pte_ppn; // @[PTW.scala:305:26] wire pte_v; // @[PTW.scala:305:26] wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26] wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38] wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}] wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54] wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99] wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}] assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}] assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}] wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}] wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58] wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25] wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26] wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}] wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}] wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}] wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}] wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}] wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}] wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33] wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}] wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51] wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}] wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73] wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}] wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}] wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}] wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}] wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40] wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}] wire _T_46 = count == 2'h1; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T = _T_46; // @[package.scala:39:86] wire _pmaHomogeneous_T; // @[package.scala:39:86] assign _pmaHomogeneous_T = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_3 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_23; // @[package.scala:39:86] assign _pmpHomogeneous_T_23 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_11 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_60; // @[package.scala:39:86] assign _pmpHomogeneous_T_60 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_5 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_19 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_97; // @[package.scala:39:86] assign _pmpHomogeneous_T_97 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_10 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_27 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_134; // @[package.scala:39:86] assign _pmpHomogeneous_T_134 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_15 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_35 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_171; // @[package.scala:39:86] assign _pmpHomogeneous_T_171 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_20 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_43 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_208; // @[package.scala:39:86] assign _pmpHomogeneous_T_208 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_25 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_51 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_245; // @[package.scala:39:86] assign _pmpHomogeneous_T_245 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_30 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_59 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_282; // @[package.scala:39:86] assign _pmpHomogeneous_T_282 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_35 = _T_46; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T = _T_46; // @[package.scala:39:86] wire _aux_pte_T; // @[package.scala:39:86] assign _aux_pte_T = _T_46; // @[package.scala:39:86] wire _leaf_T_5; // @[PTW.scala:751:53] assign _leaf_T_5 = _T_46; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}] wire _T_241 = count == 2'h2; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T_2 = _T_241; // @[package.scala:39:86] wire _pmaHomogeneous_T_2; // @[package.scala:39:86] assign _pmaHomogeneous_T_2 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_T_25 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_2 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_62; // @[package.scala:39:86] assign _pmpHomogeneous_T_62 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_7 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_99; // @[package.scala:39:86] assign _pmpHomogeneous_T_99 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_12 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_136; // @[package.scala:39:86] assign _pmpHomogeneous_T_136 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_17 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_173; // @[package.scala:39:86] assign _pmpHomogeneous_T_173 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_22 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_210; // @[package.scala:39:86] assign _pmpHomogeneous_T_210 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_27 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_247; // @[package.scala:39:86] assign _pmpHomogeneous_T_247 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_32 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_284; // @[package.scala:39:86] assign _pmpHomogeneous_T_284 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_37 = _T_241; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T_2 = _T_241; // @[package.scala:39:86] wire _l2_refill_T; // @[PTW.scala:713:39] assign _l2_refill_T = _T_241; // @[package.scala:39:86] wire _aux_pte_T_2; // @[package.scala:39:86] assign _aux_pte_T_2 = _T_241; // @[package.scala:39:86] wire _leaf_T_8; // @[PTW.scala:751:53] assign _leaf_T_8 = _T_241; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}] wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}] wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76] wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36] wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}] wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}] wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23] reg [6:0] state_reg; // @[Replacement.scala:168:70] reg [7:0] valid; // @[PTW.scala:352:24] reg [31:0] tags_0; // @[PTW.scala:353:19] reg [31:0] tags_1; // @[PTW.scala:353:19] reg [31:0] tags_2; // @[PTW.scala:353:19] reg [31:0] tags_3; // @[PTW.scala:353:19] reg [31:0] tags_4; // @[PTW.scala:353:19] reg [31:0] tags_5; // @[PTW.scala:353:19] reg [31:0] tags_6; // @[PTW.scala:353:19] reg [31:0] tags_7; // @[PTW.scala:353:19] reg [19:0] data_0; // @[PTW.scala:355:19] reg [19:0] data_1; // @[PTW.scala:355:19] reg [19:0] data_2; // @[PTW.scala:355:19] reg [19:0] data_3; // @[PTW.scala:355:19] reg [19:0] data_4; // @[PTW.scala:355:19] reg [19:0] data_5; // @[PTW.scala:355:19] reg [19:0] data_6; // @[PTW.scala:355:19] reg [19:0] data_7; // @[PTW.scala:355:19] wire _can_hit_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :358:18] wire _can_hit_T_1 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65] wire _can_hit_T_2 = r_req_vstage1 ? stage2 : _can_hit_T_1; // @[PTW.scala:270:18, :282:19, :358:{41,65}] wire can_hit = _can_hit_T & _can_hit_T_2; // @[PTW.scala:358:{18,35,41}] wire [32:0] tag = {r_req_vstage1, pte_addr}; // @[PTW.scala:270:18, :330:23, :364:15] wire _hits_T = {1'h0, tags_0} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_1 = {1'h0, tags_1} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_2 = {1'h0, tags_2} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_3 = {1'h0, tags_3} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_4 = {1'h0, tags_4} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_5 = {1'h0, tags_5} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_6 = {1'h0, tags_6} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_7 = {1'h0, tags_7} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire [1:0] hits_lo_lo = {_hits_T_1, _hits_T}; // @[package.scala:45:27] wire [1:0] hits_lo_hi = {_hits_T_3, _hits_T_2}; // @[package.scala:45:27] wire [3:0] hits_lo = {hits_lo_hi, hits_lo_lo}; // @[package.scala:45:27] wire [1:0] hits_hi_lo = {_hits_T_5, _hits_T_4}; // @[package.scala:45:27] wire [1:0] hits_hi_hi = {_hits_T_7, _hits_T_6}; // @[package.scala:45:27] wire [3:0] hits_hi = {hits_hi_hi, hits_hi_lo}; // @[package.scala:45:27] wire [7:0] _hits_T_8 = {hits_hi, hits_lo}; // @[package.scala:45:27] wire [7:0] hits = _hits_T_8 & valid; // @[package.scala:45:27] wire _hit_T = |hits; // @[PTW.scala:366:43, :367:20] wire pte_cache_hit = _hit_T & can_hit; // @[PTW.scala:358:35, :367:{20,24}] wire _r_T = &valid; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older = state_reg[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_3 = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_3 = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_1 = r_left_subtree_state[2]; // @[package.scala:163:13] wire r_left_subtree_state_1 = r_left_subtree_state[1]; // @[package.scala:163:13] wire _r_T_1 = r_left_subtree_state_1; // @[package.scala:163:13] wire r_right_subtree_state_1 = r_left_subtree_state[0]; // @[package.scala:163:13] wire _r_T_2 = r_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_T_3 = r_left_subtree_older_1 ? _r_T_1 : _r_T_2; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_4 = {r_left_subtree_older_1, _r_T_3}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_2 = r_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_2 = r_right_subtree_state[1]; // @[package.scala:163:13] wire _r_T_5 = r_left_subtree_state_2; // @[package.scala:163:13] wire r_right_subtree_state_2 = r_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_T_6 = r_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_T_7 = r_left_subtree_older_2 ? _r_T_5 : _r_T_6; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_8 = {r_left_subtree_older_2, _r_T_7}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_9 = r_left_subtree_older ? _r_T_4 : _r_T_8; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_10 = {r_left_subtree_older, _r_T_9}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_11 = ~valid; // @[PTW.scala:352:24, :370:57] wire _r_T_12 = _r_T_11[0]; // @[OneHot.scala:48:45] wire _r_T_13 = _r_T_11[1]; // @[OneHot.scala:48:45] wire _r_T_14 = _r_T_11[2]; // @[OneHot.scala:48:45] wire _r_T_15 = _r_T_11[3]; // @[OneHot.scala:48:45] wire _r_T_16 = _r_T_11[4]; // @[OneHot.scala:48:45] wire _r_T_17 = _r_T_11[5]; // @[OneHot.scala:48:45] wire _r_T_18 = _r_T_11[6]; // @[OneHot.scala:48:45] wire _r_T_19 = _r_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_20 = {2'h3, ~_r_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_T_21 = _r_T_17 ? 3'h5 : _r_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_T_22 = _r_T_16 ? 3'h4 : _r_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_T_23 = _r_T_15 ? 3'h3 : _r_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_T_24 = _r_T_14 ? 3'h2 : _r_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_T_25 = _r_T_13 ? 3'h1 : _r_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_T_26 = _r_T_12 ? 3'h0 : _r_T_25; // @[OneHot.scala:48:45] wire [2:0] r = _r_T ? _r_T_10 : _r_T_26; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized = r; // @[package.scala:163:13] wire [7:0] _valid_T = 8'h1 << r; // @[OneHot.scala:58:35] wire [7:0] _valid_T_1 = valid | _valid_T; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_1 = state_reg_left_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_1 = state_reg_left_subtree_state[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13] wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_4 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_3; // @[package.scala:163:13] wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_8 = state_reg_set_left_older_1 ? _state_reg_T_7 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_9; // @[package.scala:163:13] wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_2 = state_reg_right_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = state_reg_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13] wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_15 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_14; // @[package.scala:163:13] wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_19 = state_reg_set_left_older_2 ? _state_reg_T_18 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire _T_152 = state == 3'h1; // @[PTW.scala:233:22, :377:24] wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46] assign _io_dpath_perf_pte_hit_T = _T_152; // @[PTW.scala:377:24, :394:46] wire _io_mem_req_valid_T; // @[PTW.scala:515:29] assign _io_mem_req_valid_T = _T_152; // @[PTW.scala:377:24, :515:29] wire _r_pte_T_4; // @[PTW.scala:672:15] assign _r_pte_T_4 = _T_152; // @[PTW.scala:377:24, :672:15] wire _r_pte_T_6; // @[PTW.scala:674:15] assign _r_pte_T_6 = _T_152; // @[PTW.scala:377:24, :674:15] wire [3:0] hi = hits[7:4]; // @[OneHot.scala:30:18] wire [3:0] lo = hits[3:0]; // @[OneHot.scala:31:18] wire [3:0] _T_30 = hi | lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_1 = _T_30[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_1 = _T_30[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_reg_touch_way_sized_1 = {|hi, |hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[2]; // @[package.scala:163:13] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_23 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_34 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_4 = _state_reg_T_23[1]; // @[package.scala:163:13] wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13] wire _state_reg_T_24 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_28 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_25 = _state_reg_T_24; // @[package.scala:163:13] wire _state_reg_T_26 = ~_state_reg_T_25; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_27 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_26; // @[package.scala:163:13] wire _state_reg_T_29 = _state_reg_T_28; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_30 = ~_state_reg_T_29; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_31 = state_reg_set_left_older_4 ? _state_reg_T_30 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_4, _state_reg_T_27}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_32 = {state_reg_hi_3, _state_reg_T_31}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_33 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_32; // @[package.scala:163:13] wire _state_reg_set_left_older_T_5 = _state_reg_T_34[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38] wire _state_reg_T_35 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_39 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_36 = _state_reg_T_35; // @[package.scala:163:13] wire _state_reg_T_37 = ~_state_reg_T_36; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_38 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_37; // @[package.scala:163:13] wire _state_reg_T_40 = _state_reg_T_39; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_41 = ~_state_reg_T_40; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_42 = state_reg_set_left_older_5 ? _state_reg_T_41 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_4 = {state_reg_set_left_older_5, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_43 = {state_reg_hi_4, _state_reg_T_42}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_44 = state_reg_set_left_older_3 ? _state_reg_T_43 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_5 = {state_reg_set_left_older_3, _state_reg_T_33}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_45 = {state_reg_hi_5, _state_reg_T_44}; // @[Replacement.scala:202:12, :206:16] wire _leaf_T_2 = ~(|count); // @[PTW.scala:259:18, :324:40, :382:47, :751:53] wire [19:0] pte_cache_data = (hits[0] ? data_0 : 20'h0) | (hits[1] ? data_1 : 20'h0) | (hits[2] ? data_2 : 20'h0) | (hits[3] ? data_3 : 20'h0) | (hits[4] ? data_4 : 20'h0) | (hits[5] ? data_5 : 20'h0) | (hits[6] ? data_6 : 20'h0) | (hits[7] ? data_7 : 20'h0); // @[Mux.scala:30:73, :32:36] reg [6:0] state_reg_1; // @[Replacement.scala:168:70] reg [7:0] valid_1; // @[PTW.scala:352:24] reg [19:0] data_1_0; // @[PTW.scala:355:19] reg [19:0] data_1_1; // @[PTW.scala:355:19] reg [19:0] data_1_2; // @[PTW.scala:355:19] reg [19:0] data_1_3; // @[PTW.scala:355:19] reg [19:0] data_1_4; // @[PTW.scala:355:19] reg [19:0] data_1_5; // @[PTW.scala:355:19] reg [19:0] data_1_6; // @[PTW.scala:355:19] reg [19:0] data_1_7; // @[PTW.scala:355:19] wire _can_hit_T_3 = ~(|count); // @[PTW.scala:259:18, :324:40, :357:21] wire _can_hit_T_4 = ~(aux_count[1]); // @[PTW.scala:278:22, :357:60] wire _can_hit_T_5 = _can_hit_T_3 & _can_hit_T_4; // @[PTW.scala:357:{21,47,60}] wire _can_hit_T_6 = _can_hit_T_5 & r_req_vstage1; // @[PTW.scala:270:18, :357:{47,77}] wire _can_hit_T_7 = _can_hit_T_6 & stage2; // @[PTW.scala:282:19, :357:{77,94}] wire _can_hit_T_8 = ~stage2_final; // @[PTW.scala:283:25, :357:107] wire can_hit_1 = _can_hit_T_7 & _can_hit_T_8; // @[PTW.scala:357:{94,104,107}] wire _can_refill_T = ~stage2; // @[PTW.scala:282:19, :306:38, :360:33] wire _can_refill_T_1 = do_both_stages & _can_refill_T; // @[PTW.scala:288:38, :360:{30,33}] wire _can_refill_T_2 = ~stage2_final; // @[PTW.scala:283:25, :357:107, :360:44] wire can_refill = _can_refill_T_1 & _can_refill_T_2; // @[PTW.scala:360:{30,41,44}] wire _r_T_27 = &valid_1; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older_3 = state_reg_1[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state_3 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_6 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_9 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state_3 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state_6 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_9 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_4 = r_left_subtree_state_3[2]; // @[package.scala:163:13] wire r_left_subtree_state_4 = r_left_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_28 = r_left_subtree_state_4; // @[package.scala:163:13] wire r_right_subtree_state_4 = r_left_subtree_state_3[0]; // @[package.scala:163:13] wire _r_T_29 = r_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12] wire _r_T_30 = r_left_subtree_older_4 ? _r_T_28 : _r_T_29; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_31 = {r_left_subtree_older_4, _r_T_30}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_5 = r_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_5 = r_right_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_32 = r_left_subtree_state_5; // @[package.scala:163:13] wire r_right_subtree_state_5 = r_right_subtree_state_3[0]; // @[Replacement.scala:245:38] wire _r_T_33 = r_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12] wire _r_T_34 = r_left_subtree_older_5 ? _r_T_32 : _r_T_33; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_35 = {r_left_subtree_older_5, _r_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_36 = r_left_subtree_older_3 ? _r_T_31 : _r_T_35; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_37 = {r_left_subtree_older_3, _r_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_38 = ~valid_1; // @[PTW.scala:352:24, :370:57] wire _r_T_39 = _r_T_38[0]; // @[OneHot.scala:48:45] wire _r_T_40 = _r_T_38[1]; // @[OneHot.scala:48:45] wire _r_T_41 = _r_T_38[2]; // @[OneHot.scala:48:45] wire _r_T_42 = _r_T_38[3]; // @[OneHot.scala:48:45] wire _r_T_43 = _r_T_38[4]; // @[OneHot.scala:48:45] wire _r_T_44 = _r_T_38[5]; // @[OneHot.scala:48:45] wire _r_T_45 = _r_T_38[6]; // @[OneHot.scala:48:45] wire _r_T_46 = _r_T_38[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_47 = {2'h3, ~_r_T_45}; // @[OneHot.scala:48:45] wire [2:0] _r_T_48 = _r_T_44 ? 3'h5 : _r_T_47; // @[OneHot.scala:48:45] wire [2:0] _r_T_49 = _r_T_43 ? 3'h4 : _r_T_48; // @[OneHot.scala:48:45] wire [2:0] _r_T_50 = _r_T_42 ? 3'h3 : _r_T_49; // @[OneHot.scala:48:45] wire [2:0] _r_T_51 = _r_T_41 ? 3'h2 : _r_T_50; // @[OneHot.scala:48:45] wire [2:0] _r_T_52 = _r_T_40 ? 3'h1 : _r_T_51; // @[OneHot.scala:48:45] wire [2:0] _r_T_53 = _r_T_39 ? 3'h0 : _r_T_52; // @[OneHot.scala:48:45] wire [2:0] r_1 = _r_T_27 ? _r_T_37 : _r_T_53; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized_2 = r_1; // @[package.scala:163:13] wire [7:0] _valid_T_2 = 8'h1 << r_1; // @[OneHot.scala:58:35] wire [7:0] _valid_T_3 = valid_1 | _valid_T_2; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T_6 = state_reg_touch_way_sized_2[2]; // @[package.scala:163:13] wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_46 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_57 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_7 = _state_reg_T_46[1]; // @[package.scala:163:13] wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[0]; // @[package.scala:163:13] wire _state_reg_T_47 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_51 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_48 = _state_reg_T_47; // @[package.scala:163:13] wire _state_reg_T_49 = ~_state_reg_T_48; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_50 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_49; // @[package.scala:163:13] wire _state_reg_T_52 = _state_reg_T_51; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_53 = ~_state_reg_T_52; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_54 = state_reg_set_left_older_7 ? _state_reg_T_53 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_7, _state_reg_T_50}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_55 = {state_reg_hi_6, _state_reg_T_54}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_56 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_55; // @[package.scala:163:13] wire _state_reg_set_left_older_T_8 = _state_reg_T_57[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_8 = state_reg_right_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_8 = state_reg_right_subtree_state_6[0]; // @[Replacement.scala:198:38] wire _state_reg_T_58 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_62 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_59 = _state_reg_T_58; // @[package.scala:163:13] wire _state_reg_T_60 = ~_state_reg_T_59; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_61 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_60; // @[package.scala:163:13] wire _state_reg_T_63 = _state_reg_T_62; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_64 = ~_state_reg_T_63; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_65 = state_reg_set_left_older_8 ? _state_reg_T_64 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_7 = {state_reg_set_left_older_8, _state_reg_T_61}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_66 = {state_reg_hi_7, _state_reg_T_65}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_67 = state_reg_set_left_older_6 ? _state_reg_T_66 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_8 = {state_reg_set_left_older_6, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_68 = {state_reg_hi_8, _state_reg_T_67}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_79 = state_reg_left_subtree_state_9; // @[package.scala:163:13] wire state_reg_left_subtree_state_10 = state_reg_left_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_73 = state_reg_left_subtree_state_10; // @[package.scala:163:13] wire state_reg_right_subtree_state_10 = state_reg_left_subtree_state_9[0]; // @[package.scala:163:13] wire [1:0] state_reg_hi_9 = {1'h1, _state_reg_T_73}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_78 = {state_reg_hi_9, 1'h1}; // @[Replacement.scala:202:12] wire state_reg_left_subtree_state_11 = state_reg_right_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_84 = state_reg_left_subtree_state_11; // @[package.scala:163:13] wire state_reg_right_subtree_state_11 = state_reg_right_subtree_state_9[0]; // @[Replacement.scala:198:38] wire [1:0] state_reg_hi_10 = {1'h1, _state_reg_T_84}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_89 = {state_reg_hi_10, 1'h1}; // @[Replacement.scala:202:12] wire [2:0] _state_reg_T_90 = _state_reg_T_89; // @[Replacement.scala:202:12, :206:16] wire [3:0] state_reg_hi_11 = {1'h1, _state_reg_T_79}; // @[Replacement.scala:202:12, :203:16] wire [6:0] _state_reg_T_91 = {state_reg_hi_11, _state_reg_T_90}; // @[Replacement.scala:202:12, :206:16] reg pte_hit; // @[PTW.scala:392:24] wire _io_dpath_perf_pte_hit_T_1 = pte_hit & _io_dpath_perf_pte_hit_T; // @[PTW.scala:392:24, :394:{36,46}] assign _io_dpath_perf_pte_hit_T_3 = _io_dpath_perf_pte_hit_T_1; // @[PTW.scala:394:{36,57}] assign io_dpath_perf_pte_hit_0 = _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:219:7, :394:57] reg l2_refill; // @[PTW.scala:398:26] assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26] wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65] wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}] wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}] wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48] assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}] assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39] assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24] wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43] assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}] assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40] wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38] wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}] assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}] assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51] wire [55:0] _GEN = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96] wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T = _GEN; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_7 = _GEN; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_37 = _GEN; // @[PTW.scala:544:96] wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80] assign _pmpHomogeneous_T = _GEN; // @[PTW.scala:544:96, :548:80] wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65] wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}] wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}] wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_98 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65] wire [55:0] _GEN_0 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_43 = _GEN_0; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_122 = _GEN_0; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_1 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_48 = _GEN_1; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_110 = _GEN_1; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_127 = _GEN_1; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_159; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_159 = _GEN_1; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_166; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_166 = _GEN_1; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:18], _pmaPgLevelHomogeneous_T_37[17:0] ^ 18'h20000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFFC000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:18], _pmaPgLevelHomogeneous_T_37[17:0] ^ 18'h24000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_68 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_78; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_78 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_132; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_132 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_147 = _GEN_2; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_83 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_88 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_89 = {1'h0, _pmaPgLevelHomogeneous_T_88}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_93; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_93 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_137 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_152; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_152 = _GEN_3; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_94 = {1'h0, _pmaPgLevelHomogeneous_T_93}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_97 = _pmaPgLevelHomogeneous_T_96 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_99 = _pmaPgLevelHomogeneous_T_98 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_104 = _pmaPgLevelHomogeneous_T_103 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_104 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_106 = _pmaPgLevelHomogeneous_T_105 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107 | _pmaPgLevelHomogeneous_T_92; // @[TLBPermissions.scala:101:65] wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_108 | _pmaPgLevelHomogeneous_T_97; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h8A130000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_115 = _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_116 = ~_pmaPgLevelHomogeneous_T_115; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_118 = {1'h0, _pmaPgLevelHomogeneous_T_117}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 & 57'hFFFF3000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_120 = _pmaPgLevelHomogeneous_T_119; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_121 = _pmaPgLevelHomogeneous_T_120 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_121; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_123 = {1'h0, _pmaPgLevelHomogeneous_T_122}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 & 57'hFFFF3000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_125 = _pmaPgLevelHomogeneous_T_124; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_126 = _pmaPgLevelHomogeneous_T_125 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_128 = {1'h0, _pmaPgLevelHomogeneous_T_127}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 & 57'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_129; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_133 = {1'h0, _pmaPgLevelHomogeneous_T_132}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 & 57'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_135 = _pmaPgLevelHomogeneous_T_134; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_136 = _pmaPgLevelHomogeneous_T_135 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_138 = {1'h0, _pmaPgLevelHomogeneous_T_137}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 & 57'hF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_140 = _pmaPgLevelHomogeneous_T_139; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_141 = _pmaPgLevelHomogeneous_T_140 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142 | _pmaPgLevelHomogeneous_T_126; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 | _pmaPgLevelHomogeneous_T_131; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_144 | _pmaPgLevelHomogeneous_T_136; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_141; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8E020000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_153 = {1'h0, _pmaPgLevelHomogeneous_T_152}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_154 = _pmaPgLevelHomogeneous_T_153 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_155 = _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 | _pmaPgLevelHomogeneous_T_156; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_160 = {1'h0, _pmaPgLevelHomogeneous_T_159}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_161 = _pmaPgLevelHomogeneous_T_160 & 57'h8A130000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_162 = _pmaPgLevelHomogeneous_T_161; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_163 = _pmaPgLevelHomogeneous_T_162 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_164 = _pmaPgLevelHomogeneous_T_163; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_165 = ~_pmaPgLevelHomogeneous_T_164; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_167 = {1'h0, _pmaPgLevelHomogeneous_T_166}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_168 = _pmaPgLevelHomogeneous_T_167 & 57'h8A130000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_169 = _pmaPgLevelHomogeneous_T_168; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_170 = _pmaPgLevelHomogeneous_T_169 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_171 = _pmaPgLevelHomogeneous_T_170; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_172 = ~_pmaPgLevelHomogeneous_T_171; // @[TLBPermissions.scala:87:{22,66}] wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86] wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}] wire [31:0] _GEN_4 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_2 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_9 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_16 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_8 = |_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_15 = |_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_22 = |_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_24 = _pmpHomogeneous_T_23 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_26 = _pmpHomogeneous_T_25 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_27 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_29 = pmpHomogeneous_maskHomogeneous | _pmpHomogeneous_T_28; // @[package.scala:39:76] wire _pmpHomogeneous_T_30 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_31 = ~_pmpHomogeneous_T_30; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}] wire _pmpHomogeneous_T_32 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21] wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}] wire [55:0] _GEN_5 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T = _GEN_5; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_5; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_33 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62] wire _pmpHomogeneous_T_34 = _pmpHomogeneous_T_32 | _pmpHomogeneous_T_33; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_31 | _pmpHomogeneous_T_34; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_36 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_35; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_37 = _pmpHomogeneous_T_36; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_38 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}] wire [31:0] _GEN_6 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_39; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_39 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_46 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_53 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_40 = ~_pmpHomogeneous_T_39; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_41 = {_pmpHomogeneous_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_42 = ~_pmpHomogeneous_T_41; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_43 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_42}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_45 = |_pmpHomogeneous_T_44; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_52 = |_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_59 = |_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_61 = _pmpHomogeneous_T_60 ? _pmpHomogeneous_T_52 : _pmpHomogeneous_T_45; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_63 = _pmpHomogeneous_T_62 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_61; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_64 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_63; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_66 = pmpHomogeneous_maskHomogeneous_1 | _pmpHomogeneous_T_65; // @[package.scala:39:76] wire _pmpHomogeneous_T_67 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}] wire [55:0] _GEN_7 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_7; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_7; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_69 = pmpHomogeneous_endsBeforeLower_1 | pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_70 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_71 = _pmpHomogeneous_T_69 | _pmpHomogeneous_T_70; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_72 = _pmpHomogeneous_T_68 | _pmpHomogeneous_T_71; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_73 = _pmpHomogeneous_T_38 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_72; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_74 = _pmpHomogeneous_T_37 & _pmpHomogeneous_T_73; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_75 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}] wire [31:0] _GEN_8 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_76; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_76 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_83; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_83 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_90 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_77 = ~_pmpHomogeneous_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_78 = {_pmpHomogeneous_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_79 = ~_pmpHomogeneous_T_78; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_80 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_79}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_81 = _pmpHomogeneous_T_80[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_82 = |_pmpHomogeneous_T_81; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_84 = ~_pmpHomogeneous_T_83; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_85 = {_pmpHomogeneous_T_84[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_86 = ~_pmpHomogeneous_T_85; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_87 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_86}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_88 = _pmpHomogeneous_T_87[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_89 = |_pmpHomogeneous_T_88; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_96 = |_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_98 = _pmpHomogeneous_T_97 ? _pmpHomogeneous_T_89 : _pmpHomogeneous_T_82; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_100 = _pmpHomogeneous_T_99 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_98; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_101 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_100; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_103 = pmpHomogeneous_maskHomogeneous_2 | _pmpHomogeneous_T_102; // @[package.scala:39:76] wire _pmpHomogeneous_T_104 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}] wire [55:0] _GEN_9 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_9; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_9; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_106 = pmpHomogeneous_endsBeforeLower_2 | pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_107 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_108 = _pmpHomogeneous_T_106 | _pmpHomogeneous_T_107; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_109 = _pmpHomogeneous_T_105 | _pmpHomogeneous_T_108; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_110 = _pmpHomogeneous_T_75 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_109; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_111 = _pmpHomogeneous_T_74 & _pmpHomogeneous_T_110; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_112 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}] wire [31:0] _GEN_10 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_113; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_113 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_120; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_120 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_127; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_127 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T_114[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_116 = ~_pmpHomogeneous_T_115; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_117 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_116}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_118 = _pmpHomogeneous_T_117[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_119 = |_pmpHomogeneous_T_118; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_121 = ~_pmpHomogeneous_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_122 = {_pmpHomogeneous_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_123 = ~_pmpHomogeneous_T_122; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_124 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_123}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_125 = _pmpHomogeneous_T_124[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_126 = |_pmpHomogeneous_T_125; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_128 = ~_pmpHomogeneous_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_129 = {_pmpHomogeneous_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_130 = ~_pmpHomogeneous_T_129; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_131 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_130}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_132 = _pmpHomogeneous_T_131[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_133 = |_pmpHomogeneous_T_132; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_135 = _pmpHomogeneous_T_134 ? _pmpHomogeneous_T_126 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_137 = _pmpHomogeneous_T_136 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_135; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_138 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_137; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_140 = pmpHomogeneous_maskHomogeneous_3 | _pmpHomogeneous_T_139; // @[package.scala:39:76] wire _pmpHomogeneous_T_141 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}] wire [55:0] _GEN_11 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_11; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_11; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_143 = pmpHomogeneous_endsBeforeLower_3 | pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_144 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_145 = _pmpHomogeneous_T_143 | _pmpHomogeneous_T_144; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_146 = _pmpHomogeneous_T_142 | _pmpHomogeneous_T_145; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_147 = _pmpHomogeneous_T_112 ? _pmpHomogeneous_T_140 : _pmpHomogeneous_T_146; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_148 = _pmpHomogeneous_T_111 & _pmpHomogeneous_T_147; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_149 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}] wire [31:0] _GEN_12 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_150; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_150 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_157; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_157 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_164; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_164 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T_151[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_153 = ~_pmpHomogeneous_T_152; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_154 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_153}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_155 = _pmpHomogeneous_T_154[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_156 = |_pmpHomogeneous_T_155; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_160 = ~_pmpHomogeneous_T_159; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_161 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_160}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_162 = _pmpHomogeneous_T_161[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_163 = |_pmpHomogeneous_T_162; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_165 = ~_pmpHomogeneous_T_164; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_166 = {_pmpHomogeneous_T_165[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_167 = ~_pmpHomogeneous_T_166; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_168 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_167}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_169 = _pmpHomogeneous_T_168[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_170 = |_pmpHomogeneous_T_169; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_172 = _pmpHomogeneous_T_171 ? _pmpHomogeneous_T_163 : _pmpHomogeneous_T_156; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_173 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_172; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_175 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_175 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_174; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_177 = pmpHomogeneous_maskHomogeneous_4 | _pmpHomogeneous_T_176; // @[package.scala:39:76] wire _pmpHomogeneous_T_178 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}] wire [55:0] _GEN_13 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_13; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_13; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_180 = pmpHomogeneous_endsBeforeLower_4 | pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_181 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_182 = _pmpHomogeneous_T_180 | _pmpHomogeneous_T_181; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_183 = _pmpHomogeneous_T_179 | _pmpHomogeneous_T_182; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_184 = _pmpHomogeneous_T_149 ? _pmpHomogeneous_T_177 : _pmpHomogeneous_T_183; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_185 = _pmpHomogeneous_T_148 & _pmpHomogeneous_T_184; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_186 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}] wire [31:0] _GEN_14 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_187; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_187 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_194; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_194 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_201; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_201 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T_188[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_190 = ~_pmpHomogeneous_T_189; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_191 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_190}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_192 = _pmpHomogeneous_T_191[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_193 = |_pmpHomogeneous_T_192; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T_195[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_197 = ~_pmpHomogeneous_T_196; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_198 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_197}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_199 = _pmpHomogeneous_T_198[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_200 = |_pmpHomogeneous_T_199; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_204 = ~_pmpHomogeneous_T_203; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_205 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_204}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_206 = _pmpHomogeneous_T_205[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_207 = |_pmpHomogeneous_T_206; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_200 : _pmpHomogeneous_T_193; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_212 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_213 = _pmpHomogeneous_T_212 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_211; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_214 = pmpHomogeneous_maskHomogeneous_5 | _pmpHomogeneous_T_213; // @[package.scala:39:76] wire _pmpHomogeneous_T_215 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_216 = ~_pmpHomogeneous_T_215; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}] wire [55:0] _GEN_15 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_15; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_15; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_217 = pmpHomogeneous_endsBeforeLower_5 | pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_218 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_217 | _pmpHomogeneous_T_218; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_216 | _pmpHomogeneous_T_219; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_221 = _pmpHomogeneous_T_186 ? _pmpHomogeneous_T_214 : _pmpHomogeneous_T_220; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_222 = _pmpHomogeneous_T_185 & _pmpHomogeneous_T_221; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_223 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}] wire [31:0] _GEN_16 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_224; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_224 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_231; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_231 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_238; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_238 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T_225[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_227 = ~_pmpHomogeneous_T_226; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_228 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_227}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_229 = _pmpHomogeneous_T_228[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_230 = |_pmpHomogeneous_T_229; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T_232[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_234 = ~_pmpHomogeneous_T_233; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_235 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_234}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_236 = _pmpHomogeneous_T_235[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_237 = |_pmpHomogeneous_T_236; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T_239[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_241 = ~_pmpHomogeneous_T_240; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_242 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_241}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_243 = _pmpHomogeneous_T_242[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_244 = |_pmpHomogeneous_T_243; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_246 = _pmpHomogeneous_T_245 ? _pmpHomogeneous_T_237 : _pmpHomogeneous_T_230; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_246; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_249 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_250 = _pmpHomogeneous_T_249 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_248; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_251 = pmpHomogeneous_maskHomogeneous_6 | _pmpHomogeneous_T_250; // @[package.scala:39:76] wire _pmpHomogeneous_T_252 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_253 = ~_pmpHomogeneous_T_252; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}] wire [55:0] _GEN_17 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_17; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_17; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_254 = pmpHomogeneous_endsBeforeLower_6 | pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_255 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_256 = _pmpHomogeneous_T_254 | _pmpHomogeneous_T_255; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_257 = _pmpHomogeneous_T_253 | _pmpHomogeneous_T_256; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_258 = _pmpHomogeneous_T_223 ? _pmpHomogeneous_T_251 : _pmpHomogeneous_T_257; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_259 = _pmpHomogeneous_T_222 & _pmpHomogeneous_T_258; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_260 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}] wire [31:0] _GEN_18 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_261; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_261 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_268; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_268 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_275; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_275 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_262 = ~_pmpHomogeneous_T_261; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_263 = {_pmpHomogeneous_T_262[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_264 = ~_pmpHomogeneous_T_263; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_265 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_264}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_266 = _pmpHomogeneous_T_265[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_267 = |_pmpHomogeneous_T_266; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T_269[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_271 = ~_pmpHomogeneous_T_270; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_272 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_271}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_273 = _pmpHomogeneous_T_272[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_274 = |_pmpHomogeneous_T_273; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T_276[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_278 = ~_pmpHomogeneous_T_277; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_279 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_278}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_280 = _pmpHomogeneous_T_279[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_281 = |_pmpHomogeneous_T_280; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_283 = _pmpHomogeneous_T_282 ? _pmpHomogeneous_T_274 : _pmpHomogeneous_T_267; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_283; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_286 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_287 = _pmpHomogeneous_T_286 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_285; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_288 = pmpHomogeneous_maskHomogeneous_7 | _pmpHomogeneous_T_287; // @[package.scala:39:76] wire _pmpHomogeneous_T_289 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}] wire [55:0] _GEN_19 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_19; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_19; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_291 = pmpHomogeneous_endsBeforeLower_7 | pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_292 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_293 = _pmpHomogeneous_T_291 | _pmpHomogeneous_T_292; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_294 = _pmpHomogeneous_T_290 | _pmpHomogeneous_T_293; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_260 ? _pmpHomogeneous_T_288 : _pmpHomogeneous_T_294; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire pmpHomogeneous = _pmpHomogeneous_T_259 & _pmpHomogeneous_T_295; // @[PMP.scala:118:8, :138:10] wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76] assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_2_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_3_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _T_171 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60] wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_1_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_2_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_3_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_3_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _gpa_pgoff_T; // @[PTW.scala:615:36] assign _gpa_pgoff_T = _T_171; // @[PTW.scala:566:60, :615:36] wire _l2_refill_T_7; // @[PTW.scala:715:40] assign _l2_refill_T_7 = _T_171; // @[PTW.scala:566:60, :715:40] wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_2_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_3_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_2_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_3_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_2_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_3_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_2_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_3_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_1_resp_bits_gpa_bits_truncIdx = _io_requestor_1_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_1_resp_bits_gpa_bits_T_11 = io_requestor_1_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = _io_requestor_1_resp_bits_gpa_bits_T_11 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_14 = {_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_2_resp_bits_homogeneous_0 = _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_2_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_2_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_2_resp_bits_gpa_bits_T_2 = _io_requestor_2_resp_bits_gpa_bits_T | _io_requestor_2_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_2_resp_bits_gpa_bits_T_4 = _io_requestor_2_resp_bits_gpa_bits_T_2 | _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_7 = {_io_requestor_2_resp_bits_gpa_bits_T_5, _io_requestor_2_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_10 = {_io_requestor_2_resp_bits_gpa_bits_T_8, _io_requestor_2_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_2_resp_bits_gpa_bits_truncIdx = _io_requestor_2_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_2_resp_bits_gpa_bits_T_11 = io_requestor_2_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_12 = _io_requestor_2_resp_bits_gpa_bits_T_11 ? _io_requestor_2_resp_bits_gpa_bits_T_10 : _io_requestor_2_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_13 = _io_requestor_2_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_2_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_2_resp_bits_gpa_bits_T_14 = {_io_requestor_2_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_2_resp_bits_gpa_bits_0 = _io_requestor_2_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_2_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_2_resp_bits_gpa_is_pte_0 = _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_3_resp_bits_homogeneous_0 = _io_requestor_3_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_3_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_3_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_3_resp_bits_gpa_bits_T_2 = _io_requestor_3_resp_bits_gpa_bits_T | _io_requestor_3_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_3_resp_bits_gpa_bits_T_4 = _io_requestor_3_resp_bits_gpa_bits_T_2 | _io_requestor_3_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_3_resp_bits_gpa_bits_T_7 = {_io_requestor_3_resp_bits_gpa_bits_T_5, _io_requestor_3_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_3_resp_bits_gpa_bits_T_10 = {_io_requestor_3_resp_bits_gpa_bits_T_8, _io_requestor_3_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_3_resp_bits_gpa_bits_truncIdx = _io_requestor_3_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_3_resp_bits_gpa_bits_T_11 = io_requestor_3_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_3_resp_bits_gpa_bits_T_12 = _io_requestor_3_resp_bits_gpa_bits_T_11 ? _io_requestor_3_resp_bits_gpa_bits_T_10 : _io_requestor_3_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_3_resp_bits_gpa_bits_T_13 = _io_requestor_3_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_3_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_3_resp_bits_gpa_bits_T_14 = {_io_requestor_3_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_3_resp_bits_gpa_bits_0 = _io_requestor_3_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_3_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_3_resp_bits_gpa_is_pte_0 = _io_requestor_3_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] wire [2:0] next_state; // @[PTW.scala:579:31] wire do_switch; // @[PTW.scala:581:30] wire _T_129 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire _GEN_20 = ~(|state) & _T_129; // @[Decoupled.scala:51:35] wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38] wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26] wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58] wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40] wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40] wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67] wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}] wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32] wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32] wire [2:0] _GEN_21 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24] wire [2:0] _count_T_4; // @[PTW.scala:624:24] assign _count_T_4 = _GEN_21; // @[PTW.scala:624:24] wire [2:0] _count_T_6; // @[PTW.scala:696:22] assign _count_T_6 = _GEN_21; // @[PTW.scala:624:24, :696:22] wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38] assign _aux_count_T_3 = _GEN_21; // @[PTW.scala:624:24, :741:38] wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24] wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26] wire _T_140 = state == 3'h2; // @[PTW.scala:233:22, :583:18] wire _T_141 = state == 3'h4; // @[PTW.scala:233:22, :583:18] wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39] wire _GEN_22 = _T_152 | _T_140; // @[PTW.scala:377:24, :393:26, :583:18] assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _GEN_22) & _T_141 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :583:18, :640:{30,39}] wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45] wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86] wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}] wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64] wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62] wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}] wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64] wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62] wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}] wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}] wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86] wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76] wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26] wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32] wire [43:0] _r_pte_pte_ppn_T_1; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_ppn; // @[PTW.scala:780:26] wire [41:0] _r_pte_pte_ppn_T = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] wire [41:0] _r_pte_pte_ppn_T_2 = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] assign _r_pte_pte_ppn_T_1 = {_r_pte_pte_ppn_T, 2'h0}; // @[PTW.scala:781:{19,30}] assign r_pte_pte_ppn = _r_pte_pte_ppn_T_1; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_7 = _r_pte_T_6 & pte_cache_hit; // @[PTW.scala:367:24, :674:{15,25}] wire [43:0] r_pte_pte_1_ppn; // @[PTW.scala:771:26] assign r_pte_pte_1_ppn = {24'h0, pte_cache_data}; // @[Mux.scala:30:73] wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58] wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27] assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27] wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26] assign _r_pte_pte_ppn_T_3 = {_r_pte_pte_ppn_T_2, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:{19,30}] assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29] wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}] wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}] wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15] wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43] wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}] wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65] wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}] wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}] wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}] wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76] wire _r_pte_T_25 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26] wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26] wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26] wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35] wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35] wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35] wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35] wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35] wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35] wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35] wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35] wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35] wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35] wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_7 ? 10'h0 : _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:{8,25}, :676:8] wire [43:0] _r_pte_T_31_ppn = _r_pte_T_7 ? r_pte_pte_1_ppn : _r_pte_T_30_ppn; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_7 ? 2'h0 : _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_d = ~_r_pte_T_7 & _r_pte_T_30_d; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_a = ~_r_pte_T_7 & _r_pte_T_30_a; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_g = ~_r_pte_T_7 & _r_pte_T_30_g; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_u = ~_r_pte_T_7 & _r_pte_T_30_u; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_x = ~_r_pte_T_7 & _r_pte_T_30_x; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_w = ~_r_pte_T_7 & _r_pte_T_30_w; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_r = ~_r_pte_T_7 & _r_pte_T_30_r; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_v = ~_r_pte_T_7 & _r_pte_T_30_v; // @[PTW.scala:674:{8,25}, :676:8] wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8] wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8] wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8] wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:8, :672:8] wire [43:0] _r_pte_T_33_ppn = _r_pte_T_32_ppn; // @[PTW.scala:670:8, :672:8] wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_d = _r_pte_T_32_d; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_a = _r_pte_T_32_a; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_g = _r_pte_T_32_g; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_u = _r_pte_T_32_u; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_x = _r_pte_T_32_x; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_w = _r_pte_T_32_w; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_r = _r_pte_T_32_r; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_v = _r_pte_T_32_v; // @[PTW.scala:670:8, :672:8] wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22] wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :698:27] wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}] wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44] wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}] wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97] wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}] wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}] wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}] wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22] wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49] wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}] wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30] wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}] wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37] wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}] wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44] wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}] wire _T_168 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :357:107, :701:41, :703:{28,45}] assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_168 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21] wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}] wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61] wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}] wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12] wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65, :714:30] wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}] wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}] wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41] wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}] wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59] wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44] wire _GEN_23 = traverse | _T_168; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19] wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36] wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}] wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26] wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}] wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}] wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}] wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}] wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}] wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}] wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}] wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29] wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26] wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}] wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30] wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}] wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20] wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32] wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39] wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}] wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}] wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}] wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20] wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32] wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39] wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}] wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}] wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}] wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20] wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32] wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39] wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}] wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}] wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_21( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_176( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SourceB.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val param = UInt(3.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val clients = UInt(params.clientBits.W) } class SourceB(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceBRequest(params))) val b = Decoupled(new TLBundleB(params.inner.bundle)) }) if (params.firstLevel) { // Tie off unused ports io.req.ready := true.B io.b.valid := false.B io.b.bits := DontCare } else { val remain = RegInit(0.U(params.clientBits.W)) val remain_set = WireInit(init = 0.U(params.clientBits.W)) val remain_clr = WireInit(init = 0.U(params.clientBits.W)) remain := (remain | remain_set) & ~remain_clr val busy = remain.orR val todo = Mux(busy, remain, io.req.bits.clients) val next = ~(leftOR(todo) << 1) & todo if (params.clientBits > 1) { params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client") } assert (!io.req.valid || io.req.bits.clients =/= 0.U) io.req.ready := !busy when (io.req.fire) { remain_set := io.req.bits.clients } // No restrictions on the type of buffer used here val b = Wire(chiselTypeOf(io.b)) io.b <> params.micro.innerBuf.b(b) b.valid := busy || io.req.valid when (b.fire) { remain_clr := next } params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe") val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire)) val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire)) val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire)) b.bits.opcode := TLMessages.Probe b.bits.param := param b.bits.size := params.offsetBits .U b.bits.source := params.clientSource(next) b.bits.address := params.expandAddress(tag, set, 0.U) b.bits.mask := ~0.U(params.inner.manager.beatBytes.W) b.bits.data := 0.U b.bits.corrupt := false.B } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module SourceB_4( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [8:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [10:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [5:0] io_b_bits_source = 6'h28; // @[SourceB.scala:33:7] wire [5:0] b_bits_source = 6'h28; // @[SourceB.scala:65:17] wire [15:0] io_b_bits_mask = 16'hFFFF; // @[SourceB.scala:33:7] wire [15:0] b_bits_mask = 16'hFFFF; // @[SourceB.scala:65:17] wire [15:0] _b_bits_mask_T = 16'hFFFF; // @[SourceB.scala:81:23] wire [127:0] io_b_bits_data = 128'h0; // @[SourceB.scala:33:7] wire [127:0] b_bits_data = 128'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_lo_lo_hi_hi = 2'h0; // @[Parameters.scala:230:8] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain | remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module TLBuffer_a32d64s1k5z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [4:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_110 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k5z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k5z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_15( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_1477 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1477; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1477; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1550 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1550; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1550; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1550; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1403 = _T_1477 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1403 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1403 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1403 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1403 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1403 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1449 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1449 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1418 = _T_1550 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1418 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1418 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1418 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1521 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1521 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1503 = _T_1550 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1503 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1503 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1503 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_101( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_111 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_52( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_54( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire [2:0] _nodeIn_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala:211:22] wire [1:0] _nodeIn_d_sink_io_deq_bits_param; // @[AsyncQueue.scala:211:22] wire [1:0] _nodeIn_d_sink_io_deq_bits_size; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_source; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala:211:22] wire _nodeOut_a_source_io_enq_ready; // @[AsyncQueue.scala:220:24] TLMonitor_96 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_source_io_enq_ready), // @[AsyncQueue.scala:220:24] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_in_d_bits_opcode (_nodeIn_d_sink_io_deq_bits_opcode), // @[AsyncQueue.scala:211:22] .io_in_d_bits_param (_nodeIn_d_sink_io_deq_bits_param), // @[AsyncQueue.scala:211:22] .io_in_d_bits_size (_nodeIn_d_sink_io_deq_bits_size), // @[AsyncQueue.scala:211:22] .io_in_d_bits_source (_nodeIn_d_sink_io_deq_bits_source), // @[AsyncQueue.scala:211:22] .io_in_d_bits_sink (_nodeIn_d_sink_io_deq_bits_sink), // @[AsyncQueue.scala:211:22] .io_in_d_bits_denied (_nodeIn_d_sink_io_deq_bits_denied), // @[AsyncQueue.scala:211:22] .io_in_d_bits_corrupt (_nodeIn_d_sink_io_deq_bits_corrupt) // @[AsyncQueue.scala:211:22] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_source_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_data (auto_in_a_bits_data), .io_async_mem_0_opcode (auto_out_a_mem_0_opcode), .io_async_mem_0_address (auto_out_a_mem_0_address), .io_async_mem_0_data (auto_out_a_mem_0_data), .io_async_ridx (auto_out_a_ridx), .io_async_widx (auto_out_a_widx), .io_async_safe_ridx_valid (auto_out_a_safe_ridx_valid), .io_async_safe_widx_valid (auto_out_a_safe_widx_valid), .io_async_safe_source_reset_n (auto_out_a_safe_source_reset_n), .io_async_safe_sink_reset_n (auto_out_a_safe_sink_reset_n) ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_sink_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_sink_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_sink_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_sink_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_sink_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_sink_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_sink_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_sink_io_deq_bits_corrupt), .io_async_mem_0_opcode (auto_out_d_mem_0_opcode), .io_async_mem_0_size (auto_out_d_mem_0_size), .io_async_mem_0_source (auto_out_d_mem_0_source), .io_async_mem_0_data (auto_out_d_mem_0_data), .io_async_ridx (auto_out_d_ridx), .io_async_widx (auto_out_d_widx), .io_async_safe_ridx_valid (auto_out_d_safe_ridx_valid), .io_async_safe_widx_valid (auto_out_d_safe_widx_valid), .io_async_safe_source_reset_n (auto_out_d_safe_source_reset_n), .io_async_safe_sink_reset_n (auto_out_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = _nodeOut_a_source_io_enq_ready; // @[AsyncQueue.scala:220:24] assign auto_in_d_valid = _nodeIn_d_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_opcode = _nodeIn_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_param = _nodeIn_d_sink_io_deq_bits_param; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_size = _nodeIn_d_sink_io_deq_bits_size; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_source = _nodeIn_d_sink_io_deq_bits_source; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_sink = _nodeIn_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_denied = _nodeIn_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_corrupt = _nodeIn_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala:211:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File LazyRoCC.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.experimental.IntParam import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.rocket.{ MStatus, HellaCacheIO, TLBPTWIO, CanHavePTW, CanHavePTWModule, SimpleHellaCacheIF, M_XRD, PTE, PRV, M_SZ } import freechips.rocketchip.tilelink.{ TLNode, TLIdentityNode, TLClientNode, TLMasterParameters, TLMasterPortParameters } import freechips.rocketchip.util.InOrderArbiter case object BuildRoCC extends Field[Seq[Parameters => LazyRoCC]](Nil) class RoCCInstruction extends Bundle { val funct = Bits(7.W) val rs2 = Bits(5.W) val rs1 = Bits(5.W) val xd = Bool() val xs1 = Bool() val xs2 = Bool() val rd = Bits(5.W) val opcode = Bits(7.W) } class RoCCCommand(implicit p: Parameters) extends CoreBundle()(p) { val inst = new RoCCInstruction val rs1 = Bits(xLen.W) val rs2 = Bits(xLen.W) val status = new MStatus } class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) { val rd = Bits(5.W) val data = Bits(xLen.W) } class RoCCCoreIO(val nRoCCCSRs: Int = 0)(implicit p: Parameters) extends CoreBundle()(p) { val cmd = Flipped(Decoupled(new RoCCCommand)) val resp = Decoupled(new RoCCResponse) val mem = new HellaCacheIO val busy = Output(Bool()) val interrupt = Output(Bool()) val exception = Input(Bool()) val csrs = Flipped(Vec(nRoCCCSRs, new CustomCSRIO)) } class RoCCIO(val nPTWPorts: Int, nRoCCCSRs: Int)(implicit p: Parameters) extends RoCCCoreIO(nRoCCCSRs)(p) { val ptw = Vec(nPTWPorts, new TLBPTWIO) val fpu_req = Decoupled(new FPInput) val fpu_resp = Flipped(Decoupled(new FPResult)) } /** Base classes for Diplomatic TL2 RoCC units **/ abstract class LazyRoCC( val opcodes: OpcodeSet, val nPTWPorts: Int = 0, val usesFPU: Boolean = false, val roccCSRs: Seq[CustomCSR] = Nil )(implicit p: Parameters) extends LazyModule { val module: LazyRoCCModuleImp require(roccCSRs.map(_.id).toSet.size == roccCSRs.size) val atlNode: TLNode = TLIdentityNode() val tlNode: TLNode = TLIdentityNode() val stlNode: TLNode = TLIdentityNode() } class LazyRoCCModuleImp(outer: LazyRoCC) extends LazyModuleImp(outer) { val io = IO(new RoCCIO(outer.nPTWPorts, outer.roccCSRs.size)) io := DontCare } /** Mixins for including RoCC **/ trait HasLazyRoCC extends CanHavePTW { this: BaseTile => val roccs = p(BuildRoCC).map(_(p)) val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs require(roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size, "LazyRoCC instantiations require overlapping CSRs") roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl } roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl } roccs.map(_.stlNode).foreach { stl => stl :*= tlSlaveXbar.node } nPTWPorts += roccs.map(_.nPTWPorts).sum nDCachePorts += roccs.size } trait HasLazyRoCCModule extends CanHavePTWModule with HasCoreParameters { this: RocketTileModuleImp => val (respArb, cmdRouter) = if(outer.roccs.nonEmpty) { val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size)) val cmdRouter = Module(new RoccCommandRouter(outer.roccs.map(_.opcodes))(outer.p)) outer.roccs.zipWithIndex.foreach { case (rocc, i) => rocc.module.io.ptw ++=: ptwPorts rocc.module.io.cmd <> cmdRouter.io.out(i) val dcIF = Module(new SimpleHellaCacheIF()(outer.p)) dcIF.io.requestor <> rocc.module.io.mem dcachePorts += dcIF.io.cache respArb.io.in(i) <> Queue(rocc.module.io.resp) } (Some(respArb), Some(cmdRouter)) } else { (None, None) } val roccCSRIOs = outer.roccs.map(_.module.io.csrs) } class AccumulatorExample(opcodes: OpcodeSet, val n: Int = 4)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new AccumulatorExampleModuleImp(this) } class AccumulatorExampleModuleImp(outer: AccumulatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with HasCoreParameters { val regfile = Mem(outer.n, UInt(xLen.W)) val busy = RegInit(VecInit(Seq.fill(outer.n){false.B})) val cmd = Queue(io.cmd) val funct = cmd.bits.inst.funct val addr = cmd.bits.rs2(log2Up(outer.n)-1,0) val doWrite = funct === 0.U val doRead = funct === 1.U val doLoad = funct === 2.U val doAccum = funct === 3.U val memRespTag = io.mem.resp.bits.tag(log2Up(outer.n)-1,0) // datapath val addend = cmd.bits.rs1 val accum = regfile(addr) val wdata = Mux(doWrite, addend, accum + addend) when (cmd.fire && (doWrite || doAccum)) { regfile(addr) := wdata } when (io.mem.resp.valid) { regfile(memRespTag) := io.mem.resp.bits.data busy(memRespTag) := false.B } // control when (io.mem.req.fire) { busy(addr) := true.B } val doResp = cmd.bits.inst.xd val stallReg = busy(addr) val stallLoad = doLoad && !io.mem.req.ready val stallResp = doResp && !io.resp.ready cmd.ready := !stallReg && !stallLoad && !stallResp // command resolved if no stalls AND not issuing a load that will need a request // PROC RESPONSE INTERFACE io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad // valid response if valid command, need a response, and no stalls io.resp.bits.rd := cmd.bits.inst.rd // Must respond with the appropriate tag or undefined behavior io.resp.bits.data := accum // Semantics is to always send out prior accumulator register value io.busy := cmd.valid || busy.reduce(_||_) // Be busy when have pending memory requests or committed possibility of pending requests io.interrupt := false.B // Set this true to trigger an interrupt on the processor (please refer to supervisor documentation) // MEMORY REQUEST INTERFACE io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp io.mem.req.bits.addr := addend io.mem.req.bits.tag := addr io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores) io.mem.req.bits.size := log2Ceil(8).U io.mem.req.bits.signed := false.B io.mem.req.bits.data := 0.U // we're not performing any stores... io.mem.req.bits.phys := false.B io.mem.req.bits.dprv := cmd.bits.status.dprv io.mem.req.bits.dv := cmd.bits.status.dv io.mem.req.bits.no_resp := false.B } class TranslatorExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes, nPTWPorts = 1) { override lazy val module = new TranslatorExampleModuleImp(this) } class TranslatorExampleModuleImp(outer: TranslatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with HasCoreParameters { val req_addr = Reg(UInt(coreMaxAddrBits.W)) val req_rd = Reg(chiselTypeOf(io.resp.bits.rd)) val req_offset = req_addr(pgIdxBits - 1, 0) val req_vpn = req_addr(coreMaxAddrBits - 1, pgIdxBits) val pte = Reg(new PTE) val s_idle :: s_ptw_req :: s_ptw_resp :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.cmd.ready := (state === s_idle) when (io.cmd.fire) { req_rd := io.cmd.bits.inst.rd req_addr := io.cmd.bits.rs1 state := s_ptw_req } private val ptw = io.ptw(0) when (ptw.req.fire) { state := s_ptw_resp } when (state === s_ptw_resp && ptw.resp.valid) { pte := ptw.resp.bits.pte state := s_resp } when (io.resp.fire) { state := s_idle } ptw.req.valid := (state === s_ptw_req) ptw.req.bits.valid := true.B ptw.req.bits.bits.addr := req_vpn io.resp.valid := (state === s_resp) io.resp.bits.rd := req_rd io.resp.bits.data := Mux(pte.leaf(), Cat(pte.ppn, req_offset), -1.S(xLen.W).asUInt) io.busy := (state =/= s_idle) io.interrupt := false.B io.mem.req.valid := false.B } class CharacterCountExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new CharacterCountExampleModuleImp(this) override val atlNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("CharacterCountRoCC"))))) } class CharacterCountExampleModuleImp(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with HasCoreParameters with HasL1CacheParameters { val cacheParams = tileParams.dcache.get private val blockOffset = blockOffBits private val beatOffset = log2Up(cacheDataBits/8) val needle = Reg(UInt(8.W)) val addr = Reg(UInt(coreMaxAddrBits.W)) val count = Reg(UInt(xLen.W)) val resp_rd = Reg(chiselTypeOf(io.resp.bits.rd)) val addr_block = addr(coreMaxAddrBits - 1, blockOffset) val offset = addr(blockOffset - 1, 0) val next_addr = (addr_block + 1.U) << blockOffset.U val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(5) val state = RegInit(s_idle) val (tl_out, edgesOut) = outer.atlNode.out(0) val gnt = tl_out.d.bits val recv_data = Reg(UInt(cacheDataBits.W)) val recv_beat = RegInit(0.U(log2Up(cacheDataBeats+1).W)) val data_bytes = VecInit(Seq.tabulate(cacheDataBits/8) { i => recv_data(8 * (i + 1) - 1, 8 * i) }) val zero_match = data_bytes.map(_ === 0.U) val needle_match = data_bytes.map(_ === needle) val first_zero = PriorityEncoder(zero_match) val chars_found = PopCount(needle_match.zipWithIndex.map { case (matches, i) => val idx = Cat(recv_beat - 1.U, i.U(beatOffset.W)) matches && idx >= offset && i.U <= first_zero }) val zero_found = zero_match.reduce(_ || _) val finished = Reg(Bool()) io.cmd.ready := (state === s_idle) io.resp.valid := (state === s_resp) io.resp.bits.rd := resp_rd io.resp.bits.data := count tl_out.a.valid := (state === s_acq) tl_out.a.bits := edgesOut.Get( fromSource = 0.U, toAddress = addr_block << blockOffset, lgSize = lgCacheBlockBytes.U)._2 tl_out.d.ready := (state === s_gnt) when (io.cmd.fire) { addr := io.cmd.bits.rs1 needle := io.cmd.bits.rs2 resp_rd := io.cmd.bits.inst.rd count := 0.U finished := false.B state := s_acq } when (tl_out.a.fire) { state := s_gnt } when (tl_out.d.fire) { recv_beat := recv_beat + 1.U recv_data := gnt.data state := s_check } when (state === s_check) { when (!finished) { count := count + chars_found } when (zero_found) { finished := true.B } when (recv_beat === cacheDataBeats.U) { addr := next_addr state := Mux(zero_found || finished, s_resp, s_acq) recv_beat := 0.U } .otherwise { state := s_gnt } } when (io.resp.fire) { state := s_idle } io.busy := (state =/= s_idle) io.interrupt := false.B io.mem.req.valid := false.B // Tie off unused channels tl_out.b.ready := true.B tl_out.c.valid := false.B tl_out.e.valid := false.B } class BlackBoxExample(opcodes: OpcodeSet, blackBoxFile: String)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new BlackBoxExampleModuleImp(this, blackBoxFile) } class BlackBoxExampleModuleImp(outer: BlackBoxExample, blackBoxFile: String)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with RequireSyncReset with HasCoreParameters { val blackbox = { val roccIo = io Module( new BlackBox( Map( "xLen" -> IntParam(xLen), "PRV_SZ" -> IntParam(PRV.SZ), "coreMaxAddrBits" -> IntParam(coreMaxAddrBits), "dcacheReqTagBits" -> IntParam(roccIo.mem.req.bits.tag.getWidth), "M_SZ" -> IntParam(M_SZ), "mem_req_bits_size_width" -> IntParam(roccIo.mem.req.bits.size.getWidth), "coreDataBits" -> IntParam(coreDataBits), "coreDataBytes" -> IntParam(coreDataBytes), "paddrBits" -> IntParam(paddrBits), "vaddrBitsExtended" -> IntParam(vaddrBitsExtended), "FPConstants_RM_SZ" -> IntParam(FPConstants.RM_SZ), "fLen" -> IntParam(fLen), "FPConstants_FLAGS_SZ" -> IntParam(FPConstants.FLAGS_SZ) ) ) with HasBlackBoxResource { val io = IO( new Bundle { val clock = Input(Clock()) val reset = Input(Reset()) val rocc = chiselTypeOf(roccIo) }) override def desiredName: String = blackBoxFile addResource(s"/vsrc/$blackBoxFile.v") } ) } blackbox.io.clock := clock blackbox.io.reset := reset blackbox.io.rocc.cmd <> io.cmd io.resp <> blackbox.io.rocc.resp io.mem <> blackbox.io.rocc.mem io.busy := blackbox.io.rocc.busy io.interrupt := blackbox.io.rocc.interrupt blackbox.io.rocc.exception := io.exception io.ptw <> blackbox.io.rocc.ptw io.fpu_req <> blackbox.io.rocc.fpu_req blackbox.io.rocc.fpu_resp <> io.fpu_resp } class OpcodeSet(val opcodes: Seq[UInt]) { def |(set: OpcodeSet) = new OpcodeSet(this.opcodes ++ set.opcodes) def matches(oc: UInt) = opcodes.map(_ === oc).reduce(_ || _) } object OpcodeSet { def custom0 = new OpcodeSet(Seq("b0001011".U)) def custom1 = new OpcodeSet(Seq("b0101011".U)) def custom2 = new OpcodeSet(Seq("b1011011".U)) def custom3 = new OpcodeSet(Seq("b1111011".U)) def all = custom0 | custom1 | custom2 | custom3 } class RoccCommandRouter(opcodes: Seq[OpcodeSet])(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val in = Flipped(Decoupled(new RoCCCommand)) val out = Vec(opcodes.size, Decoupled(new RoCCCommand)) val busy = Output(Bool()) }) val cmd = Queue(io.in) val cmdReadys = io.out.zip(opcodes).map { case (out, opcode) => val me = opcode.matches(cmd.bits.inst.opcode) out.valid := cmd.valid && me out.bits := cmd.bits out.ready && me } cmd.ready := cmdReadys.reduce(_ || _) io.busy := cmd.valid assert(PopCount(cmdReadys) <= 1.U, "Custom opcode matched for more than one accelerator") } File LoopConv.scala: package gemmini import chisel3._ import chisel3.util._ import chisel3.experimental._ import freechips.rocketchip.tile.RoCCCommand import org.chipsalliance.cde.config.Parameters import GemminiISA._ import LocalAddr._ import Util._ class LoopConvOuterBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val batch_size = UInt(large_iterator_bitwidth.W) val in_row_dim = UInt(small_iterator_bitwidth.W) val in_col_dim = UInt(small_iterator_bitwidth.W) val in_channels = UInt(large_iterator_bitwidth.W) val out_channels = UInt(large_iterator_bitwidth.W) val out_col_dim = UInt(large_iterator_bitwidth.W) val out_row_dim = UInt(large_iterator_bitwidth.W) val out_stride = UInt(large_iterator_bitwidth.W) //stride for output activation val in_stride = UInt(large_iterator_bitwidth.W) //stride for input activation val weight_stride = UInt(large_iterator_bitwidth.W) //stride for weight val pool_out_row_dim = UInt(small_iterator_bitwidth.W) val pool_out_col_dim = UInt(small_iterator_bitwidth.W) val stride = UInt(tiny_iterator_bitwidth.W) val padding = UInt(tiny_iterator_bitwidth.W) val kernel_dim = UInt(tiny_iterator_bitwidth.W) val kernel_dilation = UInt(tiny_iterator_bitwidth.W) val pool_size = UInt(tiny_iterator_bitwidth.W) val pool_stride = UInt(tiny_iterator_bitwidth.W) val pool_padding = UInt(tiny_iterator_bitwidth.W) } class LoopConvInnerBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val batches = UInt(large_iterator_bitwidth.W) val porows = UInt(small_iterator_bitwidth.W) val pocols = UInt(small_iterator_bitwidth.W) val pochs = UInt(large_iterator_bitwidth.W) val krows = UInt(tiny_iterator_bitwidth.W) val kcols = UInt(tiny_iterator_bitwidth.W) val kchs = UInt(large_iterator_bitwidth.W) val lpad = UInt(tiny_iterator_bitwidth.W) val rpad = UInt(tiny_iterator_bitwidth.W) val upad = UInt(tiny_iterator_bitwidth.W) val dpad = UInt(tiny_iterator_bitwidth.W) val plpad = UInt(tiny_iterator_bitwidth.W) val prad = UInt(tiny_iterator_bitwidth.W) val pupad = UInt(tiny_iterator_bitwidth.W) val pdpad = UInt(tiny_iterator_bitwidth.W) val orows = UInt(small_iterator_bitwidth.W) val ocols = UInt(small_iterator_bitwidth.W) } class LoopConvDerivedParams(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle { val ochs = UInt(large_iterator_bitwidth.W) val irows = UInt(small_iterator_bitwidth.W) val icols = UInt(small_iterator_bitwidth.W) val irows_unpadded = UInt(small_iterator_bitwidth.W) val icols_unpadded = UInt(small_iterator_bitwidth.W) val ichs = UInt(large_iterator_bitwidth.W) val out_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size val in_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size val bias_spad_stride = UInt(large_iterator_bitwidth.W) val input_spad_stride = UInt(large_iterator_bitwidth.W) val weight_spad_stride = UInt(large_iterator_bitwidth.W) // val ex_overwrite = Bool() } class LoopConvLdBiasReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val no_bias = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdBias(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, acc_w: Int, max_block_len_acc: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)) import req.inner_bounds._ import req.derived_params._ val acc_addr_start = req.addr_start // Derived parameters val max_ochs_per_mvin = Mux(ochs < (max_block_len_acc * block_size).U, ochs, (max_block_len_acc * block_size).U) val skip = req.dram_addr === 0.U // Iterators val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) val och = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = och * (acc_w/8).U val dram_addr = Mux(req.no_bias, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset)) val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // Sizes val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol) val J = Mux(ochs - och > max_ochs_per_mvin, max_ochs_per_mvin, ochs - och) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val I = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := req.derived_params.bias_spad_stride config_cmd_rs1.pixel_repeats := 1.U config_cmd_rs1.state_id := 2.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := 0.U val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD3_CMD mvin_cmd.rs1 := 0.U mvin_cmd.rs2 := 0.U // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && !skip command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD3_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := o.I.asUInt mvin_cmd_rs2.num_cols := o.J.asUInt mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when (skip) { state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val next_och = floorAdd(och, max_ochs_per_mvin, ochs) val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U) val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U) och := next_och ocol := next_ocol orow := next_orow b := next_b state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config b := 0.U orow := 0.U ocol := 0.U och := 0.U } } class LoopConvLdInputReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val downsample = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val input_dilated = Bool() val trans_input_3120 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdInput(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2) (implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated // Derived parameters val max_ichs_per_mvin = Mux(ichs < (max_block_len * block_size).U, ichs, (max_block_len * block_size).U).zext val max_batches_per_mvin = Mux(batches < (max_block_len * block_size).U, batches, (max_block_len * block_size).U).zext val max_chs_per_mvin = Mux(req.trans_input_3120, max_batches_per_mvin, max_ichs_per_mvin) // Iterators val b = Reg(SInt(large_iterator_bitwidth.W)) val irow = Reg(SInt(small_iterator_bitwidth.W)) val icol = Reg(SInt(small_iterator_bitwidth.W)) val ich = Reg(SInt(large_iterator_bitwidth.W)) // Calculated params val irow_padded = irow +& undilated(upad).zext val icol_padded = icol +& undilated(lpad).zext val is_zeros = irow < 0.S || irow >= irows_unpadded.zext || icol < 0.S || icol >= icols_unpadded.zext val dram_stride = Mux(req.trans_input_3120, batch_size * (input_w/8).U, in_stride * (input_w/8).U) // Addresses val dram_offset = Mux(req.trans_input_3120, (((ich * in_col_dim * in_row_dim +& irow*in_col_dim +& icol) * batches +& b) * (input_w/8).U).asUInt, (((b * in_row_dim * in_col_dim +& irow*in_col_dim +& icol) * in_stride +& ich) * (input_w/8).U).asUInt) val dram_addr = Mux(is_zeros, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset)) val spad_addr = Mux(req.trans_input_3120, // To prevent Verilator errors, we replace some "/ block_size.U" calls here with ">> log2Up(block_size)" req.addr_start.zext +& (b >> log2Up(block_size)) * input_spad_stride +& ich * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample), req.addr_start.zext +& (ich >> log2Up(block_size)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample)) // Sizes val block_size_downsampled = (block_size.U << req.downsample).asUInt.zext val I = MuxCase( Mux(icols_unpadded.zext -& icol > block_size_downsampled, block_size_downsampled, icols_unpadded.zext -& icol), Seq( (icol < 0.S) -> Mux((0.S-&icol) > block_size.S, block_size.S, 0.S-&icol), (icol >= icols_unpadded.zext) -> Mux(icols_unpadded.zext +& undilated(rpad).zext -& icol > block_size.S, block_size.S, icols_unpadded.zext +& undilated(rpad).zext -& icol) ) ) val K = Mux(req.trans_input_3120, Mux(batches.zext -& b > max_chs_per_mvin, max_chs_per_mvin, batches.zext -& b), Mux(ichs.zext -& ich > max_chs_per_mvin, max_chs_per_mvin, ichs.zext -& ich)) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = SInt() val I = SInt() val K = SInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := input_spad_stride config_cmd_rs1.pixel_repeats := req.max_pixels_per_row config_cmd_rs1.state_id := 0.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := dram_stride << req.downsample val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD_CMD mvin_cmd.rs1 := 0.U // dram_addr mvin_cmd.rs2 := 0.U // mvin_cmd_rs2 // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U) command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.I := I command_p.io.in.bits.K := K command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := (o.I >> req.downsample).asUInt mvin_cmd_rs2.num_cols := o.K.asUInt mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when(req.dram_addr === 0.U){ state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val b_it = Mux(req.trans_input_3120, max_chs_per_mvin.asUInt, 1.U) val ich_it = Mux(req.trans_input_3120, 1.U, max_chs_per_mvin.asUInt) val next_ich = sFloorAdd(ich, ich_it, ichs.zext, 0.S) val next_icol = sFloorAdd(icol, I.asUInt, (icols_unpadded +& undilated(rpad)).zext, 0.S-&undilated(lpad).zext, next_ich === 0.S) val next_irow = sFloorAdd(irow, 1.U << req.downsample, (irows_unpadded +& undilated(dpad)).zext, 0.S-&undilated(upad).zext, next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S) val next_b = sFloorAdd(b, b_it, batches.zext, 0.S, next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S) ich := next_ich icol := next_icol irow := next_irow b := next_b state := Mux(next_b === 0.S && next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config b := 0.S irow := 0.S -& ((io.req.bits.inner_bounds.upad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext icol := 0.S -& ((io.req.bits.inner_bounds.lpad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext ich := 0.S } } class LoopConvLdWeightReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_end = UInt(log2Up(max_addr+1).W) val dram_addr = UInt(coreMaxAddrBits.W) val trans_weight_1203 = Bool() val trans_weight_0132 = Bool() val dw = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvLdWeight(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module { val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val wait_for_prev_loop = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ // Derived parameters val max_chs_per_mvin = { val max_ochs_per_mvin = Mux(ochs < (max_block_len * block_size).U, ochs, (max_block_len * block_size).U) val max_kchs_per_mvin = Mux(kchs < (max_block_len * block_size).U, kchs, (max_block_len * block_size).U) Mux(req.trans_weight_0132, max_kchs_per_mvin, max_ochs_per_mvin) } val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs, out_channels_per_bank * kcols * krows * kchs) val addr_start = req.addr_end - B_rows val dram_stride = MuxCase(weight_stride, Seq( req.dw -> 1.U, req.trans_weight_1203 -> (kernel_dim * kernel_dim * out_channels), req.trans_weight_0132 -> in_channels )) * (input_w/8).U // Iterators val och = Reg(UInt(large_iterator_bitwidth.W)) val krow = Reg(UInt(tiny_iterator_bitwidth.W)) val kcol = Reg(UInt(tiny_iterator_bitwidth.W)) val kch = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = MuxCase(((krow*kernel_dim*in_channels +& kcol*in_channels +& kch) * weight_stride +& och) * (input_w/8).U, Seq( req.dw -> (krow * kernel_dim +& kcol) * (input_w/8).U, req.trans_weight_1203 -> (((kch*kernel_dim*kernel_dim +& krow*kernel_dim +& kcol) * out_channels +& och) * (input_w/8).U), req.trans_weight_0132 -> (((krow*kernel_dim*out_channels +& kcol*out_channels +& och) * in_channels +& kch) * (input_w/8).U) )) val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset) val spad_addr = Mux(req.trans_weight_0132, // The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier addr_start + (kch / block_size.U(kch.getWidth.W)) * krows * kcols * ochs + krow * kcols * ochs + kcol * ochs + och, addr_start + (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs + krow * kcols * kchs + kcol * kchs + kch) // Sizes val J = Mux(req.trans_weight_0132, Mux(kchs - kch > max_chs_per_mvin, max_chs_per_mvin, kchs - kch), Mux(ochs - och > max_chs_per_mvin, max_chs_per_mvin, ochs - och)) val K = Mux(req.trans_weight_0132, Mux(ochs - och > block_size.U, block_size.U, ochs - och), Mux(kchs - kch > block_size.U, block_size.U, kchs - kch)) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val K = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.scale := MVIN_SCALE_IDENTITY config_cmd_rs1.stride := req.derived_params.weight_spad_stride config_cmd_rs1.pixel_repeats := 1.U config_cmd_rs1.state_id := 1.U config_cmd_rs1.shrink := 0.U config_cmd_rs1._unused := 1.U config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := dram_stride val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD2_CMD mvin_cmd.rs1 := 0.U // dram_addr mvin_cmd.rs2 := 0.U // mvin_cmd_rs2 // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U) command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd) command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.K := K command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === LOAD2_CMD) { val o = command_p.io.out.bits io.cmd.bits.rs1 := o.dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := o.K mvin_cmd_rs2.num_cols := o.J mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr) io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt } // Sending outputs when(req.dram_addr === 0.U){ state := idle }.elsewhen(command_p.io.in.fire) { when (state === config) { state := ld }.otherwise { val och_it = Mux(req.trans_weight_0132, block_size.U, max_chs_per_mvin) val kch_it = Mux(req.trans_weight_0132, max_chs_per_mvin, block_size.U) val next_kch = floorAdd(kch, kch_it, kchs) val next_kcol = floorAdd(kcol, 1.U, kcols, next_kch === 0.U) val next_krow = floorAdd(krow, 1.U, krows, next_kcol === 0.U && next_kch === 0.U) val next_och = floorAdd(och, och_it, ochs, next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U) kch := next_kch kcol := next_kcol krow := next_krow och := next_och state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U, idle, ld) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := config kch := 0.U kcol := 0.U krow := 0.U och := 0.U } } class LoopConvExecuteReq(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) val c_addr_start = UInt(log2Up(max_acc_addr).W) val wrot180 = Bool() val downsample = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val input_dilated = Bool() val trans_weight_0132 = Bool() val trans_input_3120 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvExecute(block_size: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, max_acc_addr: Int, concurrent_loops: Int, latency: Int, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val lda_completed = Input(Bool()) val ldb_completed = Input(Bool()) val ldd_completed = Input(Bool()) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, config, pre, comp = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated // Derived parameters val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs, out_channels_per_bank * kcols * krows * kchs) val a_addr_start = req.a_addr_start val b_addr_start = req.b_addr_end - B_rows val c_addr_start = /*(BigInt(3) << 30).U |*/ req.c_addr_start // Iterators val och = Reg(UInt(large_iterator_bitwidth.W)) val krow = Reg(UInt(tiny_iterator_bitwidth.W)) val kcol = Reg(UInt(tiny_iterator_bitwidth.W)) val kch = Reg(UInt(large_iterator_bitwidth.W)) val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) // TODO kernel-dilation and input-dilation can never be activated at the same time, so we can optimize out some multiplications by kernel_dilation val skip_iteration = state >= pre && req.input_dilated && (((krow * kernel_dilation +& orow -& upad)(0) & req.input_dilated).asBool || ((kcol * kernel_dilation +& ocol -& lpad)(0) & req.input_dilated).asBool) val pixels = Mux(kcols - kcol > req.max_pixels_per_row, req.max_pixels_per_row, kcols - kcol) val irow = undilated(orow * stride +& krow * kernel_dilation) val icol = undilated(ocol * stride +& kcol * kernel_dilation) val I = Mux(req.trans_input_3120, Mux(batches - b > block_size.U, block_size.U, batches - b), undilated(Mux(ocols - ocol > (block_size.U << req.input_dilated).asUInt, (block_size.U << req.input_dilated).asUInt, ocols - ocol))) val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och) val K = pixels * Mux(kchs - kch > block_size.U, block_size.U, kchs - kch) // Addresses val a_addr = Mux(req.trans_input_3120, a_addr_start +& (b / block_size.U) * input_spad_stride +& kch * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample), a_addr_start +& (kch / block_size.U(kch.getWidth.W)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample)) // val c_addr = Mux(ex_overwrite && krow === 0.U && kcol === 0.U && kch === 0.U, d_addr_start, c_addr_start) +& // (och / block_size.U) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier val c_addr = c_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol // val new_weights = b === 0.U && orow === 0.U && ocol === 0.U val new_weights = Reg(Bool()) val krow_rot = Mux(req.wrot180, krows - krow - 1.U, krow) val kcol_rot = Mux(req.wrot180, kcols - kcol - 1.U, kcol) val b_addr = Mux(req.trans_weight_0132, b_addr_start +& (kch / block_size.U(och.getWidth.W)) * krows * kcols * ochs +& krow_rot * kcols * ochs +& kcol_rot * ochs +& och, b_addr_start +& (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs +& krow_rot * kcols * kchs +& kcol_rot * kchs +& kch) class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val a_addr = UInt() val b_addr = UInt() val c_addr = UInt() val I = UInt() val J = UInt() val K = UInt() val new_weights = Bool() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val config_cmd = Wire(new RoCCCommand) config_cmd := DontCare config_cmd.inst.funct := CONFIG_CMD val config_cmd_rs1 = Wire(config_ex_rs1_t.cloneType) config_cmd_rs1 := DontCare config_cmd_rs1.a_stride := (irows * icols).asUInt config_cmd_rs1.set_only_strides := 1.U config_cmd_rs1.cmd_type := 0.U val config_cmd_rs2 = Wire(new ConfigExRs2) config_cmd_rs2 := DontCare config_cmd_rs2.c_stride := (orows * ocols).asUInt config_cmd.rs1 := config_cmd_rs1.asUInt config_cmd.rs2 := config_cmd_rs2.asUInt val pre_cmd = Wire(new RoCCCommand) // preload pre_cmd := DontCare pre_cmd.inst.funct := PRELOAD_CMD pre_cmd.rs1 := 0.U//(K << 48) | (J << 32) | pre_addr pre_cmd.rs2 := 0.U//(I << 48) | (J << 32) | c_addr val comp_cmd = Wire(new RoCCCommand()) // compute.preloaded comp_cmd := DontCare comp_cmd.inst.funct := Mux(new_weights, COMPUTE_AND_FLIP_CMD, COMPUTE_AND_STAY_CMD) comp_cmd.rs1 := 0.U//(I << 48) | (K << 32) | a_addr comp_cmd.rs2 := 0.U//(I << 48) | (J << 32) | GARBAGE_ADDR val ld_ahead = io.lda_completed && io.ldb_completed && io.ldd_completed // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !skip_iteration && ld_ahead command_p.io.in.bits.cmd := MuxCase(config_cmd, Seq((state === pre) -> pre_cmd, (state === comp) -> comp_cmd)) command_p.io.in.bits.a_addr := a_addr command_p.io.in.bits.b_addr := b_addr command_p.io.in.bits.c_addr := c_addr command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.in.bits.K := K command_p.io.in.bits.new_weights := new_weights command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === PRELOAD_CMD) { val o = command_p.io.out.bits val pre_cmd_rs1 = Wire(preload_rs1_t.cloneType) pre_cmd_rs1 := DontCare pre_cmd_rs1.num_rows := o.K.asUInt pre_cmd_rs1.num_cols := o.J.asUInt pre_cmd_rs1.local_addr := Mux(o.new_weights, cast_to_sp_addr(pre_cmd_rs1.local_addr, o.b_addr), garbage_addr(pre_cmd_rs1.local_addr)) val pre_cmd_rs2 = Wire(preload_rs2_t.cloneType) pre_cmd_rs2 := DontCare pre_cmd_rs2.num_rows := o.I.asUInt pre_cmd_rs2.num_cols := o.J.asUInt pre_cmd_rs2.local_addr := cast_to_acc_addr(pre_cmd_rs2.local_addr, o.c_addr, accumulate = true.B, read_full = false.B) io.cmd.bits.rs1 := pre_cmd_rs1.asUInt io.cmd.bits.rs2 := pre_cmd_rs2.asUInt }.elsewhen(command_p.io.out.bits.cmd.inst.funct =/= CONFIG_CMD) { val o = command_p.io.out.bits val comp_cmd_rs1 = Wire(compute_rs1_t.cloneType) comp_cmd_rs1 := DontCare comp_cmd_rs1.num_rows := o.I.asUInt comp_cmd_rs1.num_cols := o.K.asUInt comp_cmd_rs1.local_addr := cast_to_sp_addr(comp_cmd_rs1.local_addr, o.a_addr) val comp_cmd_rs2 = Wire(compute_rs2_t.cloneType) comp_cmd_rs2 := DontCare comp_cmd_rs2.num_rows := o.I.asUInt comp_cmd_rs2.num_cols := o.J.asUInt comp_cmd_rs2.local_addr := garbage_addr(comp_cmd_rs2.local_addr) io.cmd.bits.rs1 := comp_cmd_rs1.asUInt io.cmd.bits.rs2 := comp_cmd_rs2.asUInt } // Updating "new_weights" when (state === comp && command_p.io.in.fire) { new_weights := false.B } // Sending outputs when (command_p.io.in.fire || skip_iteration) { when (state === config) { state := pre }.elsewhen (state === pre) { state := comp }.otherwise { val b_it = Mux(req.trans_input_3120, block_size.U, 1.U) val ocol_it = Mux(skip_iteration || req.trans_input_3120, 1.U, block_size.U << req.input_dilated).asUInt val next_ocol = floorAdd(ocol, ocol_it, ocols) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U) val next_b = floorAdd(b, b_it, batches, next_orow === 0.U && next_ocol === 0.U) val next_kch = floorAdd(kch, block_size.U, kchs, next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_kcol = floorAdd(kcol, req.max_pixels_per_row, kcols, next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_krow = floorAdd(krow, 1.U, krows, next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) val next_och = floorAdd(och, block_size.U, ochs, next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) ocol := next_ocol orow := next_orow b := next_b kch := next_kch kcol := next_kcol krow := next_krow och := next_och when (next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) { new_weights := true.B } state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U, idle, pre) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := Mux(io.req.bits.trans_input_3120, config, pre) b := 0.U orow := 0.U ocol := 0.U och := 0.U krow := 0.U kcol := 0.U kch := 0.U new_weights := true.B } } class LoopConvStReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val addr_start = UInt(log2Up(max_acc_addr).W) val dram_addr = UInt(coreMaxAddrBits.W) val no_pool = Bool() val activation = UInt(2.W) // TODO magic number val trans_output_1203 = Bool() val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopConvSt(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, input_w: Int, concurrent_loops: Int, latency: Int, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2)(implicit p: Parameters) extends Module { val ACC_SCALE_NO_CHANGE = ~(0.U(32.W)) // TODO get this from ISA description somehow val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val ex_completed = Input(Bool()) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, st, pre_pool_config, pool, post_pool_config = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)) import req.outer_bounds._ import req.inner_bounds._ import req.derived_params._ val acc_addr_start = req.addr_start // Derived parameters val skip = req.dram_addr === 0.U // Iterators val b = Reg(UInt(large_iterator_bitwidth.W)) val orow = Reg(UInt(small_iterator_bitwidth.W)) val ocol = Reg(UInt(small_iterator_bitwidth.W)) val och = Reg(UInt(large_iterator_bitwidth.W)) // Addresses val dram_offset = Mux(req.trans_output_1203, ((orow*out_col_dim*batch_size +& ocol*batch_size +& b) * out_channels +& och) * (input_w/8).U, ((b*out_row_dim*out_col_dim +& orow*out_col_dim +& ocol) * out_stride +& och) * (input_w/8).U) val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset) val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol val pool_dram_addr = req.dram_addr + ((b * pool_out_col_dim * pool_out_row_dim) * out_stride + och) * (input_w/8).U val pool_spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols // Sizes val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol) val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och) val channels = J class RoCCCommandWithAddr extends Bundle { val cmd = new RoCCCommand val dram_addr = UInt() val spad_addr = UInt() val pool_dram_addr = UInt() val pool_spad_addr = UInt() val channels = UInt() val is_pool = Bool() val I = UInt() val J = UInt() } val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)()) // Commands val mvout_cmd = Wire(new RoCCCommand) mvout_cmd := DontCare mvout_cmd.inst.funct := STORE_CMD mvout_cmd.rs1 := 0.U // dram_addr mvout_cmd.rs2 := 0.U // mvout_cmd_rs2 val pre_pool_config_cmd = Wire(new RoCCCommand) pre_pool_config_cmd := DontCare pre_pool_config_cmd.inst.funct := CONFIG_CMD val pre_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1) pre_pool_config_cmd_rs1 := DontCare pre_pool_config_cmd_rs1.ocols := ocols pre_pool_config_cmd_rs1.orows := orows pre_pool_config_cmd_rs1.pocols := pocols pre_pool_config_cmd_rs1.porows := porows pre_pool_config_cmd_rs1.pool_out_dim := pool_out_col_dim pre_pool_config_cmd_rs1.lpad := plpad pre_pool_config_cmd_rs1.upad := pupad pre_pool_config_cmd_rs1.pool_size := pool_size pre_pool_config_cmd_rs1.pool_stride := pool_stride pre_pool_config_cmd_rs1.activation := req.activation pre_pool_config_cmd_rs1.cmd_type := CONFIG_STORE pre_pool_config_cmd.rs1 := pre_pool_config_cmd_rs1.asUInt val pre_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType) pre_pool_config_cmd_rs2 := DontCare pre_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE pre_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U pre_pool_config_cmd.rs2 := pre_pool_config_cmd_rs2.asUInt val post_pool_config_cmd = Wire(new RoCCCommand) post_pool_config_cmd := DontCare post_pool_config_cmd.inst.funct := CONFIG_CMD val post_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1) post_pool_config_cmd_rs1 := DontCare post_pool_config_cmd_rs1.activation := req.activation post_pool_config_cmd_rs1.cmd_type := CONFIG_STORE post_pool_config_cmd.rs1 := post_pool_config_cmd_rs1.asUInt val post_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType) post_pool_config_cmd_rs2 := DontCare post_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE post_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U post_pool_config_cmd.rs2 := post_pool_config_cmd_rs2.asUInt val pool_cmd = Wire(new RoCCCommand) pool_cmd := DontCare pool_cmd.inst.funct := STORE_CMD pool_cmd.rs1 := 0.U//pool_dram_addr pool_cmd.rs2 := 0.U//(channels << 32.U) | pool_spad_addr // Inputs and outputs io.req.ready := state === idle && !command_p.io.busy io.idle := state === idle && !command_p.io.busy io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !skip && io.ex_completed command_p.io.in.bits.cmd := MuxLookup(state.asUInt, mvout_cmd)(Seq( pre_pool_config.asUInt -> pre_pool_config_cmd, pool.asUInt -> pool_cmd, post_pool_config.asUInt -> post_pool_config_cmd) ) command_p.io.in.bits.is_pool := state === pool command_p.io.in.bits.dram_addr := dram_addr command_p.io.in.bits.spad_addr := spad_addr command_p.io.in.bits.pool_spad_addr := pool_spad_addr command_p.io.in.bits.pool_dram_addr := pool_dram_addr command_p.io.in.bits.channels := channels command_p.io.in.bits.I := I command_p.io.in.bits.J := J command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded io.cmd.bits := command_p.io.out.bits.cmd when (command_p.io.out.bits.cmd.inst.funct === STORE_CMD) { val o = command_p.io.out.bits when (o.is_pool) { val pool_mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) pool_mvout_cmd_rs2 := DontCare pool_mvout_cmd_rs2.num_cols := o.channels pool_mvout_cmd_rs2.local_addr := cast_to_acc_addr(pool_mvout_cmd_rs2.local_addr, o.pool_spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs1 := o.pool_dram_addr io.cmd.bits.rs2 := pool_mvout_cmd_rs2.asUInt } .otherwise { val mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) mvout_cmd_rs2 := DontCare mvout_cmd_rs2.num_rows := o.I.asUInt mvout_cmd_rs2.num_cols := o.J.asUInt mvout_cmd_rs2.local_addr := cast_to_acc_addr(mvout_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B) io.cmd.bits.rs1 := o.dram_addr io.cmd.bits.rs2 := mvout_cmd_rs2.asUInt } } // Sending outputs when (skip) { state := idle }.elsewhen(command_p.io.in.fire) { when (req.no_pool) { val next_och = floorAdd(och, block_size.U, ochs) val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U) val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U) val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U) och := next_och ocol := next_ocol orow := next_orow b := next_b state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U, idle, st) }.elsewhen(state === pre_pool_config) { state := pool }.elsewhen(state === post_pool_config) { state := idle }.otherwise { val next_och = floorAdd(och, block_size.U, ochs) val next_b = floorAdd(b, 1.U, batches, next_och === 0.U) och := next_och b := next_b state := Mux(next_b === 0.U && next_och === 0.U, post_pool_config, pool) } } // Accepting requests when (io.req.fire) { req := io.req.bits state := Mux(io.req.bits.no_pool, st, pre_pool_config) b := 0.U orow := 0.U ocol := 0.U och := 0.U } } class LoopConvState(val block_size: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val coreMaxAddrBits: Int, val max_addr: Int, val max_acc_addr: Int) extends Bundle { val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth) val bias_dram_addr = UInt(coreMaxAddrBits.W) val weights_dram_addr = UInt(coreMaxAddrBits.W) val input_dram_addr = UInt(coreMaxAddrBits.W) val output_dram_addr = UInt(coreMaxAddrBits.W) val no_bias = Bool() val wrot180 = Bool() val no_pool = Bool() val downsample = Bool() val input_dilated = Bool() val activation = UInt(2.W) // TODO magic number val trans_output_1203 = Bool() val trans_weight_1203 = Bool() val trans_weight_0132 = Bool() val trans_input_3120 = Bool() val dw = Bool() val max_pixels_per_row = UInt(small_iterator_bitwidth.W) val a_ex_spad_id = UInt(2.W) val b_ex_spad_id = UInt(2.W) val configured = Bool() val running = Bool() val ld_bias_started = Bool() val ld_input_started = Bool() val ld_weights_started = Bool() val ex_started = Bool() val st_started = Bool() val ld_bias_completed = Bool() val ld_input_completed = Bool() val ld_weights_completed = Bool() val ex_completed = Bool() val st_completed = Bool() def all_completed(dummy: Int=0): Bool = ld_bias_completed && ld_input_completed && ld_weights_completed && ex_completed && st_completed val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) def derived_params(dummy: Int=0): LoopConvDerivedParams = { import outer_bounds.{stride, kernel_dilation} import inner_bounds.{batches, pochs, orows, ocols, krows, kcols, upad, dpad, lpad, rpad, kchs} val result = Wire(new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)) result.ochs := pochs val dilated_krows = krows + (kernel_dilation - 1.U)*(krows - 1.U) val dilated_kcols = kcols + (kernel_dilation - 1.U)*(kcols - 1.U) val irows_without_dilation = orows * stride +& dilated_krows -& 1.U val icols_without_dilation = ocols * stride +& dilated_kcols -& 1.U val irows_unpadded_without_dilation = irows_without_dilation -& upad -& dpad val icols_unpadded_without_dilation = icols_without_dilation -& lpad -& rpad def undilated(x: UInt): UInt = (x +& input_dilated) >> input_dilated val irows_unpadded = undilated(irows_unpadded_without_dilation) val icols_unpadded = undilated(icols_unpadded_without_dilation) result.irows := Mux(input_dilated, irows_unpadded +& undilated(upad) +& undilated(dpad), irows_without_dilation) result.icols := Mux(input_dilated, icols_unpadded +& undilated(lpad) +& undilated(rpad), icols_without_dilation) result.irows_unpadded := irows_unpadded result.icols_unpadded := icols_unpadded result.ichs := kchs result.out_channels_per_bank := result.ochs / block_size.U(result.ochs.getWidth.W) +& (result.ochs % block_size.U =/= 0.U) result.in_channels_per_bank := result.ichs / block_size.U(result.ochs.getWidth.W) +& (result.ichs % block_size.U =/= 0.U) result.bias_spad_stride := batches * orows * ocols result.input_spad_stride := Mux(trans_input_3120, result.ichs * (result.irows >> downsample) * (result.icols >> downsample), batches * (result.irows >> downsample) * (result.icols >> downsample)) result.weight_spad_stride := Mux(trans_weight_0132, krows * kcols * pochs, krows * kcols * kchs) // result.ex_overwrite := bias_dram_addr =/= 0.U && no_bias result } def reset(): Unit = { configured := false.B running := false.B ld_bias_started := false.B ld_input_started := false.B ld_weights_started := false.B ex_started := false.B st_started := false.B ld_bias_completed := false.B ld_input_completed := false.B ld_weights_completed := false.B ex_completed := false.B st_completed := false.B } } class LoopConv (block_size: Int, coreMaxAddrBits: Int, reservation_station_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, has_training_convs: Boolean, has_max_pool: Boolean, has_first_layer_optimizations: Boolean, has_dw_convs: Boolean) (implicit p: Parameters) extends Module { val large_iterator_bitwidth = 16 val small_iterator_bitwidth = 16 // 8 val tiny_iterator_bitwidth = 16 // 4 val max_block_len = (dma_max_bytes / (block_size * (input_w / 8))) max 1 val max_block_len_acc = (dma_max_bytes / (block_size * (acc_w / 8))) max 1 val io = IO(new Bundle { val in = Flipped(Decoupled(new GemminiCmd(reservation_station_size))) val out = Decoupled(new GemminiCmd(reservation_station_size)) val ld_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val st_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val ex_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val busy = Output(Bool()) }) // Create states val concurrent_loops = 2 val loops = Reg(Vec(concurrent_loops, new LoopConvState(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, coreMaxAddrBits, max_addr, max_acc_addr))) val head_loop_id = RegInit(0.U(log2Up(concurrent_loops).W)) val tail_loop_id = (~head_loop_id).asUInt // This is the loop that we always try to configure if available val head_loop = loops(head_loop_id) val tail_loop = loops(tail_loop_id) val loop_configured = loops.map(_.configured).reduce(_ || _) val loop_being_configured_id = Mux(head_loop.configured, tail_loop_id, head_loop_id) val loop_being_configured = loops(loop_being_configured_id) // Create inner modules val latency = 2 val ld_bias = Module(new LoopConvLdBias(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, acc_w, max_block_len_acc, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ld_input = Module(new LoopConvLdInput(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ld_weights = Module(new LoopConvLdWeight(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t)) val ex = Module(new LoopConvExecute(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops, latency, config_ex_rs1_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t)) val st = Module(new LoopConvSt(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, input_w, concurrent_loops, latency, config_mvout_rs2_t, mvout_rs2_t)) // Create command queue val cmd = Queue(io.in) io.busy := cmd.valid || loop_configured // Create arbiter val arb = Module(new Arbiter(new RoCCCommand, 5)) arb.io.in(0) <> st.io.cmd arb.io.in(1) <> ex.io.cmd arb.io.in(2) <> ld_bias.io.cmd arb.io.in(3) <> ld_weights.io.cmd arb.io.in(4) <> ld_input.io.cmd val unrolled_cmd = arb.io.out // Create reservation station utilization counters val ld_utilization = RegInit(0.U(log2Up(max_lds+1).W)) val st_utilization = RegInit(0.U(log2Up(max_sts+1).W)) val ex_utilization = RegInit(0.U(log2Up(max_exs+1).W)) ld_utilization := ld_utilization +& (ld_bias.io.cmd.fire || ld_weights.io.cmd.fire || ld_input.io.cmd.fire) -& io.ld_completed st_utilization := st_utilization +& st.io.cmd.fire -& io.st_completed ex_utilization := ex_utilization +& ex.io.cmd.fire -& io.ex_completed assert(ld_utilization >= io.ld_completed, "ld utilization underflow") assert(st_utilization >= io.st_completed, "st utilization underflow") assert(ex_utilization >= io.ex_completed, "ex utilization underflow") // Wire up unrolled command output val is_loop_run_cmd = cmd.bits.cmd.inst.funct === LOOP_CONV_WS val is_loop_config_cmd = cmd.bits.cmd.inst.funct >= LOOP_CONV_WS_CONFIG_1 && cmd.bits.cmd.inst.funct <= LOOP_CONV_WS_CONFIG_6 val is_loop_cmd = is_loop_run_cmd || is_loop_config_cmd io.out.bits.cmd := Mux(loop_configured, unrolled_cmd.bits, cmd.bits.cmd) io.out.bits.cmd.status := cmd.bits.cmd.status // TODO This is not guaranteed to be the correct fix! We must fix this io.out.bits.rob_id := DontCare io.out.bits.from_matmul_fsm := Mux(loop_configured, false.B, cmd.bits.from_matmul_fsm) io.out.bits.from_conv_fsm := Mux(loop_configured, true.B, cmd.bits.from_conv_fsm) io.out.valid := Mux(loop_configured, unrolled_cmd.valid, cmd.valid && !is_loop_config_cmd && !is_loop_run_cmd) cmd.ready := Mux(is_loop_cmd, !loop_being_configured.configured, !loop_configured && io.out.ready) arb.io.out.ready := io.out.ready // Wire up waiting-for-loads signals val ex_is_waiting_for_loads = loops(ex.io.loop_id).ex_started && !loops(ex.io.loop_id).ex_completed && !(loops(ex.io.loop_id).ld_input_completed && loops(ex.io.loop_id).ld_weights_completed && loops(ex.io.loop_id).ld_bias_completed) ld_bias.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_bias.io.loop_id =/= ex.io.loop_id ld_weights.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_weights.io.loop_id =/= ex.io.loop_id ld_input.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_input.io.loop_id =/= ex.io.loop_id // Wire up overloaded signals ld_bias.io.rob_overloaded := ld_utilization >= max_lds.U ld_input.io.rob_overloaded := ld_utilization >= max_lds.U ld_weights.io.rob_overloaded := ld_utilization >= max_lds.U ex.io.rob_overloaded := ex_utilization >= max_exs.U st.io.rob_overloaded := st_utilization >= max_sts.U // Wire up iterator inputs ex.io.lda_completed := (ld_input.io.loop_id =/= ex.io.loop_id) || ld_input.io.idle ex.io.ldb_completed := (ld_weights.io.loop_id =/= ex.io.loop_id) || ld_weights.io.idle ex.io.ldd_completed := (ld_bias.io.loop_id =/= ex.io.loop_id) || ld_bias.io.idle st.io.ex_completed := (ex.io.loop_id =/= st.io.loop_id) || ex.io.idle // Create config registers when(cmd.valid && is_loop_cmd && !loop_being_configured.configured) { switch (cmd.bits.cmd.inst.funct) { is (LOOP_CONV_WS_CONFIG_1) { loop_being_configured.outer_bounds.out_channels := cmd.bits.cmd.rs1(63, 48) loop_being_configured.outer_bounds.in_channels := cmd.bits.cmd.rs1(47, 32) loop_being_configured.outer_bounds.in_row_dim := cmd.bits.cmd.rs1(31, 16) loop_being_configured.outer_bounds.batch_size := cmd.bits.cmd.rs1(15, 0) loop_being_configured.outer_bounds.padding := cmd.bits.cmd.rs2(63, 56) loop_being_configured.outer_bounds.stride := cmd.bits.cmd.rs2(55, 48) loop_being_configured.outer_bounds.out_col_dim := cmd.bits.cmd.rs2(47, 32) loop_being_configured.outer_bounds.pool_out_row_dim := cmd.bits.cmd.rs2(31, 16) loop_being_configured.outer_bounds.out_row_dim := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_2) { loop_being_configured.outer_bounds.kernel_dim := cmd.bits.cmd.rs1(63, 48) loop_being_configured.outer_bounds.pool_out_col_dim := cmd.bits.cmd.rs1(47, 32) loop_being_configured.outer_bounds.pool_size := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(31, 16)) loop_being_configured.outer_bounds.pool_stride := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(15, 8)) loop_being_configured.outer_bounds.pool_padding := (if (!has_max_pool) 0.U else cmd.bits.cmd.rs1(7, 0)) loop_being_configured.inner_bounds.batches := cmd.bits.cmd.rs2(63, 48) loop_being_configured.inner_bounds.porows := cmd.bits.cmd.rs2(47, 32) loop_being_configured.inner_bounds.pocols := cmd.bits.cmd.rs2(31, 16) loop_being_configured.inner_bounds.pochs := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_3) { loop_being_configured.inner_bounds.krows := cmd.bits.cmd.rs1(63, 48) loop_being_configured.inner_bounds.kcols := cmd.bits.cmd.rs1(47, 32) loop_being_configured.inner_bounds.kchs := cmd.bits.cmd.rs1(31, 16) loop_being_configured.inner_bounds.lpad := cmd.bits.cmd.rs1(15, 0) loop_being_configured.inner_bounds.rpad := cmd.bits.cmd.rs2(63, 48) loop_being_configured.inner_bounds.upad := cmd.bits.cmd.rs2(47, 32) loop_being_configured.inner_bounds.dpad := cmd.bits.cmd.rs2(31, 24) loop_being_configured.inner_bounds.plpad := cmd.bits.cmd.rs2(23, 16) loop_being_configured.outer_bounds.in_col_dim := cmd.bits.cmd.rs2(15, 0) } is (LOOP_CONV_WS_CONFIG_4) { loop_being_configured.inner_bounds.orows := cmd.bits.cmd.rs1(63, 48) loop_being_configured.inner_bounds.prad := cmd.bits.cmd.rs1(47, 32) loop_being_configured.inner_bounds.pupad := cmd.bits.cmd.rs1(31, 21) loop_being_configured.inner_bounds.pdpad := cmd.bits.cmd.rs1(20, 10) loop_being_configured.outer_bounds.kernel_dilation := cmd.bits.cmd.rs1(9, 0) loop_being_configured.inner_bounds.ocols := cmd.bits.cmd.rs2(15, 0) loop_being_configured.outer_bounds.in_stride := cmd.bits.cmd.rs2(63, 48) loop_being_configured.outer_bounds.weight_stride := cmd.bits.cmd.rs2(47, 32) loop_being_configured.outer_bounds.out_stride := cmd.bits.cmd.rs2(31, 16) } is (LOOP_CONV_WS_CONFIG_5) { loop_being_configured.weights_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.output_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_CONV_WS_CONFIG_6) { loop_being_configured.bias_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.input_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_CONV_WS) { loop_being_configured.no_bias := cmd.bits.cmd.rs1(0) // TODO we added a default value for max_pixels_per_row just to maintain backwards compatibility. we should deprecate and remove it later val config_max_pixels_per_row = cmd.bits.cmd.rs1(15, 8) loop_being_configured.max_pixels_per_row := Mux( !has_first_layer_optimizations.B || config_max_pixels_per_row === 0.U, 1.U, config_max_pixels_per_row) loop_being_configured.a_ex_spad_id := cmd.bits.cmd.rs1(19, 18) loop_being_configured.b_ex_spad_id := cmd.bits.cmd.rs1(17, 16) loop_being_configured.wrot180 := has_training_convs.B && cmd.bits.cmd.rs1(1) loop_being_configured.input_dilated := has_training_convs.B && cmd.bits.cmd.rs2(2) loop_being_configured.trans_output_1203 := has_training_convs.B && cmd.bits.cmd.rs1(2) loop_being_configured.trans_weight_1203 := has_training_convs.B && cmd.bits.cmd.rs1(3) loop_being_configured.trans_weight_0132 := has_training_convs.B && cmd.bits.cmd.rs1(4) loop_being_configured.trans_input_3120 := has_training_convs.B && cmd.bits.cmd.rs1(5) loop_being_configured.dw := has_dw_convs.B && cmd.bits.cmd.rs1(6) loop_being_configured.no_pool := !has_max_pool.B || cmd.bits.cmd.rs2(0) loop_being_configured.activation := cmd.bits.cmd.rs2(4,3) loop_being_configured.downsample := cmd.bits.cmd.rs2(1) loop_being_configured.configured := true.B // assert(!loop_being_configured.input_dilated || loop_being_configured.outer_bounds.stride === 1.U) // assert(!loop_being_configured.downsample || (loop_being_configured.outer_bounds.kernel_dim === 1.U && loop_being_configured.outer_bounds.stride === 2.U)) // TODO add the rest of the conditions that must be true for "downsample" to be enabled } } } // Wire up request signals val ld_bias_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val ex_c_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val st_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val loop_requesting_ld_bias_id = Mux(head_loop.ld_bias_started, tail_loop_id, head_loop_id) val loop_requesting_ld_bias = loops(loop_requesting_ld_bias_id) ld_bias.io.req.bits.outer_bounds := loop_requesting_ld_bias.outer_bounds ld_bias.io.req.bits.inner_bounds := loop_requesting_ld_bias.inner_bounds ld_bias.io.req.bits.derived_params := loop_requesting_ld_bias.derived_params() ld_bias.io.req.bits.addr_start := ld_bias_addr_start ld_bias.io.req.bits.dram_addr := loop_requesting_ld_bias.bias_dram_addr ld_bias.io.req.bits.no_bias := loop_requesting_ld_bias.no_bias ld_bias.io.req.bits.loop_id := loop_requesting_ld_bias_id ld_bias.io.req.valid := !loop_requesting_ld_bias.ld_bias_started && loop_requesting_ld_bias.configured when (ld_bias.io.req.fire) { loop_requesting_ld_bias.running := true.B loop_requesting_ld_bias.ld_bias_started := true.B // when (loop_requesting_ld_bias.bias_dram_addr =/= 0.U) { when (loop_requesting_ld_bias.output_dram_addr =/= 0.U) { ld_bias_addr_start := floorAdd(ld_bias_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_ld_input_id = Mux(head_loop.ld_input_started, tail_loop_id, head_loop_id) val loop_requesting_ld_input = loops(loop_requesting_ld_input_id) ld_input.io.req.bits.outer_bounds := loop_requesting_ld_input.outer_bounds ld_input.io.req.bits.inner_bounds := loop_requesting_ld_input.inner_bounds ld_input.io.req.bits.derived_params := loop_requesting_ld_input.derived_params() ld_input.io.req.bits.addr_start := Mux(loop_requesting_ld_input.a_ex_spad_id === 0.U, loop_requesting_ld_input.a_addr_start, (loop_requesting_ld_input.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ld_input.io.req.bits.dram_addr := loop_requesting_ld_input.input_dram_addr ld_input.io.req.bits.downsample := loop_requesting_ld_input.downsample ld_input.io.req.bits.max_pixels_per_row := loop_requesting_ld_input.max_pixels_per_row ld_input.io.req.bits.input_dilated := loop_requesting_ld_input.input_dilated ld_input.io.req.bits.trans_input_3120 := loop_requesting_ld_input.trans_input_3120 ld_input.io.req.bits.loop_id := loop_requesting_ld_input_id ld_input.io.req.valid := !loop_requesting_ld_input.ld_input_started && loop_requesting_ld_input.configured when (ld_input.io.req.fire) { loop_requesting_ld_input.running := true.B loop_requesting_ld_input.ld_input_started := true.B } val loop_requesting_ld_weights_id = Mux(head_loop.ld_weights_started, tail_loop_id, head_loop_id) val loop_requesting_ld_weights = loops(loop_requesting_ld_weights_id) ld_weights.io.req.bits.outer_bounds := loop_requesting_ld_weights.outer_bounds ld_weights.io.req.bits.inner_bounds := loop_requesting_ld_weights.inner_bounds ld_weights.io.req.bits.derived_params := loop_requesting_ld_weights.derived_params() ld_weights.io.req.bits.addr_end := Mux(loop_requesting_ld_weights.b_ex_spad_id === 0.U, loop_requesting_ld_weights.b_addr_end, (loop_requesting_ld_weights.b_ex_spad_id) * (max_addr / concurrent_loops).U) ld_weights.io.req.bits.dram_addr := loop_requesting_ld_weights.weights_dram_addr ld_weights.io.req.bits.trans_weight_1203 := loop_requesting_ld_weights.trans_weight_1203 ld_weights.io.req.bits.trans_weight_0132 := loop_requesting_ld_weights.trans_weight_0132 ld_weights.io.req.bits.dw := loop_requesting_ld_weights.dw ld_weights.io.req.bits.loop_id := loop_requesting_ld_weights_id ld_weights.io.req.valid := !loop_requesting_ld_weights.ld_weights_started && loop_requesting_ld_weights.configured when (ld_weights.io.req.fire) { loop_requesting_ld_weights.running := true.B loop_requesting_ld_weights.ld_weights_started := true.B } val loop_requesting_ex_id = Mux(head_loop.ex_started, tail_loop_id, head_loop_id) val loop_requesting_ex = loops(loop_requesting_ex_id) ex.io.req.bits.outer_bounds := loop_requesting_ex.outer_bounds ex.io.req.bits.inner_bounds := loop_requesting_ex.inner_bounds ex.io.req.bits.derived_params := loop_requesting_ex.derived_params() ex.io.req.bits.a_addr_start := Mux(loop_requesting_ex.a_ex_spad_id === 0.U, loop_requesting_ex.a_addr_start, (loop_requesting_ex.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ex.io.req.bits.b_addr_end := Mux(loop_requesting_ex.b_ex_spad_id === 0.U, loop_requesting_ex.b_addr_end, (loop_requesting_ex.b_ex_spad_id) * (max_addr / concurrent_loops).U) ex.io.req.bits.c_addr_start := ex_c_addr_start ex.io.req.bits.wrot180 := loop_requesting_ex.wrot180 ex.io.req.bits.downsample := loop_requesting_ex.downsample ex.io.req.bits.max_pixels_per_row := loop_requesting_ex.max_pixels_per_row ex.io.req.bits.input_dilated := loop_requesting_ex.input_dilated ex.io.req.bits.trans_weight_0132 := loop_requesting_ex.trans_weight_0132 ex.io.req.bits.trans_input_3120 := loop_requesting_ex.trans_input_3120 ex.io.req.bits.loop_id := loop_requesting_ex_id ex.io.req.valid := !loop_requesting_ex.ex_started && loop_requesting_ex.ld_bias_started && loop_requesting_ex.ld_input_started && loop_requesting_ex.ld_weights_started && loop_requesting_ex.configured when (ex.io.req.fire) { loop_requesting_ex.running := true.B loop_requesting_ex.ex_started := true.B when (loop_requesting_ex.output_dram_addr =/= 0.U) { ex_c_addr_start := floorAdd(ex_c_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_st_id = Mux(head_loop.st_started, tail_loop_id, head_loop_id) val loop_requesting_st = loops(loop_requesting_st_id) st.io.req.bits.outer_bounds := loop_requesting_st.outer_bounds st.io.req.bits.inner_bounds := loop_requesting_st.inner_bounds st.io.req.bits.derived_params := loop_requesting_st.derived_params() st.io.req.bits.addr_start := st_addr_start st.io.req.bits.dram_addr := loop_requesting_st.output_dram_addr st.io.req.bits.no_pool := loop_requesting_st.no_pool st.io.req.bits.activation := loop_requesting_st.activation st.io.req.bits.trans_output_1203 := loop_requesting_st.trans_output_1203 st.io.req.bits.loop_id := loop_requesting_st_id st.io.req.valid := !loop_requesting_st.st_started && loop_requesting_st.ex_started && loop_requesting_st.configured when (st.io.req.fire) { loop_requesting_st.running := true.B loop_requesting_st.st_started := true.B when (loop_requesting_st.output_dram_addr =/= 0.U) { st_addr_start := floorAdd(st_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } // Handle completed signals when (ld_bias.io.idle && loops(ld_bias.io.loop_id).running && loops(ld_bias.io.loop_id).ld_bias_started) { loops(ld_bias.io.loop_id).ld_bias_completed := true.B } when (ld_input.io.idle && loops(ld_input.io.loop_id).running && loops(ld_input.io.loop_id).ld_input_started) { loops(ld_input.io.loop_id).ld_input_completed := true.B } when (ld_weights.io.idle && loops(ld_weights.io.loop_id).running && loops(ld_weights.io.loop_id).ld_weights_started) { loops(ld_weights.io.loop_id).ld_weights_completed := true.B } when (ex.io.idle && loops(ex.io.loop_id).running && loops(ex.io.loop_id).ex_started) { loops(ex.io.loop_id).ex_completed := true.B } when (st.io.idle && loops(st.io.loop_id).running && loops(st.io.loop_id).st_started) { loops(st.io.loop_id).st_completed := true.B } when (head_loop.running && head_loop.all_completed()) { head_loop.reset() head_loop_id := ~head_loop_id } // Resets when (reset.asBool) { loops.zipWithIndex.foreach { case (l, i) => l.reset() l.a_addr_start := (i * (max_addr / concurrent_loops)).U l.b_addr_end := ((i+1) * (max_addr / concurrent_loops)).U } } } object LoopConv { def apply(in: DecoupledIO[GemminiCmd], ld_completed: UInt, st_completed: UInt, ex_completed: UInt, block_size: Int, coreMaxAddrBits: Int, rob_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, has_training_convs: Boolean, has_max_pool: Boolean, has_first_layer_optimizations: Boolean, has_dw_convs: Boolean) (implicit p: Parameters): (DecoupledIO[GemminiCmd], Bool) = { val mod = Module(new LoopConv(block_size, coreMaxAddrBits, rob_size, max_lds, max_exs, max_sts, max_addr, max_acc_addr, input_w, acc_w, dma_max_bytes, config_mvin_rs1_t, mvin_rs2_t, config_mvout_rs2_t, mvout_rs2_t, config_ex_rs1_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t, has_training_convs, has_max_pool, has_first_layer_optimizations, has_dw_convs)) mod.io.in <> in mod.io.ld_completed := ld_completed mod.io.st_completed := st_completed mod.io.ex_completed := ex_completed (mod.io.out, mod.io.busy) } def castDramOffset(dram_offset: UInt): UInt = { // Cast dram offsets to 32 bits max dram_offset & "hFFFFFFFF".U } } File LoopMatmul.scala: package gemmini import chisel3._ import chisel3.util._ import chisel3.experimental._ import freechips.rocketchip.tile.RoCCCommand import org.chipsalliance.cde.config.Parameters import GemminiISA._ import LocalAddr._ import Util._ // LdA class LoopMatmulLdAReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_addr: Int, val concurrent_loops: Int) extends Bundle { val max_i = UInt(iterator_bitwidth.W) val max_k = UInt(iterator_bitwidth.W) val pad_i = UInt(log2Up(block_size).W) val pad_k = UInt(log2Up(block_size).W) val dram_addr = UInt(coreMaxAddrBits.W) val dram_stride = UInt(coreMaxAddrBits.W) val transpose = Bool() val addr_start = UInt(log2Up(max_addr).W) val loop_id = UInt(log2Up(concurrent_loops).W) val is_resadd = Bool() } class LoopMatmulLdA(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, mvin_rs2_t: MvinRs2) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopMatmulLdAReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val i = Output(UInt(iterator_bitwidth.W)) val k = Output(UInt(iterator_bitwidth.W)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopMatmulLdAReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, concurrent_loops)) val i = Reg(UInt(iterator_bitwidth.W)) val k = Reg(UInt(iterator_bitwidth.W)) val row_iterator = Mux(req.transpose, k, i) val col_iterator = Mux(req.transpose, i, k) val max_row_iterator = Mux(req.transpose, req.max_k, req.max_i) val max_col_iterator = Mux(req.transpose, req.max_i, req.max_k) val row_pad = Mux(req.transpose, req.pad_k, req.pad_i) val col_pad = Mux(req.transpose, req.pad_i, req.pad_k) val max_col_dim = Mux(req.transpose, req.max_i, req.max_k) val max_blocks = Mux(max_col_dim <= max_block_len.U, max_col_dim, max_block_len.U) val sp_addr_start = req.addr_start val dram_offset = (row_iterator * req.dram_stride + col_iterator) * block_size.U * (input_w/8).U val dram_addr = req.dram_addr + LoopMatmul.castDramOffset(dram_offset) val sp_addr = sp_addr_start + (row_iterator * max_col_iterator + col_iterator) * block_size.U val blocks = Mux(col_iterator + max_blocks <= max_col_iterator, max_blocks, max_col_iterator-col_iterator) val cols = (blocks * block_size.U) - Mux(col_iterator + blocks >= max_col_iterator, col_pad, 0.U) val rows = block_size.U - Mux(row_iterator === max_row_iterator-1.U, row_pad, 0.U) val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD_CMD mvin_cmd.rs1 := dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := rows.asUInt mvin_cmd_rs2.num_cols := cols.asUInt mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, sp_addr) mvin_cmd.rs2 := mvin_cmd_rs2.asUInt when(req.is_resadd){ mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, sp_addr, accumulate = false.B, read_full = false.B) } io.req.ready := state === idle io.i := i io.k := k io.idle := state === idle io.cmd.valid := state =/= idle && !io.rob_overloaded && req.dram_addr =/= 0.U io.cmd.bits := mvin_cmd io.loop_id := req.loop_id when(req.dram_addr === 0.U){ state := idle }.elsewhen(io.cmd.fire) { // The order here is k, j, i val i_blocks = Mux(req.transpose, max_blocks, 1.U) val k_blocks = Mux(req.transpose, 1.U, max_blocks) val next_i = floorAdd(i, i_blocks, req.max_i) val next_k = floorAdd(k, k_blocks, req.max_k, next_i === 0.U) i := next_i k := next_k when (next_i === 0.U && next_k === 0.U) { state := idle } } when (io.req.fire) { req := io.req.bits state := ld i := 0.U k := 0.U } } // LdB class LoopMatmulLdBReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_addr: Int, val concurrent_loops: Int) extends Bundle { val max_k = UInt(iterator_bitwidth.W) val max_j = UInt(iterator_bitwidth.W) val pad_k = UInt(log2Up(block_size).W) val pad_j = UInt(log2Up(block_size).W) val dram_addr = UInt(coreMaxAddrBits.W) val dram_stride = UInt(coreMaxAddrBits.W) val transpose = Bool() val addr_end = UInt(log2Up(max_addr+1).W) val loop_id = UInt(log2Up(concurrent_loops).W) val is_resadd = Bool() } class LoopMatmulLdB(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int, concurrent_loops: Int, mvin_rs2_t: MvinRs2) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopMatmulLdBReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val k = Output(UInt(iterator_bitwidth.W)) val j = Output(UInt(iterator_bitwidth.W)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopMatmulLdBReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, concurrent_loops)) val k = Reg(UInt(iterator_bitwidth.W)) val j = Reg(UInt(iterator_bitwidth.W)) val row_iterator = Mux(req.transpose, j, k) val col_iterator = Mux(req.transpose, k, j) val max_row_iterator = Mux(req.transpose, req.max_j, req.max_k) val max_col_iterator = Mux(req.transpose, req.max_k, req.max_j) val row_pad = Mux(req.transpose, req.pad_j, req.pad_k) val col_pad = Mux(req.transpose, req.pad_k, req.pad_j) val max_col_dim = Mux(req.transpose, req.max_k, req.max_j) val max_blocks = Mux(max_col_dim <= max_block_len.U, max_col_dim, max_block_len.U) val sp_addr_start = Mux(req.is_resadd, req.addr_end, req.addr_end - req.max_k * req.max_j * block_size.U) val dram_offset = (row_iterator * req.dram_stride + col_iterator) * block_size.U * (input_w/8).U val dram_addr = req.dram_addr + LoopMatmul.castDramOffset(dram_offset) val sp_addr = sp_addr_start + (row_iterator * max_col_iterator + col_iterator) * block_size.U val blocks = Mux(col_iterator + max_blocks <= max_col_iterator, max_blocks, max_col_iterator-col_iterator) val cols = (blocks * block_size.U) - Mux(col_iterator + blocks >= max_col_iterator, col_pad, 0.U) val rows = block_size.U - Mux(max_row_iterator === max_row_iterator-1.U, row_pad, 0.U) val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD2_CMD mvin_cmd.rs1 := dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := rows.asUInt mvin_cmd_rs2.num_cols := cols.asUInt mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, sp_addr) mvin_cmd.rs2 := mvin_cmd_rs2.asUInt when (req.is_resadd){ mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, sp_addr, accumulate = true.B, read_full = false.B) } io.req.ready := state === idle io.k := k io.j := j io.idle := state === idle io.cmd.valid := state =/= idle && !io.rob_overloaded && req.dram_addr =/= 0.U io.cmd.bits := mvin_cmd io.loop_id := req.loop_id when(req.dram_addr === 0.U){ state := idle }.elsewhen(io.cmd.fire) { // The order here is k, j, i val j_blocks = Mux(req.transpose, 1.U, max_blocks) val k_blocks = Mux(req.transpose, max_blocks, 1.U) val next_j = floorAdd(j, j_blocks, req.max_j) val next_k = floorAdd(k, k_blocks, req.max_k, next_j === 0.U) j := next_j k := next_k when (next_j === 0.U && next_k === 0.U) { state := idle } } when (io.req.fire) { req := io.req.bits state := ld j := 0.U k := 0.U } } // LdD class LoopMatmulLdDReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val max_j = UInt(iterator_bitwidth.W) val max_i = UInt(iterator_bitwidth.W) val pad_j = UInt(log2Up(block_size).W) val pad_i = UInt(log2Up(block_size).W) val dram_addr = UInt(coreMaxAddrBits.W) val dram_stride = UInt(coreMaxAddrBits.W) val low_d = Bool() val addr_start = UInt(log2Up(max_acc_addr).W) val loop_id = UInt(log2Up(concurrent_loops).W) } class LoopMatmulLdD(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, max_block_len: Int, max_block_len_acc: Int, concurrent_loops: Int, mvin_rs2_t: MvinRs2) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopMatmulLdDReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, ld = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopMatmulLdDReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, concurrent_loops)) val max_blocks = Mux(req.low_d, Mux(req.max_j <= max_block_len.U, req.max_j, max_block_len.U), Mux(req.max_j <= max_block_len_acc.U, req.max_j, max_block_len_acc.U)) val j = Reg(UInt(iterator_bitwidth.W)) val i = Reg(UInt(iterator_bitwidth.W)) val acc_addr_start = req.addr_start val dram_offset = Mux(req.low_d, (i * req.dram_stride + j) * block_size.U * (input_w/8).U, (i * req.dram_stride + j) * block_size.U * (acc_w/8).U) val dram_addr = req.dram_addr + LoopMatmul.castDramOffset(dram_offset) val sp_addr = acc_addr_start + (i * req.max_j + j) * block_size.U val blocks = Mux(j + max_blocks <= req.max_j, max_blocks, req.max_j-j) val cols = (blocks * block_size.U) - Mux(j + blocks >= req.max_j, req.pad_j, 0.U) val rows = block_size.U - Mux(i === req.max_i-1.U, req.pad_i, 0.U) val mvin_cmd = Wire(new RoCCCommand) mvin_cmd := DontCare mvin_cmd.inst.funct := LOAD3_CMD mvin_cmd.rs1 := dram_addr val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType) mvin_cmd_rs2 := DontCare mvin_cmd_rs2.num_rows := rows.asUInt mvin_cmd_rs2.num_cols := cols.asUInt mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, sp_addr, accumulate = false.B, read_full = false.B) mvin_cmd.rs2 := mvin_cmd_rs2.asUInt io.req.ready := state === idle io.idle := state === idle // The order here is k, j, i io.cmd.valid := state =/= idle && !io.rob_overloaded && req.dram_addr =/= 0.U io.cmd.bits := mvin_cmd io.loop_id := req.loop_id when (req.dram_addr === 0.U) { state := idle }.elsewhen (io.cmd.fire) { // The order here is k, j, i val next_i = floorAdd(i, 1.U, req.max_i) val next_j = floorAdd(j, max_blocks, req.max_j, next_i === 0.U) i := next_i j := next_j when (next_i === 0.U && next_j === 0.U) { state := idle } } when (io.req.fire) { req := io.req.bits state := ld j := 0.U i := 0.U } } // Compute class LoopMatmulExecuteReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_addr: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val max_j = UInt(iterator_bitwidth.W) val max_k = UInt(iterator_bitwidth.W) val max_i = UInt(iterator_bitwidth.W) val pad_j = UInt(log2Up(block_size).W) val pad_k = UInt(log2Up(block_size).W) val pad_i = UInt(log2Up(block_size).W) val a_tranpose = Bool() val b_tranpose = Bool() val accumulate = Bool() val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) val c_addr_start = UInt(log2Up(max_acc_addr).W) val loop_id = UInt(log2Up(concurrent_loops).W) val skip = Bool() } class LoopMatmulExecute(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_addr: Int, max_acc_addr: Int, concurrent_loops: Int, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopMatmulExecuteReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val k = Output(UInt(iterator_bitwidth.W)) val j = Output(UInt(iterator_bitwidth.W)) val i = Output(UInt(iterator_bitwidth.W)) val ld_ka = Input(UInt(iterator_bitwidth.W)) val ld_kb = Input(UInt(iterator_bitwidth.W)) val ld_j = Input(UInt(iterator_bitwidth.W)) val ld_i = Input(UInt(iterator_bitwidth.W)) val lda_completed = Input(Bool()) val ldb_completed = Input(Bool()) val ldd_completed = Input(Bool()) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, pre, comp = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopMatmulExecuteReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops)) val c_addr_start = /*(BigInt(1) << 31).U |*/ req.c_addr_start val b_addr_start = req.b_addr_end - req.max_k * req.max_j * block_size.U val k = Reg(UInt(iterator_bitwidth.W)) val j = Reg(UInt(iterator_bitwidth.W)) val i = Reg(UInt(iterator_bitwidth.W)) val a_row = Mux(req.a_tranpose, k, i) val a_col = Mux(req.a_tranpose, i, k) val b_row = Mux(req.b_tranpose, j, k) val b_col = Mux(req.b_tranpose, k, j) val a_max_col = Mux(req.a_tranpose, req.max_i, req.max_k) val b_max_col = Mux(req.b_tranpose, req.max_k, req.max_j) val a_addr = req.a_addr_start + (a_row * a_max_col + a_col) * block_size.U val b_addr = b_addr_start + (b_row * b_max_col + b_col) * block_size.U val c_addr = c_addr_start + (i * req.max_j + j) * block_size.U val a_cols = block_size.U - Mux(k === req.max_k - 1.U, req.pad_k, 0.U) val a_rows = block_size.U - Mux(i === req.max_i - 1.U, req.pad_i, 0.U) val b_cols = block_size.U - Mux(j === req.max_j - 1.U, req.pad_j, 0.U) val b_rows = block_size.U - Mux(k === req.max_k - 1.U, req.pad_k, 0.U) val c_cols = block_size.U - Mux(j === req.max_j - 1.U, req.pad_j, 0.U) val c_rows = block_size.U - Mux(i === req.max_i - 1.U, req.pad_i, 0.U) val pre_cmd = Wire(new RoCCCommand) pre_cmd := DontCare pre_cmd.inst.funct := PRELOAD_CMD val pre_cmd_rs1 = Wire(preload_rs1_t.cloneType) pre_cmd_rs1 := DontCare pre_cmd_rs1.num_rows := b_rows.asUInt pre_cmd_rs1.num_cols := b_cols.asUInt pre_cmd_rs1.local_addr := Mux(i === 0.U, cast_to_sp_addr(pre_cmd_rs1.local_addr, b_addr), garbage_addr(pre_cmd_rs1.local_addr)) val pre_cmd_rs2 = Wire(preload_rs2_t.cloneType) pre_cmd_rs2 := DontCare pre_cmd_rs2.num_rows := c_rows.asUInt pre_cmd_rs2.num_cols := c_cols.asUInt pre_cmd_rs2.local_addr := cast_to_acc_addr(pre_cmd_rs2.local_addr, c_addr, accumulate = req.accumulate || k =/= 0.U, read_full = false.B) pre_cmd.rs1 := pre_cmd_rs1.asUInt pre_cmd.rs2 := pre_cmd_rs2.asUInt val comp_cmd = Wire(new RoCCCommand()) comp_cmd := DontCare comp_cmd.inst.funct := Mux(i === 0.U, COMPUTE_AND_FLIP_CMD, COMPUTE_AND_STAY_CMD) val comp_cmd_rs1 = Wire(compute_rs1_t.cloneType) comp_cmd_rs1 := DontCare comp_cmd_rs1.num_rows := a_rows.asUInt comp_cmd_rs1.num_cols := a_cols.asUInt comp_cmd_rs1.local_addr := cast_to_sp_addr(comp_cmd_rs1.local_addr, a_addr) val comp_cmd_rs2 = Wire(compute_rs2_t.cloneType) comp_cmd_rs2 := DontCare comp_cmd_rs2.num_rows := block_size.U comp_cmd_rs2.num_cols := block_size.U comp_cmd_rs2.local_addr := garbage_addr(comp_cmd_rs2.local_addr) comp_cmd.rs1 := comp_cmd_rs1.asUInt comp_cmd.rs2 := comp_cmd_rs2.asUInt io.req.ready := state === idle io.k := k io.j := j io.i := i io.idle := state === idle // The order here is k, j, i val lda_ahead = io.lda_completed || io.ld_ka > k || (io.ld_ka === k && io.ld_i > i) val ldb_ahead = io.ldb_completed || io.ld_kb > k || (io.ld_ka === k && io.ld_j > j) val ldd_ahead = io.ldd_completed val ld_ahead = lda_ahead && ldb_ahead && ldd_ahead io.cmd.valid := state =/= idle && !io.rob_overloaded && ld_ahead && !req.skip io.cmd.bits := Mux(state === pre, pre_cmd, comp_cmd) io.loop_id := req.loop_id when(req.skip) { state := idle }.elsewhen (io.cmd.fire) { when (state === pre) { state := comp }.otherwise { val next_i = floorAdd(i, 1.U, req.max_i) val next_j = floorAdd(j, 1.U, req.max_j, next_i === 0.U) val next_k = floorAdd(k, 1.U, req.max_k, next_j === 0.U && next_i === 0.U) k := next_k j := next_j i := next_i state := Mux(next_k === 0.U && next_j === 0.U && next_i === 0.U, idle, pre) } } when (io.req.fire) { req := io.req.bits state := pre j := 0.U k := 0.U i := 0.U } assert(!(state =/= idle && req.a_tranpose && req.b_tranpose)) } // StC class LoopMatmulStCReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle { val max_k = UInt(iterator_bitwidth.W) val max_j = UInt(iterator_bitwidth.W) val max_i = UInt(iterator_bitwidth.W) val pad_j = UInt(log2Up(block_size).W) val pad_i = UInt(log2Up(block_size).W) val dram_addr = UInt(coreMaxAddrBits.W) val dram_stride = UInt(coreMaxAddrBits.W) val full_c = Bool() val act = UInt(Activation.bitwidth.W) val addr_start = UInt(log2Up(max_acc_addr).W) val loop_id = UInt(log2Up(concurrent_loops).W) val is_resadd = Bool() } class LoopMatmulStC(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, max_block_len: Int, concurrent_loops: Int, mvout_rs2_t: MvoutRs2) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new LoopMatmulStCReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, concurrent_loops))) val cmd = Decoupled(Output(new RoCCCommand)) val ex_k = Input(UInt(iterator_bitwidth.W)) val ex_j = Input(UInt(iterator_bitwidth.W)) val ex_i = Input(UInt(iterator_bitwidth.W)) val ex_completed = Input(Bool()) val j = Output(UInt(iterator_bitwidth.W)) val i = Output(UInt(iterator_bitwidth.W)) val idle = Output(Bool()) val rob_overloaded = Input(Bool()) val loop_id = Output(UInt(log2Up(concurrent_loops).W)) }) object State extends ChiselEnum { val idle, st, ln_config, ln_st = Value } import State._ val state = RegInit(idle) val req = Reg(new LoopMatmulStCReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, concurrent_loops)) val max_blocks = Mux(req.full_c, 1.U, Mux(req.max_j <= max_block_len.U, req.max_j, max_block_len.U)) // Non-normalization-related iterators and calculations val j = Reg(UInt(iterator_bitwidth.W)) val i = Reg(UInt(iterator_bitwidth.W)) val acc_addr_start = /*(BigInt(1) << 31).U | (req.full_c << 29.U).asUInt |*/ req.addr_start val dram_offset = Mux(req.full_c, (i * req.dram_stride + j) * block_size.U * (acc_w/8).U, (i * req.dram_stride + j) * block_size.U * (input_w/8).U) val dram_addr = req.dram_addr + LoopMatmul.castDramOffset(dram_offset) val sp_addr = acc_addr_start + (i * req.max_j + j) * block_size.U val blocks = Mux(j + max_blocks <= req.max_j, max_blocks, req.max_j-j) val cols = (blocks * block_size.U) - Mux(j + blocks >= req.max_j, req.pad_j, 0.U) val rows = block_size.U - Mux(i === req.max_i-1.U, req.pad_i, 0.U) val mvout_cmd = Wire(new RoCCCommand) mvout_cmd := DontCare mvout_cmd.inst.funct := STORE_CMD mvout_cmd.rs1 := dram_addr val mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) mvout_cmd_rs2 := DontCare mvout_cmd_rs2.num_rows := rows.asUInt mvout_cmd_rs2.num_cols := cols.asUInt mvout_cmd_rs2.local_addr := cast_to_acc_addr(mvout_cmd_rs2.local_addr, sp_addr, accumulate = false.B, read_full = req.full_c) mvout_cmd.rs2 := mvout_cmd_rs2.asUInt // Layernorm iterators and calculations val ln_row = Reg(UInt(iterator_bitwidth.W)) val ln_cmd = Reg(UInt(iterator_bitwidth.W)) val ln_stat_id = Reg(UInt(iterator_bitwidth.W)) val NORM_STAT_IDS = 2 // TODO magic number val ln_norm_cmds = VecInit(VecInit(NormCmd.SUM, NormCmd.MEAN), VecInit(NormCmd.VARIANCE, NormCmd.INV_STDDEV), VecInit(NormCmd.RESET, NormCmd.RESET)) val sm_norm_cmds = VecInit(VecInit(NormCmd.MAX, NormCmd.MAX), VecInit(NormCmd.SUM_EXP, NormCmd.INV_SUM_EXP), VecInit(NormCmd.RESET, NormCmd.RESET)) val ln_stat_ids = Mux(rows -& ln_row > NORM_STAT_IDS.U, NORM_STAT_IDS.U, rows -& ln_row) val ln_r = ln_row +& ln_stat_id val ln_sp_addr = acc_addr_start +& (i * req.max_j +& j) * block_size.U +& ln_r val ln_norm_cmd = Mux(j +& max_blocks >= req.max_j, Mux(req.act === Activation.LAYERNORM, ln_norm_cmds(ln_cmd)(1), sm_norm_cmds(ln_cmd)(1)), Mux(req.act === Activation.LAYERNORM, ln_norm_cmds(ln_cmd)(0), sm_norm_cmds(ln_cmd)(0))) // TODO we assume for now that full_C and layernorm aren't true at the same val ln_dram_offset = ((i * req.dram_stride +& j) * block_size.U +& ln_r * req.dram_stride) * (input_w/8).U val ln_dram_addr = req.dram_addr + LoopMatmul.castDramOffset(ln_dram_offset) val ln_config_norm_rs1 = Wire(new GemminiISA.ConfigNormRs1) ln_config_norm_rs1 := DontCare ln_config_norm_rs1.set_stats_id_only := 1.U ln_config_norm_rs1.cmd_type := CONFIG_NORM ln_config_norm_rs1.norm_stats_id := ln_stat_id val ln_config_norm = Wire(new RoCCCommand) ln_config_norm := DontCare ln_config_norm.inst.funct := CONFIG_CMD ln_config_norm.rs1 := ln_config_norm_rs1.asUInt ln_config_norm.rs2 := DontCare val ln_mvout_cmd = Wire(new RoCCCommand) ln_mvout_cmd := DontCare ln_mvout_cmd.inst.funct := STORE_CMD ln_mvout_cmd.rs1 := ln_dram_addr val ln_mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType) ln_mvout_cmd_rs2 := DontCare ln_mvout_cmd_rs2.num_rows := 1.U ln_mvout_cmd_rs2.num_cols := cols.asUInt ln_mvout_cmd_rs2.local_addr := cast_to_acc_addr(ln_mvout_cmd_rs2.local_addr, ln_sp_addr, accumulate = false.B, read_full = req.full_c) ln_mvout_cmd_rs2.local_addr.norm_cmd := ln_norm_cmd ln_mvout_cmd.rs2 := ln_mvout_cmd_rs2.asUInt io.req.ready := state === idle io.j := j io.i := i io.idle := state === idle // The order here is k, j, i when not doing LAYERNORM or SOFTMAX val ex_ahead = WireInit(io.ex_completed || ((req.act =/= Activation.LAYERNORM) && (req.act =/= Activation.SOFTMAX) && (io.ex_k === req.max_k - 1.U && (io.ex_j >= j + blocks || ((io.ex_j === j + blocks - 1.U) && io.ex_i > i))))) when(req.is_resadd){ ex_ahead := io.ex_completed || (io.ex_i > i || (io.ex_i === i && io.ex_j >= j + blocks)) } io.cmd.valid := state =/= idle && !io.rob_overloaded && ex_ahead && req.dram_addr =/= 0.U io.cmd.bits := MuxCase(mvout_cmd, Seq( (state === ln_config) -> ln_config_norm, (state === ln_st) -> ln_mvout_cmd, )) io.loop_id := req.loop_id when (req.dram_addr === 0.U) { state := idle }.elsewhen (io.cmd.fire && state === st) { // The order here is k, j, i val next_i = floorAdd(i, 1.U, req.max_i) val next_j = floorAdd(j, max_blocks, req.max_j, next_i === 0.U) i := next_i j := next_j when (next_i === 0.U && next_j === 0.U) { state := idle } }.elsewhen (io.cmd.fire && state === ln_config) { state := ln_st }.elsewhen (io.cmd.fire && state === ln_st) { val next_j = floorAdd(j, max_blocks, req.max_j) val next_stat_id = floorAdd(ln_stat_id, 1.U, ln_stat_ids, next_j === 0.U) val next_cmd = floorAdd(ln_cmd, 1.U, ln_norm_cmds.size.U, next_j === 0.U && next_stat_id === 0.U) val next_row = floorAdd(ln_row, NORM_STAT_IDS.U, rows, next_j === 0.U && next_stat_id === 0.U && next_cmd === 0.U) val next_i = floorAdd(i, 1.U, req.max_i, next_j === 0.U && next_stat_id === 0.U && next_cmd === 0.U && next_row === 0.U) j := next_j ln_stat_id := next_stat_id ln_cmd := next_cmd ln_row := next_row i := next_i when (next_i === 0.U && next_row === 0.U && next_cmd === 0.U && next_stat_id === 0.U && next_j === 0.U) { state := idle }.elsewhen (next_j === 0.U) { state := ln_config } } when (io.req.fire) { req := io.req.bits state := Mux((io.req.bits.act === Activation.LAYERNORM) || (io.req.bits.act === Activation.SOFTMAX), ln_config, st) j := 0.U i := 0.U ln_row := 0.U ln_cmd := 0.U ln_stat_id := 0.U } } // Combined loop class LoopMatmulState(val iterator_bitwidth: Int, val coreMaxAddrBits: Int, val max_addr: Int, val max_acc_addr: Int) extends Bundle { val max_k = UInt(iterator_bitwidth.W) val max_j = UInt(iterator_bitwidth.W) val max_i = UInt(iterator_bitwidth.W) val pad_k = UInt(iterator_bitwidth.W) val pad_j = UInt(iterator_bitwidth.W) val pad_i = UInt(iterator_bitwidth.W) val a_dram_addr = UInt(coreMaxAddrBits.W) val b_dram_addr = UInt(coreMaxAddrBits.W) val d_dram_addr = UInt(coreMaxAddrBits.W) val c_dram_addr = UInt(coreMaxAddrBits.W) val a_dram_stride = UInt(coreMaxAddrBits.W) val b_dram_stride = UInt(coreMaxAddrBits.W) val d_dram_stride = UInt(coreMaxAddrBits.W) val c_dram_stride = UInt(coreMaxAddrBits.W) val a_transpose = Bool() val b_transpose = Bool() val act = UInt(Activation.bitwidth.W) val low_d = Bool() val full_c = Bool() val ex_accumulate = Bool() val a_ex_spad_id = UInt(2.W) val b_ex_spad_id = UInt(2.W) val configured = Bool() val running = Bool() val lda_started = Bool() val ldb_started = Bool() val ex_started = Bool() val ldd_started = Bool() val st_started = Bool() val lda_completed = Bool() val ldb_completed = Bool() val ex_completed = Bool() val ldd_completed = Bool() val st_completed = Bool() def all_completed(dummy: Int=0): Bool = lda_completed && ldb_completed && ldd_completed && ex_completed && st_completed val a_addr_start = UInt(log2Up(max_addr).W) val b_addr_end = UInt(log2Up(max_addr+1).W) val resadd_addr_start = UInt(log2Up(max_acc_addr).W) def reset(): Unit = { configured := false.B running := false.B lda_started := false.B ldb_started := false.B ex_started := false.B ldd_started := false.B st_started := false.B lda_completed := false.B ldb_completed := false.B ex_completed := false.B ldd_completed := false.B st_completed := false.B //is_resadd := false.B } } class LoopMatmul(block_size: Int, coreMaxAddrBits: Int, reservation_station_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, mvin_rs2_t: MvinRs2, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, mvout_rs2_t: MvoutRs2) (implicit p: Parameters) extends Module { val iterator_bitwidth = 16 val max_block_len = (dma_max_bytes / (block_size * input_w / 8)) max 1 val max_block_len_acc = (dma_max_bytes / (block_size * acc_w / 8)) max 1 val io = IO(new Bundle { val in = Flipped(Decoupled(new GemminiCmd(reservation_station_size))) val out = Decoupled(new GemminiCmd(reservation_station_size)) val ld_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val st_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val ex_completed = Input(UInt(log2Up(reservation_station_size+1).W)) val busy = Output(Bool()) }) // Create states val concurrent_loops = 2 val loops = Reg(Vec(concurrent_loops, new LoopMatmulState(iterator_bitwidth, coreMaxAddrBits, max_addr, max_acc_addr))) val head_loop_id = Reg(UInt(log2Up(concurrent_loops).W)) val tail_loop_id = (~head_loop_id).asUInt // This is the loop that we always try to configure if available val head_loop = loops(head_loop_id) val tail_loop = loops(tail_loop_id) val loop_configured = loops.map(_.configured).reduce(_ || _) val loop_being_configured_id = Mux(head_loop.configured, tail_loop_id, head_loop_id) val loop_being_configured = loops(loop_being_configured_id) val is_resadd = RegInit(false.B) val max_all_addr = if(max_addr > max_acc_addr) max_addr else max_acc_addr // Create inner modules val ldA = Module(new LoopMatmulLdA(block_size, coreMaxAddrBits, iterator_bitwidth, max_all_addr, input_w, max_block_len, concurrent_loops, mvin_rs2_t)) val ldB = Module(new LoopMatmulLdB(block_size, coreMaxAddrBits, iterator_bitwidth, max_all_addr, input_w, max_block_len, concurrent_loops, mvin_rs2_t)) val ldD = Module(new LoopMatmulLdD(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, input_w, acc_w, max_block_len, max_block_len_acc, concurrent_loops, mvin_rs2_t)) val ex = Module(new LoopMatmulExecute(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t)) val stC = Module(new LoopMatmulStC(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, input_w, acc_w, max_block_len, concurrent_loops, mvout_rs2_t)) // Create command queue val cmd = Queue(io.in) io.busy := cmd.valid || loop_configured // Create ld arbiters val ldab_arb = Module(new WeightedArbiter(new RoCCCommand(), maxWeightA=255, staticWeightAEnabled=true)) // TODO magic numbers ldab_arb.io.inA <> ldA.io.cmd ldab_arb.io.inB <> ldB.io.cmd val ab_loads_on_same_loop = ldA.io.loop_id === ldB.io.loop_id val forceA = !ab_loads_on_same_loop && ldA.io.loop_id === head_loop_id val forceB = !ab_loads_on_same_loop && ldB.io.loop_id === head_loop_id ldab_arb.io.forceA := Mux(is_resadd, ab_loads_on_same_loop && !ldA.io.idle, forceA) ldab_arb.io.forceB := Mux(is_resadd, forceB || ldA.io.idle, forceB) ldab_arb.io.weightA := 0.U ldab_arb.io.inA_idle := ldA.io.idle ldab_arb.io.inB_idle := ldB.io.idle ldab_arb.io.inA_k := ldA.io.k ldab_arb.io.inA_i := ldA.io.i ldab_arb.io.inB_k := ldB.io.k ldab_arb.io.inB_j := ldB.io.j // Create global arbiter val arb = Module(new Arbiter(new RoCCCommand(), 4)) arb.io.in(0) <> stC.io.cmd arb.io.in(1) <> ex.io.cmd arb.io.in(2) <> ldD.io.cmd arb.io.in(3) <> ldab_arb.io.out val unrolled_cmd = arb.io.out // Create reservation station utilization counters val ld_utilization = RegInit(0.U(log2Up(max_lds+1).W)) val st_utilization = RegInit(0.U(log2Up(max_sts+1).W)) val ex_utilization = RegInit(0.U(log2Up(max_exs+1).W)) ld_utilization := ld_utilization +& (ldA.io.cmd.fire || ldB.io.cmd.fire || ldD.io.cmd.fire) -& io.ld_completed st_utilization := st_utilization +& stC.io.cmd.fire -& io.st_completed ex_utilization := ex_utilization +& ex.io.cmd.fire -& io.ex_completed assert(ld_utilization >= io.ld_completed, "ld utilization underflow") assert(st_utilization >= io.st_completed, "st utilization underflow") assert(ex_utilization >= io.ex_completed, "ex utilization underflow") // Wire up unrolled command output val is_loop_run_cmd = cmd.bits.cmd.inst.funct === LOOP_WS val is_loop_config_cmd = cmd.bits.cmd.inst.funct >= LOOP_WS_CONFIG_BOUNDS && cmd.bits.cmd.inst.funct <= LOOP_WS_CONFIG_STRIDES_DC val is_loop_cmd = is_loop_run_cmd || is_loop_config_cmd io.out.bits.cmd := Mux(loop_configured, unrolled_cmd.bits, cmd.bits.cmd) io.out.bits.cmd.status := cmd.bits.cmd.status // TODO This is not guaranteed to be the correct fix! We must fix this io.out.bits.rob_id := DontCare io.out.bits.from_matmul_fsm := Mux(loop_configured, true.B, cmd.bits.from_matmul_fsm) io.out.bits.from_conv_fsm := Mux(loop_configured, false.B, cmd.bits.from_conv_fsm) io.out.valid := Mux(loop_configured, unrolled_cmd.valid, cmd.valid && !is_loop_config_cmd && !is_loop_run_cmd) cmd.ready := Mux(is_loop_cmd, !loop_being_configured.configured, !loop_configured && io.out.ready) arb.io.out.ready := io.out.ready // Wire up overloaded signals ldA.io.rob_overloaded := ld_utilization >= max_lds.U ldB.io.rob_overloaded := ld_utilization >= max_lds.U ex.io.rob_overloaded := ex_utilization >= max_exs.U ldD.io.rob_overloaded := ld_utilization >= max_lds.U stC.io.rob_overloaded := st_utilization >= max_sts.U // Wire up iterator inputs ex.io.lda_completed := (ldA.io.loop_id =/= ex.io.loop_id) || ldA.io.idle ex.io.ldb_completed := (ldB.io.loop_id =/= ex.io.loop_id) || ldB.io.idle ex.io.ldd_completed := (ldD.io.loop_id =/= ex.io.loop_id) || ldD.io.idle ex.io.ld_ka := ldA.io.k ex.io.ld_kb := ldB.io.k ex.io.ld_j := ldB.io.j ex.io.ld_i := ldA.io.i stC.io.ex_completed := (ex.io.loop_id =/= stC.io.loop_id) || ex.io.idle stC.io.ex_k := ex.io.k stC.io.ex_j := ex.io.j stC.io.ex_i := ex.io.i // when loop matmul is used as resadd unroller // skip ex // track ldB instead of ex when(is_resadd){ stC.io.ex_completed := (ldA.io.loop_id =/= stC.io.loop_id || ldA.io.idle) && (ldB.io.loop_id =/= stC.io.loop_id || ldB.io.idle) stC.io.ex_k := 0.U // req.max_k shall be 1 stC.io.ex_j := ldB.io.j stC.io.ex_i := ldB.io.k //ldB.io.rob_overloaded := ld_utilization >= max_lds.U || !((ldA.io.loop_id =/= ldB.io.loop_id) || ldA.io.idle) } val loops_configured = RegInit(0.U(16.W)) dontTouch(loops_configured) // Create config registers when(cmd.valid && is_loop_cmd && !loop_being_configured.configured) { switch (cmd.bits.cmd.inst.funct) { is (LOOP_WS_CONFIG_BOUNDS) { loop_being_configured.max_k := cmd.bits.cmd.rs2(iterator_bitwidth * 3 - 1, iterator_bitwidth * 2) loop_being_configured.max_j := cmd.bits.cmd.rs2(iterator_bitwidth * 2 - 1, iterator_bitwidth) loop_being_configured.max_i := cmd.bits.cmd.rs2(iterator_bitwidth-1, 0) loop_being_configured.pad_k := cmd.bits.cmd.rs1(iterator_bitwidth * 3 - 1, iterator_bitwidth * 2) loop_being_configured.pad_j := cmd.bits.cmd.rs1(iterator_bitwidth * 2 - 1, iterator_bitwidth) loop_being_configured.pad_i := cmd.bits.cmd.rs1(iterator_bitwidth-1, 0) } is (LOOP_WS_CONFIG_ADDRS_AB) { loop_being_configured.a_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.b_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_WS_CONFIG_ADDRS_DC) { loop_being_configured.d_dram_addr := cmd.bits.cmd.rs1 loop_being_configured.c_dram_addr := cmd.bits.cmd.rs2 } is (LOOP_WS_CONFIG_STRIDES_AB) { loop_being_configured.a_dram_stride := cmd.bits.cmd.rs1 loop_being_configured.b_dram_stride := cmd.bits.cmd.rs2 } is (LOOP_WS_CONFIG_STRIDES_DC) { loop_being_configured.d_dram_stride := cmd.bits.cmd.rs1 loop_being_configured.c_dram_stride := cmd.bits.cmd.rs2 } is (LOOP_WS) { loop_being_configured.ex_accumulate := cmd.bits.cmd.rs1(0) loop_being_configured.full_c := cmd.bits.cmd.rs1(1) loop_being_configured.low_d := cmd.bits.cmd.rs1(2) loop_being_configured.act := cmd.bits.cmd.rs1(8+Activation.bitwidth-1, 8) // TODO magic numbers loop_being_configured.a_ex_spad_id := cmd.bits.cmd.rs1(19, 18) loop_being_configured.b_ex_spad_id := cmd.bits.cmd.rs1(17, 16) loop_being_configured.a_transpose := cmd.bits.cmd.rs2(0) loop_being_configured.b_transpose := cmd.bits.cmd.rs2(1) is_resadd := cmd.bits.cmd.rs2(2) loop_being_configured.configured := true.B loops_configured := loops_configured + 1.U } } } // Wire up request signals val ld_d_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val ex_c_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val st_c_addr_start = RegInit(0.U(log2Up(max_acc_addr).W)) val loop_requesting_ldA_id = Mux(head_loop.lda_started, tail_loop_id, head_loop_id) val loop_requesting_ldA = loops(loop_requesting_ldA_id) ldA.io.req.bits.max_k := Mux(is_resadd, loop_requesting_ldA.max_j, loop_requesting_ldA.max_k) ldA.io.req.bits.max_i := loop_requesting_ldA.max_i ldA.io.req.bits.pad_k := Mux(is_resadd, loop_requesting_ldA.pad_j, loop_requesting_ldA.pad_k) ldA.io.req.bits.pad_i := loop_requesting_ldA.pad_i ldA.io.req.bits.dram_addr := loop_requesting_ldA.a_dram_addr ldA.io.req.bits.dram_stride := loop_requesting_ldA.a_dram_stride ldA.io.req.bits.transpose := loop_requesting_ldA.a_transpose ldA.io.req.bits.addr_start := Mux(loop_requesting_ldA.a_ex_spad_id === 0.U, loop_requesting_ldA.a_addr_start, (loop_requesting_ldA.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ldA.io.req.bits.loop_id := loop_requesting_ldA_id ldA.io.req.bits.is_resadd := is_resadd ldA.io.req.valid := !loop_requesting_ldA.lda_started && loop_requesting_ldA.configured when (ldA.io.req.fire) { loop_requesting_ldA.running := true.B loop_requesting_ldA.lda_started := true.B } val loop_requesting_ldB_id = Mux(head_loop.ldb_started, tail_loop_id, head_loop_id) val loop_requesting_ldB = loops(loop_requesting_ldB_id) ldB.io.req.bits.max_j := loop_requesting_ldB.max_j ldB.io.req.bits.max_k := Mux(is_resadd, loop_requesting_ldB.max_i, loop_requesting_ldB.max_k) ldB.io.req.bits.pad_j := loop_requesting_ldB.pad_j ldB.io.req.bits.pad_k := Mux(is_resadd, loop_requesting_ldB.pad_i, loop_requesting_ldB.pad_k) ldB.io.req.bits.dram_addr := loop_requesting_ldB.b_dram_addr ldB.io.req.bits.dram_stride := loop_requesting_ldB.b_dram_stride ldB.io.req.bits.transpose := loop_requesting_ldB.b_transpose ldB.io.req.bits.addr_end := Mux(loop_requesting_ldB.b_ex_spad_id === 0.U, loop_requesting_ldB.b_addr_end, (loop_requesting_ldB.b_ex_spad_id) * (max_addr / concurrent_loops).U) ldB.io.req.bits.loop_id := loop_requesting_ldB_id ldB.io.req.bits.is_resadd := is_resadd ldB.io.req.valid := !loop_requesting_ldB.ldb_started && loop_requesting_ldB.configured when (ldB.io.req.fire) { loop_requesting_ldB.running := true.B loop_requesting_ldB.ldb_started := true.B } val loop_requesting_ex_id = Mux(head_loop.ex_started, tail_loop_id, head_loop_id) val loop_requesting_ex = loops(loop_requesting_ex_id) ex.io.req.bits.max_j := loop_requesting_ex.max_j ex.io.req.bits.max_k := loop_requesting_ex.max_k ex.io.req.bits.max_i := loop_requesting_ex.max_i ex.io.req.bits.pad_j := loop_requesting_ex.pad_j ex.io.req.bits.pad_k := loop_requesting_ex.pad_k ex.io.req.bits.pad_i := loop_requesting_ex.pad_i ex.io.req.bits.accumulate := loop_requesting_ex.ex_accumulate ex.io.req.bits.a_addr_start := Mux(loop_requesting_ex.a_ex_spad_id === 0.U, loop_requesting_ex.a_addr_start, (loop_requesting_ex.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U) ex.io.req.bits.b_addr_end := Mux(loop_requesting_ex.b_ex_spad_id === 0.U, loop_requesting_ex.b_addr_end, (loop_requesting_ex.b_ex_spad_id) * (max_addr / concurrent_loops).U) ex.io.req.bits.a_tranpose := loop_requesting_ex.a_transpose ex.io.req.bits.b_tranpose := loop_requesting_ex.b_transpose ex.io.req.bits.c_addr_start := ex_c_addr_start ex.io.req.bits.loop_id := loop_requesting_ex_id ex.io.req.bits.skip := is_resadd ex.io.req.valid := !loop_requesting_ex.ex_started && loop_requesting_ex.lda_started && loop_requesting_ex.ldb_started && loop_requesting_ex.ldd_started && loop_requesting_ex.configured when (ex.io.req.fire) { loop_requesting_ex.running := true.B loop_requesting_ex.ex_started := true.B when (loop_requesting_ex.c_dram_addr =/= 0.U) { ex_c_addr_start := floorAdd(ex_c_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_ldD_id = Mux(head_loop.ldd_started, tail_loop_id, head_loop_id) val loop_requesting_ldD = loops(loop_requesting_ldD_id) ldD.io.req.bits.max_j := loop_requesting_ldD.max_j ldD.io.req.bits.max_i := loop_requesting_ldD.max_i ldD.io.req.bits.pad_j := loop_requesting_ldD.pad_j ldD.io.req.bits.pad_i := loop_requesting_ldD.pad_i ldD.io.req.bits.dram_addr := loop_requesting_ldD.d_dram_addr ldD.io.req.bits.dram_stride := loop_requesting_ldD.d_dram_stride ldD.io.req.bits.low_d := loop_requesting_ldD.low_d ldD.io.req.bits.addr_start := ld_d_addr_start ldD.io.req.bits.loop_id := loop_requesting_ldD_id ldD.io.req.valid := !loop_requesting_ldD.ldd_started && loop_requesting_ldD.configured when (ldD.io.req.fire) { loop_requesting_ldD.running := true.B loop_requesting_ldD.ldd_started := true.B when (loop_requesting_ldD.c_dram_addr =/= 0.U) { ld_d_addr_start := floorAdd(ld_d_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } val loop_requesting_st_id = Mux(head_loop.st_started, tail_loop_id, head_loop_id) val loop_requesting_st = loops(loop_requesting_st_id) stC.io.req.bits.max_k := Mux(is_resadd, 1.U, loop_requesting_st.max_k) stC.io.req.bits.max_j := loop_requesting_st.max_j stC.io.req.bits.max_i := loop_requesting_st.max_i stC.io.req.bits.pad_j := loop_requesting_st.pad_j stC.io.req.bits.pad_i := loop_requesting_st.pad_i stC.io.req.bits.dram_addr := loop_requesting_st.c_dram_addr stC.io.req.bits.dram_stride := loop_requesting_st.c_dram_stride stC.io.req.bits.full_c := loop_requesting_st.full_c stC.io.req.bits.act := loop_requesting_st.act stC.io.req.bits.addr_start := st_c_addr_start stC.io.req.bits.loop_id := loop_requesting_st_id stC.io.req.bits.is_resadd := is_resadd stC.io.req.valid := !loop_requesting_st.st_started && loop_requesting_st.ex_started && loop_requesting_st.configured when (stC.io.req.fire) { loop_requesting_st.running := true.B loop_requesting_st.st_started := true.B when (loop_requesting_st.c_dram_addr =/= 0.U) { st_c_addr_start := floorAdd(st_c_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U) } } when(is_resadd){ ldA.io.req.bits.addr_start := loop_requesting_ldA.resadd_addr_start ldB.io.req.bits.addr_end := loop_requesting_ldB.resadd_addr_start stC.io.req.bits.addr_start := loop_requesting_st.resadd_addr_start stC.io.req.valid := !loop_requesting_st.st_started && loop_requesting_st.configured } // Handle completed signals when (ldA.io.idle && loops(ldA.io.loop_id).running && loops(ldA.io.loop_id).lda_started) { loops(ldA.io.loop_id).lda_completed := true.B } when (ldB.io.idle && loops(ldB.io.loop_id).running && loops(ldB.io.loop_id).ldb_started) { loops(ldB.io.loop_id).ldb_completed := true.B } when (ex.io.idle && loops(ex.io.loop_id).running && loops(ex.io.loop_id).ex_started) { loops(ex.io.loop_id).ex_completed := true.B } when (ldD.io.idle && loops(ldD.io.loop_id).running && loops(ldD.io.loop_id).ldd_started) { loops(ldD.io.loop_id).ldd_completed := true.B } when (stC.io.idle && loops(stC.io.loop_id).running && loops(stC.io.loop_id).st_started) { loops(stC.io.loop_id).st_completed := true.B } when (head_loop.running && head_loop.all_completed()) { head_loop.reset() head_loop_id := ~head_loop_id } // Resets when (reset.asBool) { loops.zipWithIndex.foreach { case (l, i) => l.reset() l.a_addr_start := (i * (max_addr / concurrent_loops)).U l.b_addr_end := ((i+1) * (max_addr / concurrent_loops)).U l.resadd_addr_start := (i * (max_acc_addr / concurrent_loops)).U } } } object LoopMatmul { def apply(in: DecoupledIO[GemminiCmd], ld_completed: UInt, st_completed: UInt, ex_completed: UInt, block_size: Int, coreMaxAddrBits: Int, rob_size: Int, max_lds: Int, max_exs: Int, max_sts: Int, max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int, mvin_rs2_t: MvinRs2, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs, compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, mvout_rs2_t: MvoutRs2) (implicit p: Parameters): (DecoupledIO[GemminiCmd], Bool) = { val mod = Module(new LoopMatmul(block_size, coreMaxAddrBits, rob_size, max_lds, max_exs, max_sts, max_addr, max_acc_addr, input_w, acc_w, dma_max_bytes, mvin_rs2_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t, mvout_rs2_t)) mod.io.in <> in mod.io.ld_completed := ld_completed mod.io.st_completed := st_completed mod.io.ex_completed := ex_completed (mod.io.out, mod.io.busy) } def castDramOffset(dram_offset: UInt): UInt = { // Cast dram offsets to 32 bits max dram_offset & "hFFFFFFFF".U } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File FrontendTLB.scala: package gemmini import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.tile.{CoreBundle, CoreModule} import freechips.rocketchip.tilelink.TLEdgeOut import Util._ import midas.targetutils.PerfCounter class DecoupledTLBReq(val lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle { val tlb_req = new TLBReq(lgMaxSize) val status = new MStatus } class TLBExceptionIO extends Bundle { val interrupt = Output(Bool()) val flush_retry = Input(Bool()) val flush_skip = Input(Bool()) def flush(dummy: Int = 0): Bool = flush_retry || flush_skip } // TODO can we make TLB hits only take one cycle? class DecoupledTLB(entries: Int, maxSize: Int, use_firesim_simulation_counters: Boolean)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule { val lgMaxSize = log2Ceil(maxSize) val io = IO(new Bundle { val req = Flipped(Valid(new DecoupledTLBReq(lgMaxSize))) val resp = new TLBResp val ptw = new TLBPTWIO val exp = new TLBExceptionIO val counter = new CounterEventIO() }) val interrupt = RegInit(false.B) io.exp.interrupt := interrupt val tlb = Module(new TLB(false, lgMaxSize, TLBConfig(nSets=1, nWays=entries))) tlb.io.req.valid := io.req.valid tlb.io.req.bits := io.req.bits.tlb_req io.resp := tlb.io.resp tlb.io.kill := false.B tlb.io.sfence.valid := io.exp.flush() tlb.io.sfence.bits.rs1 := false.B tlb.io.sfence.bits.rs2 := false.B tlb.io.sfence.bits.addr := DontCare tlb.io.sfence.bits.asid := DontCare tlb.io.sfence.bits.hv := false.B tlb.io.sfence.bits.hg := false.B io.ptw <> tlb.io.ptw tlb.io.ptw.status := io.req.bits.status val exception = io.req.valid && Mux(io.req.bits.tlb_req.cmd === M_XRD, tlb.io.resp.pf.ld || tlb.io.resp.ae.ld, tlb.io.resp.pf.st || tlb.io.resp.ae.st) when (exception) { interrupt := true.B } when (interrupt && tlb.io.sfence.fire) { interrupt := false.B } assert(!io.exp.flush_retry || !io.exp.flush_skip, "TLB: flushing with both retry and skip at same time") CounterEventIO.init(io.counter) io.counter.connectEventSignal(CounterEvent.DMA_TLB_HIT_REQ, io.req.fire && !tlb.io.resp.miss) io.counter.connectEventSignal(CounterEvent.DMA_TLB_TOTAL_REQ, io.req.fire) io.counter.connectEventSignal(CounterEvent.DMA_TLB_MISS_CYCLE, tlb.io.resp.miss) if (use_firesim_simulation_counters) { PerfCounter(io.req.fire && !tlb.io.resp.miss, "tlb_hits", "total number of tlb hits") PerfCounter(io.req.fire, "tlb_reqs", "total number of tlb reqs") PerfCounter(tlb.io.resp.miss, "tlb_miss_cycles", "total number of cycles where the tlb is resolving a miss") } } class FrontendTLBIO(implicit p: Parameters) extends CoreBundle { val lgMaxSize = log2Ceil(coreDataBytes) // val req = Decoupled(new TLBReq(lgMaxSize)) val req = Valid(new DecoupledTLBReq(lgMaxSize)) val resp = Flipped(new TLBResp) } class FrontendTLB(nClients: Int, entries: Int, maxSize: Int, use_tlb_register_filter: Boolean, use_firesim_simulation_counters: Boolean, use_shared_tlb: Boolean) (implicit edge: TLEdgeOut, p: Parameters) extends CoreModule { val num_tlbs = if (use_shared_tlb) 1 else nClients val lgMaxSize = log2Ceil(coreDataBytes) val io = IO(new Bundle { val clients = Flipped(Vec(nClients, new FrontendTLBIO)) val ptw = Vec(num_tlbs, new TLBPTWIO) val exp = Vec(num_tlbs, new TLBExceptionIO) val counter = new CounterEventIO() }) val tlbs = Seq.fill(num_tlbs)(Module(new DecoupledTLB(entries, maxSize, use_firesim_simulation_counters))) io.ptw <> VecInit(tlbs.map(_.io.ptw)) io.exp <> VecInit(tlbs.map(_.io.exp)) val tlbArbOpt = if (use_shared_tlb) Some(Module(new RRArbiter(new DecoupledTLBReq(lgMaxSize), nClients))) else None if (use_shared_tlb) { val tlbArb = tlbArbOpt.get val tlb = tlbs.head tlb.io.req.valid := tlbArb.io.out.valid tlb.io.req.bits := tlbArb.io.out.bits tlbArb.io.out.ready := true.B } io.clients.zipWithIndex.foreach { case (client, i) => val last_translated_valid = RegInit(false.B) val last_translated_vpn = RegInit(0.U(vaddrBits.W)) val last_translated_ppn = RegInit(0.U(paddrBits.W)) val l0_tlb_hit = last_translated_valid && ((client.req.bits.tlb_req.vaddr >> pgIdxBits).asUInt === (last_translated_vpn >> pgIdxBits).asUInt) val l0_tlb_paddr = Cat(last_translated_ppn >> pgIdxBits, client.req.bits.tlb_req.vaddr(pgIdxBits-1,0)) val tlb = if (use_shared_tlb) tlbs.head else tlbs(i) val tlbReq = if (use_shared_tlb) tlbArbOpt.get.io.in(i).bits else tlb.io.req.bits val tlbReqValid = if (use_shared_tlb) tlbArbOpt.get.io.in(i).valid else tlb.io.req.valid val tlbReqFire = if (use_shared_tlb) tlbArbOpt.get.io.in(i).fire else tlb.io.req.fire tlbReqValid := RegNext(client.req.valid && !l0_tlb_hit) tlbReq := RegNext(client.req.bits) when (tlbReqFire && !tlb.io.resp.miss) { last_translated_valid := true.B last_translated_vpn := tlbReq.tlb_req.vaddr last_translated_ppn := tlb.io.resp.paddr } when (tlb.io.exp.flush()) { last_translated_valid := false.B } when (tlbReqFire) { client.resp := tlb.io.resp }.otherwise { client.resp := DontCare client.resp.paddr := RegNext(l0_tlb_paddr) client.resp.miss := !RegNext(l0_tlb_hit) } // If we're not using the TLB filter register, then we set this value to always be false if (!use_tlb_register_filter) { last_translated_valid := false.B } } // TODO Return the sum of the TLB counters, rather than just the counters of the first TLB. This only matters if we're // not using the shared TLB io.counter := DontCare tlbs.foreach(_.io.counter.external_reset := false.B) io.counter.collect(tlbs.head.io.counter) } File Controller.scala: package gemmini import java.nio.charset.StandardCharsets import java.nio.file.{Files, Paths} import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.util.ClockGate import freechips.rocketchip.tilelink.TLIdentityNode import GemminiISA._ import Util._ class GemminiCmd(rob_entries: Int)(implicit p: Parameters) extends Bundle { val cmd = new RoCCCommand val rob_id = UDValid(UInt(log2Up(rob_entries).W)) val from_matmul_fsm = Bool() val from_conv_fsm = Bool() } class Gemmini[T <: Data : Arithmetic, U <: Data, V <: Data](val config: GemminiArrayConfig[T, U, V]) (implicit p: Parameters) extends LazyRoCC ( opcodes = config.opcodes, nPTWPorts = if (config.use_shared_tlb) 1 else 2) { Files.write(Paths.get(config.headerFilePath), config.generateHeader().getBytes(StandardCharsets.UTF_8)) if (System.getenv("GEMMINI_ONLY_GENERATE_GEMMINI_H") == "1") { System.exit(1) } val xLen = p(TileKey).core.xLen val spad = LazyModule(new Scratchpad(config)) override lazy val module = new GemminiModule(this) override val tlNode = if (config.use_dedicated_tl_port) spad.id_node else TLIdentityNode() override val atlNode = if (config.use_dedicated_tl_port) TLIdentityNode() else spad.id_node val node = if (config.use_dedicated_tl_port) tlNode else atlNode } class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data] (outer: Gemmini[T, U, V]) extends LazyRoCCModuleImp(outer) with HasCoreParameters { import outer.config._ import outer.spad val ext_mem_io = if (use_shared_ext_mem) Some(IO(new ExtSpadMemIO(sp_banks, acc_banks, acc_sub_banks))) else None ext_mem_io.foreach(_ <> outer.spad.module.io.ext_mem.get) val tagWidth = 32 // Counters val counters = Module(new CounterController(outer.config.num_counter, outer.xLen)) io.resp <> counters.io.out // Counter access command will be committed immediately counters.io.event_io.external_values(0) := 0.U counters.io.event_io.event_signal(0) := false.B counters.io.in.valid := false.B counters.io.in.bits := DontCare counters.io.event_io.collect(spad.module.io.counter) // TLB implicit val edge = outer.spad.id_node.edges.out.head val tlb = Module(new FrontendTLB(2, tlb_size, dma_maxbytes, use_tlb_register_filter, use_firesim_simulation_counters, use_shared_tlb)) (tlb.io.clients zip outer.spad.module.io.tlb).foreach(t => t._1 <> t._2) tlb.io.exp.foreach(_.flush_skip := false.B) tlb.io.exp.foreach(_.flush_retry := false.B) io.ptw <> tlb.io.ptw counters.io.event_io.collect(tlb.io.counter) spad.module.io.flush := tlb.io.exp.map(_.flush()).reduce(_ || _) val clock_en_reg = RegInit(true.B) val gated_clock = if (clock_gate) ClockGate(clock, clock_en_reg, "gemmini_clock_gate") else clock outer.spad.module.clock := gated_clock /* //========================================================================= // Frontends: Incoming commands and ROB //========================================================================= // forward cmd to correct frontend. if the rob is busy, do not forward new // commands to tiler, and vice versa val is_cisc_mode = RegInit(false.B) val raw_cmd = Queue(io.cmd) val funct = raw_cmd.bits.inst.funct val is_cisc_funct = (funct === CISC_CONFIG) || (funct === ADDR_AB) || (funct === ADDR_CD) || (funct === SIZE_MN) || (funct === SIZE_K) || (funct === RPT_BIAS) || (funct === RESET) || (funct === COMPUTE_CISC) val raw_cisc_cmd = WireInit(raw_cmd) val raw_risc_cmd = WireInit(raw_cmd) raw_cisc_cmd.valid := false.B raw_risc_cmd.valid := false.B raw_cmd.ready := false.B //------------------------------------------------------------------------- // cisc val cmd_fsm = CmdFSM(outer.config) cmd_fsm.io.cmd <> raw_cisc_cmd val tiler = TilerController(outer.config) tiler.io.cmd_in <> cmd_fsm.io.tiler //------------------------------------------------------------------------- // risc val unrolled_cmd = LoopUnroller(raw_risc_cmd, outer.config.meshRows * outer.config.tileRows) */ val reservation_station = withClock (gated_clock) { Module(new ReservationStation(outer.config, new GemminiCmd(reservation_station_entries))) } counters.io.event_io.collect(reservation_station.io.counter) when (io.cmd.valid && io.cmd.bits.inst.funct === CLKGATE_EN && !io.busy) { clock_en_reg := io.cmd.bits.rs1(0) } val raw_cmd_q = Module(new Queue(new GemminiCmd(reservation_station_entries), entries = 2)) raw_cmd_q.io.enq.valid := io.cmd.valid io.cmd.ready := raw_cmd_q.io.enq.ready raw_cmd_q.io.enq.bits.cmd := io.cmd.bits raw_cmd_q.io.enq.bits.rob_id := DontCare raw_cmd_q.io.enq.bits.from_conv_fsm := false.B raw_cmd_q.io.enq.bits.from_matmul_fsm := false.B val raw_cmd = raw_cmd_q.io.deq val max_lds = reservation_station_entries_ld val max_exs = reservation_station_entries_ex val max_sts = reservation_station_entries_st val (conv_cmd, loop_conv_unroller_busy) = withClock (gated_clock) { LoopConv(raw_cmd, reservation_station.io.conv_ld_completed, reservation_station.io.conv_st_completed, reservation_station.io.conv_ex_completed, meshRows*tileRows, coreMaxAddrBits, reservation_station_entries, max_lds, max_exs, max_sts, sp_banks * sp_bank_entries, acc_banks * acc_bank_entries, inputType.getWidth, accType.getWidth, dma_maxbytes, new ConfigMvinRs1(mvin_scale_t_bits, block_stride_bits, pixel_repeats_bits), new MvinRs2(mvin_rows_bits, mvin_cols_bits, local_addr_t), new ConfigMvoutRs2(acc_scale_t_bits, 32), new MvoutRs2(mvout_rows_bits, mvout_cols_bits, local_addr_t), new ConfigExRs1(acc_scale_t_bits), new PreloadRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new PreloadRs(mvout_rows_bits, mvout_cols_bits, local_addr_t), new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), has_training_convs, has_max_pool, has_first_layer_optimizations, has_dw_convs) } val (loop_cmd, loop_matmul_unroller_busy) = withClock (gated_clock) { LoopMatmul(conv_cmd, reservation_station.io.matmul_ld_completed, reservation_station.io.matmul_st_completed, reservation_station.io.matmul_ex_completed, meshRows*tileRows, coreMaxAddrBits, reservation_station_entries, max_lds, max_exs, max_sts, sp_banks * sp_bank_entries, acc_banks * acc_bank_entries, inputType.getWidth, accType.getWidth, dma_maxbytes, new MvinRs2(mvin_rows_bits, mvin_cols_bits, local_addr_t), new PreloadRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new PreloadRs(mvout_rows_bits, mvout_cols_bits, local_addr_t), new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new MvoutRs2(mvout_rows_bits, mvout_cols_bits, local_addr_t)) } val unrolled_cmd = Queue(loop_cmd) unrolled_cmd.ready := false.B counters.io.event_io.connectEventSignal(CounterEvent.LOOP_MATMUL_ACTIVE_CYCLES, loop_matmul_unroller_busy) // Wire up controllers to ROB reservation_station.io.alloc.valid := false.B reservation_station.io.alloc.bits := unrolled_cmd.bits /* //------------------------------------------------------------------------- // finish muxing control signals to rob (risc) or tiler (cisc) when (raw_cmd.valid && is_cisc_funct && !rob.io.busy) { is_cisc_mode := true.B raw_cisc_cmd.valid := true.B raw_cmd.ready := raw_cisc_cmd.ready } .elsewhen (raw_cmd.valid && !is_cisc_funct && !tiler.io.busy) { is_cisc_mode := false.B raw_risc_cmd.valid := true.B raw_cmd.ready := raw_risc_cmd.ready } */ //========================================================================= // Controllers //========================================================================= val load_controller = withClock (gated_clock) { Module(new LoadController(outer.config, coreMaxAddrBits, local_addr_t)) } val store_controller = withClock (gated_clock) { Module(new StoreController(outer.config, coreMaxAddrBits, local_addr_t)) } val ex_controller = withClock (gated_clock) { Module(new ExecuteController(xLen, tagWidth, outer.config)) } counters.io.event_io.collect(load_controller.io.counter) counters.io.event_io.collect(store_controller.io.counter) counters.io.event_io.collect(ex_controller.io.counter) /* tiler.io.issue.load.ready := false.B tiler.io.issue.store.ready := false.B tiler.io.issue.exec.ready := false.B */ reservation_station.io.issue.ld.ready := false.B reservation_station.io.issue.st.ready := false.B reservation_station.io.issue.ex.ready := false.B /* when (is_cisc_mode) { load_controller.io.cmd <> tiler.io.issue.load store_controller.io.cmd <> tiler.io.issue.store ex_controller.io.cmd <> tiler.io.issue.exec } .otherwise { load_controller.io.cmd.valid := rob.io.issue.ld.valid rob.io.issue.ld.ready := load_controller.io.cmd.ready load_controller.io.cmd.bits.cmd := rob.io.issue.ld.cmd load_controller.io.cmd.bits.cmd.inst.funct := rob.io.issue.ld.cmd.inst.funct load_controller.io.cmd.bits.rob_id.push(rob.io.issue.ld.rob_id) store_controller.io.cmd.valid := rob.io.issue.st.valid rob.io.issue.st.ready := store_controller.io.cmd.ready store_controller.io.cmd.bits.cmd := rob.io.issue.st.cmd store_controller.io.cmd.bits.cmd.inst.funct := rob.io.issue.st.cmd.inst.funct store_controller.io.cmd.bits.rob_id.push(rob.io.issue.st.rob_id) ex_controller.io.cmd.valid := rob.io.issue.ex.valid rob.io.issue.ex.ready := ex_controller.io.cmd.ready ex_controller.io.cmd.bits.cmd := rob.io.issue.ex.cmd ex_controller.io.cmd.bits.cmd.inst.funct := rob.io.issue.ex.cmd.inst.funct ex_controller.io.cmd.bits.rob_id.push(rob.io.issue.ex.rob_id) } */ load_controller.io.cmd.valid := reservation_station.io.issue.ld.valid reservation_station.io.issue.ld.ready := load_controller.io.cmd.ready load_controller.io.cmd.bits := reservation_station.io.issue.ld.cmd load_controller.io.cmd.bits.rob_id.push(reservation_station.io.issue.ld.rob_id) store_controller.io.cmd.valid := reservation_station.io.issue.st.valid reservation_station.io.issue.st.ready := store_controller.io.cmd.ready store_controller.io.cmd.bits := reservation_station.io.issue.st.cmd store_controller.io.cmd.bits.rob_id.push(reservation_station.io.issue.st.rob_id) ex_controller.io.cmd.valid := reservation_station.io.issue.ex.valid reservation_station.io.issue.ex.ready := ex_controller.io.cmd.ready ex_controller.io.cmd.bits := reservation_station.io.issue.ex.cmd ex_controller.io.cmd.bits.rob_id.push(reservation_station.io.issue.ex.rob_id) // Wire up scratchpad to controllers spad.module.io.dma.read <> load_controller.io.dma spad.module.io.dma.write <> store_controller.io.dma ex_controller.io.srams.read <> spad.module.io.srams.read ex_controller.io.srams.write <> spad.module.io.srams.write spad.module.io.acc.read_req <> ex_controller.io.acc.read_req ex_controller.io.acc.read_resp <> spad.module.io.acc.read_resp ex_controller.io.acc.write <> spad.module.io.acc.write // Im2Col unit val im2col = withClock (gated_clock) { Module(new Im2Col(outer.config)) } // Wire up Im2col counters.io.event_io.collect(im2col.io.counter) // im2col.io.sram_reads <> spad.module.io.srams.read im2col.io.req <> ex_controller.io.im2col.req ex_controller.io.im2col.resp <> im2col.io.resp // Wire arbiter for ExecuteController and Im2Col scratchpad reads (ex_controller.io.srams.read, im2col.io.sram_reads, spad.module.io.srams.read).zipped.foreach { case (ex_read, im2col_read, spad_read) => val req_arb = Module(new Arbiter(new ScratchpadReadReq(n=sp_bank_entries), 2)) req_arb.io.in(0) <> ex_read.req req_arb.io.in(1) <> im2col_read.req spad_read.req <> req_arb.io.out // TODO if necessary, change how the responses are handled when fromIm2Col is added to spad read interface ex_read.resp.valid := spad_read.resp.valid im2col_read.resp.valid := spad_read.resp.valid ex_read.resp.bits := spad_read.resp.bits im2col_read.resp.bits := spad_read.resp.bits spad_read.resp.ready := ex_read.resp.ready || im2col_read.resp.ready } // Wire up controllers to ROB reservation_station.io.alloc.valid := false.B // rob.io.alloc.bits := compressed_cmd.bits reservation_station.io.alloc.bits := unrolled_cmd.bits /* //========================================================================= // committed insn return path to frontends //========================================================================= //------------------------------------------------------------------------- // cisc tiler.io.completed.exec.valid := ex_controller.io.completed.valid tiler.io.completed.exec.bits := ex_controller.io.completed.bits tiler.io.completed.load <> load_controller.io.completed tiler.io.completed.store <> store_controller.io.completed // mux with cisc frontend arbiter tiler.io.completed.exec.valid := ex_controller.io.completed.valid && is_cisc_mode tiler.io.completed.load.valid := load_controller.io.completed.valid && is_cisc_mode tiler.io.completed.store.valid := store_controller.io.completed.valid && is_cisc_mode */ //------------------------------------------------------------------------- // risc val reservation_station_completed_arb = Module(new Arbiter(UInt(log2Up(reservation_station_entries).W), 3)) reservation_station_completed_arb.io.in(0).valid := ex_controller.io.completed.valid reservation_station_completed_arb.io.in(0).bits := ex_controller.io.completed.bits reservation_station_completed_arb.io.in(1) <> load_controller.io.completed reservation_station_completed_arb.io.in(2) <> store_controller.io.completed // mux with cisc frontend arbiter reservation_station_completed_arb.io.in(0).valid := ex_controller.io.completed.valid // && !is_cisc_mode reservation_station_completed_arb.io.in(1).valid := load_controller.io.completed.valid // && !is_cisc_mode reservation_station_completed_arb.io.in(2).valid := store_controller.io.completed.valid // && !is_cisc_mode reservation_station.io.completed.valid := reservation_station_completed_arb.io.out.valid reservation_station.io.completed.bits := reservation_station_completed_arb.io.out.bits reservation_station_completed_arb.io.out.ready := true.B // Wire up global RoCC signals io.busy := raw_cmd.valid || loop_conv_unroller_busy || loop_matmul_unroller_busy || reservation_station.io.busy || spad.module.io.busy || unrolled_cmd.valid || loop_cmd.valid || conv_cmd.valid io.interrupt := tlb.io.exp.map(_.interrupt).reduce(_ || _) // assert(!io.interrupt, "Interrupt handlers have not been written yet") // Cycle counters val incr_ld_cycles = load_controller.io.busy && !store_controller.io.busy && !ex_controller.io.busy val incr_st_cycles = !load_controller.io.busy && store_controller.io.busy && !ex_controller.io.busy val incr_ex_cycles = !load_controller.io.busy && !store_controller.io.busy && ex_controller.io.busy val incr_ld_st_cycles = load_controller.io.busy && store_controller.io.busy && !ex_controller.io.busy val incr_ld_ex_cycles = load_controller.io.busy && !store_controller.io.busy && ex_controller.io.busy val incr_st_ex_cycles = !load_controller.io.busy && store_controller.io.busy && ex_controller.io.busy val incr_ld_st_ex_cycles = load_controller.io.busy && store_controller.io.busy && ex_controller.io.busy counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_CYCLES, incr_ld_cycles) counters.io.event_io.connectEventSignal(CounterEvent.MAIN_ST_CYCLES, incr_st_cycles) counters.io.event_io.connectEventSignal(CounterEvent.MAIN_EX_CYCLES, incr_ex_cycles) counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_ST_CYCLES, incr_ld_st_cycles) counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_EX_CYCLES, incr_ld_ex_cycles) counters.io.event_io.connectEventSignal(CounterEvent.MAIN_ST_EX_CYCLES, incr_st_ex_cycles) counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_ST_EX_CYCLES, incr_ld_st_ex_cycles) // Issue commands to controllers // TODO we combinationally couple cmd.ready and cmd.valid signals here // when (compressed_cmd.valid) { when (unrolled_cmd.valid) { // val config_cmd_type = cmd.bits.rs1(1,0) // TODO magic numbers //val funct = unrolled_cmd.bits.inst.funct val risc_funct = unrolled_cmd.bits.cmd.inst.funct val is_flush = risc_funct === FLUSH_CMD val is_counter_op = risc_funct === COUNTER_OP val is_clock_gate_en = risc_funct === CLKGATE_EN /* val is_load = (funct === LOAD_CMD) || (funct === CONFIG_CMD && config_cmd_type === CONFIG_LOAD) val is_store = (funct === STORE_CMD) || (funct === CONFIG_CMD && config_cmd_type === CONFIG_STORE) val is_ex = (funct === COMPUTE_AND_FLIP_CMD || funct === COMPUTE_AND_STAY_CMD || funct === PRELOAD_CMD) || (funct === CONFIG_CMD && config_cmd_type === CONFIG_EX) */ when (is_flush) { val skip = unrolled_cmd.bits.cmd.rs1(0) tlb.io.exp.foreach(_.flush_skip := skip) tlb.io.exp.foreach(_.flush_retry := !skip) unrolled_cmd.ready := true.B // TODO should we wait for an acknowledgement from the TLB? } .elsewhen (is_counter_op) { // If this is a counter access/configuration command, execute immediately counters.io.in.valid := unrolled_cmd.valid unrolled_cmd.ready := counters.io.in.ready counters.io.in.bits := unrolled_cmd.bits.cmd } .elsewhen (is_clock_gate_en) { unrolled_cmd.ready := true.B } .otherwise { reservation_station.io.alloc.valid := true.B when(reservation_station.io.alloc.fire) { // compressed_cmd.ready := true.B unrolled_cmd.ready := true.B } } } // Debugging signals val pipeline_stall_counter = RegInit(0.U(32.W)) when (io.cmd.fire) { pipeline_stall_counter := 0.U }.elsewhen(io.busy) { pipeline_stall_counter := pipeline_stall_counter + 1.U } assert(pipeline_stall_counter < 10000000.U, "pipeline stall") /* //========================================================================= // Wire up global RoCC signals //========================================================================= io.busy := raw_cmd.valid || unrolled_cmd.valid || rob.io.busy || spad.module.io.busy || tiler.io.busy io.interrupt := tlb.io.exp.interrupt // hack when(is_cisc_mode || !(unrolled_cmd.valid || rob.io.busy || tiler.io.busy)){ tlb.io.exp.flush_retry := cmd_fsm.io.flush_retry tlb.io.exp.flush_skip := cmd_fsm.io.flush_skip } */ //========================================================================= // Performance Counters Access //========================================================================= }
module Gemmini( // @[Controller.scala:45:7] input clock, // @[Controller.scala:45:7] input reset, // @[Controller.scala:45:7] input auto_spad_id_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_spad_id_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_spad_id_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_spad_id_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_spad_id_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_spad_id_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_spad_id_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_spad_id_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_spad_id_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_spad_id_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_spad_id_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_spad_id_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_spad_id_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_spad_id_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_spad_id_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_spad_id_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_spad_id_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_spad_id_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_spad_id_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_spad_id_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_cmd_ready, // @[LazyRoCC.scala:78:14] input io_cmd_valid, // @[LazyRoCC.scala:78:14] input [6:0] io_cmd_bits_inst_funct, // @[LazyRoCC.scala:78:14] input [4:0] io_cmd_bits_inst_rs2, // @[LazyRoCC.scala:78:14] input [4:0] io_cmd_bits_inst_rs1, // @[LazyRoCC.scala:78:14] input io_cmd_bits_inst_xd, // @[LazyRoCC.scala:78:14] input io_cmd_bits_inst_xs1, // @[LazyRoCC.scala:78:14] input io_cmd_bits_inst_xs2, // @[LazyRoCC.scala:78:14] input [4:0] io_cmd_bits_inst_rd, // @[LazyRoCC.scala:78:14] input [6:0] io_cmd_bits_inst_opcode, // @[LazyRoCC.scala:78:14] input [63:0] io_cmd_bits_rs1, // @[LazyRoCC.scala:78:14] input [63:0] io_cmd_bits_rs2, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_debug, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_cease, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_wfi, // @[LazyRoCC.scala:78:14] input [31:0] io_cmd_bits_status_isa, // @[LazyRoCC.scala:78:14] input [1:0] io_cmd_bits_status_dprv, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_dv, // @[LazyRoCC.scala:78:14] input [1:0] io_cmd_bits_status_prv, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_v, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_sd, // @[LazyRoCC.scala:78:14] input [22:0] io_cmd_bits_status_zero2, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_mpv, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_gva, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_mbe, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_sbe, // @[LazyRoCC.scala:78:14] input [1:0] io_cmd_bits_status_sxl, // @[LazyRoCC.scala:78:14] input [1:0] io_cmd_bits_status_uxl, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_sd_rv32, // @[LazyRoCC.scala:78:14] input [7:0] io_cmd_bits_status_zero1, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_tsr, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_tw, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_tvm, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_mxr, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_sum, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_mprv, // @[LazyRoCC.scala:78:14] input [1:0] io_cmd_bits_status_xs, // @[LazyRoCC.scala:78:14] input [1:0] io_cmd_bits_status_fs, // @[LazyRoCC.scala:78:14] input [1:0] io_cmd_bits_status_mpp, // @[LazyRoCC.scala:78:14] input [1:0] io_cmd_bits_status_vs, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_spp, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_mpie, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_ube, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_spie, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_upie, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_mie, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_hie, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_sie, // @[LazyRoCC.scala:78:14] input io_cmd_bits_status_uie, // @[LazyRoCC.scala:78:14] input io_resp_ready, // @[LazyRoCC.scala:78:14] output io_resp_valid, // @[LazyRoCC.scala:78:14] output [4:0] io_resp_bits_rd, // @[LazyRoCC.scala:78:14] output [63:0] io_resp_bits_data, // @[LazyRoCC.scala:78:14] input io_mem_req_ready, // @[LazyRoCC.scala:78:14] input io_mem_resp_valid, // @[LazyRoCC.scala:78:14] input [39:0] io_mem_resp_bits_addr, // @[LazyRoCC.scala:78:14] input [7:0] io_mem_resp_bits_tag, // @[LazyRoCC.scala:78:14] input [4:0] io_mem_resp_bits_cmd, // @[LazyRoCC.scala:78:14] input [1:0] io_mem_resp_bits_size, // @[LazyRoCC.scala:78:14] input io_mem_resp_bits_signed, // @[LazyRoCC.scala:78:14] input [1:0] io_mem_resp_bits_dprv, // @[LazyRoCC.scala:78:14] input io_mem_resp_bits_dv, // @[LazyRoCC.scala:78:14] input [63:0] io_mem_resp_bits_data, // @[LazyRoCC.scala:78:14] input [7:0] io_mem_resp_bits_mask, // @[LazyRoCC.scala:78:14] input io_mem_resp_bits_replay, // @[LazyRoCC.scala:78:14] input io_mem_resp_bits_has_data, // @[LazyRoCC.scala:78:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[LazyRoCC.scala:78:14] input [63:0] io_mem_resp_bits_data_raw, // @[LazyRoCC.scala:78:14] input [63:0] io_mem_resp_bits_store_data, // @[LazyRoCC.scala:78:14] output io_busy, // @[LazyRoCC.scala:78:14] output io_interrupt, // @[LazyRoCC.scala:78:14] input io_exception, // @[LazyRoCC.scala:78:14] input io_ptw_0_req_ready, // @[LazyRoCC.scala:78:14] output io_ptw_0_req_valid, // @[LazyRoCC.scala:78:14] output [26:0] io_ptw_0_req_bits_bits_addr, // @[LazyRoCC.scala:78:14] output io_ptw_0_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_valid, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_ae_final, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_pf, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_gf, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_hr, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_hw, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_hx, // @[LazyRoCC.scala:78:14] input [9:0] io_ptw_0_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14] input [43:0] io_ptw_0_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_pte_d, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_pte_a, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_pte_g, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_pte_u, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_pte_x, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_pte_w, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_pte_r, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_pte_v, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_resp_bits_level, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14] input [38:0] io_ptw_0_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14] input io_ptw_0_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14] input [3:0] io_ptw_0_ptbr_mode, // @[LazyRoCC.scala:78:14] input [43:0] io_ptw_0_ptbr_ppn, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_debug, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_cease, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_wfi, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_status_isa, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_status_dprv, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_dv, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_status_prv, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_v, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_mpv, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_gva, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_tsr, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_tw, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_tvm, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_mxr, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_sum, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_mprv, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_status_fs, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_status_mpp, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_spp, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_mpie, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_spie, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_mie, // @[LazyRoCC.scala:78:14] input io_ptw_0_status_sie, // @[LazyRoCC.scala:78:14] input io_ptw_0_hstatus_spvp, // @[LazyRoCC.scala:78:14] input io_ptw_0_hstatus_spv, // @[LazyRoCC.scala:78:14] input io_ptw_0_hstatus_gva, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_debug, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_cease, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_wfi, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_gstatus_isa, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_gstatus_dprv, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_dv, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_gstatus_prv, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_v, // @[LazyRoCC.scala:78:14] input [22:0] io_ptw_0_gstatus_zero2, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_mpv, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_gva, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_mbe, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_sbe, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_gstatus_sxl, // @[LazyRoCC.scala:78:14] input [7:0] io_ptw_0_gstatus_zero1, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_tsr, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_tw, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_tvm, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_mxr, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_sum, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_mprv, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_gstatus_fs, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_gstatus_mpp, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_gstatus_vs, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_spp, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_mpie, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_ube, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_spie, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_upie, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_mie, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_hie, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_sie, // @[LazyRoCC.scala:78:14] input io_ptw_0_gstatus_uie, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14] input [29:0] io_ptw_0_pmp_0_addr, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_pmp_0_mask, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14] input [29:0] io_ptw_0_pmp_1_addr, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_pmp_1_mask, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14] input [29:0] io_ptw_0_pmp_2_addr, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_pmp_2_mask, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14] input [29:0] io_ptw_0_pmp_3_addr, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_pmp_3_mask, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14] input [29:0] io_ptw_0_pmp_4_addr, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_pmp_4_mask, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14] input [29:0] io_ptw_0_pmp_5_addr, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_pmp_5_mask, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14] input [29:0] io_ptw_0_pmp_6_addr, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_pmp_6_mask, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14] input [1:0] io_ptw_0_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14] input io_ptw_0_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14] input [29:0] io_ptw_0_pmp_7_addr, // @[LazyRoCC.scala:78:14] input [31:0] io_ptw_0_pmp_7_mask, // @[LazyRoCC.scala:78:14] input io_ptw_0_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14] input io_ptw_0_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14] input [63:0] io_ptw_0_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14] input [63:0] io_ptw_0_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14] input io_ptw_0_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14] input io_ptw_0_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14] input [63:0] io_ptw_0_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14] input [63:0] io_ptw_0_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14] input io_ptw_0_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14] input io_ptw_0_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14] input [63:0] io_ptw_0_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14] input [63:0] io_ptw_0_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14] input io_ptw_0_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14] input io_ptw_0_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14] input [63:0] io_ptw_0_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14] input [63:0] io_ptw_0_customCSRs_csrs_3_value // @[LazyRoCC.scala:78:14] ); wire tlb_io_exp_0_flush_retry; // @[Controller.scala:73:36, :358:29, :375:21, :378:40] wire tlb_io_exp_0_flush_skip; // @[Controller.scala:72:35, :358:29, :375:21, :377:39] wire _reservation_station_completed_arb_io_in_1_ready; // @[Controller.scala:312:49] wire _reservation_station_completed_arb_io_in_2_ready; // @[Controller.scala:312:49] wire _reservation_station_completed_arb_io_out_valid; // @[Controller.scala:312:49] wire [5:0] _reservation_station_completed_arb_io_out_bits; // @[Controller.scala:312:49] wire _req_arb_3_io_in_0_ready; // @[Controller.scala:268:25] wire _req_arb_3_io_in_1_ready; // @[Controller.scala:268:25] wire _req_arb_3_io_out_valid; // @[Controller.scala:268:25] wire [11:0] _req_arb_3_io_out_bits_addr; // @[Controller.scala:268:25] wire _req_arb_2_io_in_0_ready; // @[Controller.scala:268:25] wire _req_arb_2_io_in_1_ready; // @[Controller.scala:268:25] wire _req_arb_2_io_out_valid; // @[Controller.scala:268:25] wire [11:0] _req_arb_2_io_out_bits_addr; // @[Controller.scala:268:25] wire _req_arb_1_io_in_0_ready; // @[Controller.scala:268:25] wire _req_arb_1_io_in_1_ready; // @[Controller.scala:268:25] wire _req_arb_1_io_out_valid; // @[Controller.scala:268:25] wire [11:0] _req_arb_1_io_out_bits_addr; // @[Controller.scala:268:25] wire _req_arb_io_in_0_ready; // @[Controller.scala:268:25] wire _req_arb_io_in_1_ready; // @[Controller.scala:268:25] wire _req_arb_io_out_valid; // @[Controller.scala:268:25] wire [11:0] _req_arb_io_out_bits_addr; // @[Controller.scala:268:25] wire [7:0] _im2col_io_resp_bits_a_im2col_0; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_1; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_2; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_3; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_4; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_5; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_6; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_7; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_8; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_9; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_10; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_11; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_12; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_13; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_14; // @[Controller.scala:258:48] wire [7:0] _im2col_io_resp_bits_a_im2col_15; // @[Controller.scala:258:48] wire _im2col_io_resp_bits_im2col_end; // @[Controller.scala:258:48] wire [8:0] _im2col_io_resp_bits_im2col_turn; // @[Controller.scala:258:48] wire [6:0] _im2col_io_resp_bits_row_turn; // @[Controller.scala:258:48] wire [11:0] _im2col_io_sram_reads_0_req_bits_addr; // @[Controller.scala:258:48] wire [11:0] _im2col_io_sram_reads_1_req_bits_addr; // @[Controller.scala:258:48] wire [11:0] _im2col_io_sram_reads_2_req_bits_addr; // @[Controller.scala:258:48] wire [11:0] _im2col_io_sram_reads_3_req_bits_addr; // @[Controller.scala:258:48] wire _im2col_io_counter_event_signal_38; // @[Controller.scala:258:48] wire _im2col_io_counter_event_signal_39; // @[Controller.scala:258:48] wire _im2col_io_counter_event_signal_40; // @[Controller.scala:258:48] wire _ex_controller_io_cmd_ready; // @[Controller.scala:190:55] wire _ex_controller_io_im2col_req_bits_addr_is_acc_addr; // @[Controller.scala:190:55] wire _ex_controller_io_im2col_req_bits_addr_accumulate; // @[Controller.scala:190:55] wire _ex_controller_io_im2col_req_bits_addr_read_full_acc_row; // @[Controller.scala:190:55] wire [2:0] _ex_controller_io_im2col_req_bits_addr_norm_cmd; // @[Controller.scala:190:55] wire [10:0] _ex_controller_io_im2col_req_bits_addr_garbage; // @[Controller.scala:190:55] wire _ex_controller_io_im2col_req_bits_addr_garbage_bit; // @[Controller.scala:190:55] wire [13:0] _ex_controller_io_im2col_req_bits_addr_data; // @[Controller.scala:190:55] wire [7:0] _ex_controller_io_im2col_req_bits_ocol; // @[Controller.scala:190:55] wire [3:0] _ex_controller_io_im2col_req_bits_krow; // @[Controller.scala:190:55] wire [8:0] _ex_controller_io_im2col_req_bits_icol; // @[Controller.scala:190:55] wire [8:0] _ex_controller_io_im2col_req_bits_irow; // @[Controller.scala:190:55] wire [2:0] _ex_controller_io_im2col_req_bits_stride; // @[Controller.scala:190:55] wire [8:0] _ex_controller_io_im2col_req_bits_channel; // @[Controller.scala:190:55] wire [10:0] _ex_controller_io_im2col_req_bits_row_turn; // @[Controller.scala:190:55] wire [7:0] _ex_controller_io_im2col_req_bits_kdim2; // @[Controller.scala:190:55] wire [3:0] _ex_controller_io_im2col_req_bits_row_left; // @[Controller.scala:190:55] wire _ex_controller_io_im2col_req_bits_weight_double_bank; // @[Controller.scala:190:55] wire _ex_controller_io_im2col_req_bits_weight_triple_bank; // @[Controller.scala:190:55] wire _ex_controller_io_im2col_req_bits_start_inputting; // @[Controller.scala:190:55] wire _ex_controller_io_im2col_resp_ready; // @[Controller.scala:190:55] wire _ex_controller_io_srams_read_0_req_valid; // @[Controller.scala:190:55] wire [11:0] _ex_controller_io_srams_read_0_req_bits_addr; // @[Controller.scala:190:55] wire _ex_controller_io_srams_read_1_req_valid; // @[Controller.scala:190:55] wire [11:0] _ex_controller_io_srams_read_1_req_bits_addr; // @[Controller.scala:190:55] wire _ex_controller_io_srams_read_2_req_valid; // @[Controller.scala:190:55] wire [11:0] _ex_controller_io_srams_read_2_req_bits_addr; // @[Controller.scala:190:55] wire _ex_controller_io_srams_read_3_req_valid; // @[Controller.scala:190:55] wire [11:0] _ex_controller_io_srams_read_3_req_bits_addr; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_valid; // @[Controller.scala:190:55] wire [8:0] _ex_controller_io_acc_write_0_bits_addr; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_0_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_1_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_2_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_3_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_4_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_5_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_6_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_7_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_8_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_9_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_10_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_11_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_12_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_13_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_14_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_0_bits_data_15_0; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_acc; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_0; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_1; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_2; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_3; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_4; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_5; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_6; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_7; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_8; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_9; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_10; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_11; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_12; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_13; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_14; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_15; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_16; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_17; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_18; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_19; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_20; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_21; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_22; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_23; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_24; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_25; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_26; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_27; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_28; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_29; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_30; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_31; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_32; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_33; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_34; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_35; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_36; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_37; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_38; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_39; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_40; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_41; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_42; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_43; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_44; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_45; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_46; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_47; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_48; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_49; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_50; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_51; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_52; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_53; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_54; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_55; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_56; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_57; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_58; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_59; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_60; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_61; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_62; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_0_bits_mask_63; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_valid; // @[Controller.scala:190:55] wire [8:0] _ex_controller_io_acc_write_1_bits_addr; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_0_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_1_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_2_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_3_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_4_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_5_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_6_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_7_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_8_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_9_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_10_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_11_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_12_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_13_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_14_0; // @[Controller.scala:190:55] wire [31:0] _ex_controller_io_acc_write_1_bits_data_15_0; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_acc; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_0; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_1; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_2; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_3; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_4; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_5; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_6; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_7; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_8; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_9; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_10; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_11; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_12; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_13; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_14; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_15; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_16; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_17; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_18; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_19; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_20; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_21; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_22; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_23; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_24; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_25; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_26; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_27; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_28; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_29; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_30; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_31; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_32; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_33; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_34; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_35; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_36; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_37; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_38; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_39; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_40; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_41; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_42; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_43; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_44; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_45; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_46; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_47; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_48; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_49; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_50; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_51; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_52; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_53; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_54; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_55; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_56; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_57; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_58; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_59; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_60; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_61; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_62; // @[Controller.scala:190:55] wire _ex_controller_io_acc_write_1_bits_mask_63; // @[Controller.scala:190:55] wire _ex_controller_io_completed_valid; // @[Controller.scala:190:55] wire [5:0] _ex_controller_io_completed_bits; // @[Controller.scala:190:55] wire _ex_controller_io_busy; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_24; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_25; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_26; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_29; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_30; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_31; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_32; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_33; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_34; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_35; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_36; // @[Controller.scala:190:55] wire _ex_controller_io_counter_event_signal_37; // @[Controller.scala:190:55] wire _store_controller_io_cmd_ready; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_valid; // @[Controller.scala:189:58] wire [39:0] _store_controller_io_dma_req_bits_vaddr; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_laddr_is_acc_addr; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_laddr_accumulate; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_laddr_read_full_acc_row; // @[Controller.scala:189:58] wire [10:0] _store_controller_io_dma_req_bits_laddr_garbage; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_laddr_garbage_bit; // @[Controller.scala:189:58] wire [13:0] _store_controller_io_dma_req_bits_laddr_data; // @[Controller.scala:189:58] wire [2:0] _store_controller_io_dma_req_bits_acc_act; // @[Controller.scala:189:58] wire [31:0] _store_controller_io_dma_req_bits_acc_scale; // @[Controller.scala:189:58] wire [15:0] _store_controller_io_dma_req_bits_len; // @[Controller.scala:189:58] wire [7:0] _store_controller_io_dma_req_bits_block; // @[Controller.scala:189:58] wire [7:0] _store_controller_io_dma_req_bits_cmd_id; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_debug; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_cease; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_wfi; // @[Controller.scala:189:58] wire [31:0] _store_controller_io_dma_req_bits_status_isa; // @[Controller.scala:189:58] wire [1:0] _store_controller_io_dma_req_bits_status_dprv; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_dv; // @[Controller.scala:189:58] wire [1:0] _store_controller_io_dma_req_bits_status_prv; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_v; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_sd; // @[Controller.scala:189:58] wire [22:0] _store_controller_io_dma_req_bits_status_zero2; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_mpv; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_gva; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_mbe; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_sbe; // @[Controller.scala:189:58] wire [1:0] _store_controller_io_dma_req_bits_status_sxl; // @[Controller.scala:189:58] wire [1:0] _store_controller_io_dma_req_bits_status_uxl; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_sd_rv32; // @[Controller.scala:189:58] wire [7:0] _store_controller_io_dma_req_bits_status_zero1; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_tsr; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_tw; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_tvm; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_mxr; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_sum; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_mprv; // @[Controller.scala:189:58] wire [1:0] _store_controller_io_dma_req_bits_status_xs; // @[Controller.scala:189:58] wire [1:0] _store_controller_io_dma_req_bits_status_fs; // @[Controller.scala:189:58] wire [1:0] _store_controller_io_dma_req_bits_status_mpp; // @[Controller.scala:189:58] wire [1:0] _store_controller_io_dma_req_bits_status_vs; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_spp; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_mpie; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_ube; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_spie; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_upie; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_mie; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_hie; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_sie; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_status_uie; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_pool_en; // @[Controller.scala:189:58] wire _store_controller_io_dma_req_bits_store_en; // @[Controller.scala:189:58] wire _store_controller_io_completed_valid; // @[Controller.scala:189:58] wire [5:0] _store_controller_io_completed_bits; // @[Controller.scala:189:58] wire _store_controller_io_busy; // @[Controller.scala:189:58] wire _store_controller_io_counter_event_signal_11; // @[Controller.scala:189:58] wire _store_controller_io_counter_event_signal_12; // @[Controller.scala:189:58] wire _store_controller_io_counter_event_signal_13; // @[Controller.scala:189:58] wire _store_controller_io_counter_event_signal_14; // @[Controller.scala:189:58] wire _load_controller_io_cmd_ready; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_valid; // @[Controller.scala:188:57] wire [39:0] _load_controller_io_dma_req_bits_vaddr; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_laddr_is_acc_addr; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_laddr_accumulate; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_laddr_read_full_acc_row; // @[Controller.scala:188:57] wire [2:0] _load_controller_io_dma_req_bits_laddr_norm_cmd; // @[Controller.scala:188:57] wire [10:0] _load_controller_io_dma_req_bits_laddr_garbage; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_laddr_garbage_bit; // @[Controller.scala:188:57] wire [13:0] _load_controller_io_dma_req_bits_laddr_data; // @[Controller.scala:188:57] wire [15:0] _load_controller_io_dma_req_bits_cols; // @[Controller.scala:188:57] wire [15:0] _load_controller_io_dma_req_bits_repeats; // @[Controller.scala:188:57] wire [31:0] _load_controller_io_dma_req_bits_scale; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_has_acc_bitwidth; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_all_zeros; // @[Controller.scala:188:57] wire [15:0] _load_controller_io_dma_req_bits_block_stride; // @[Controller.scala:188:57] wire [7:0] _load_controller_io_dma_req_bits_pixel_repeats; // @[Controller.scala:188:57] wire [7:0] _load_controller_io_dma_req_bits_cmd_id; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_debug; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_cease; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_wfi; // @[Controller.scala:188:57] wire [31:0] _load_controller_io_dma_req_bits_status_isa; // @[Controller.scala:188:57] wire [1:0] _load_controller_io_dma_req_bits_status_dprv; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_dv; // @[Controller.scala:188:57] wire [1:0] _load_controller_io_dma_req_bits_status_prv; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_v; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_sd; // @[Controller.scala:188:57] wire [22:0] _load_controller_io_dma_req_bits_status_zero2; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_mpv; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_gva; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_mbe; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_sbe; // @[Controller.scala:188:57] wire [1:0] _load_controller_io_dma_req_bits_status_sxl; // @[Controller.scala:188:57] wire [1:0] _load_controller_io_dma_req_bits_status_uxl; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_sd_rv32; // @[Controller.scala:188:57] wire [7:0] _load_controller_io_dma_req_bits_status_zero1; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_tsr; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_tw; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_tvm; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_mxr; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_sum; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_mprv; // @[Controller.scala:188:57] wire [1:0] _load_controller_io_dma_req_bits_status_xs; // @[Controller.scala:188:57] wire [1:0] _load_controller_io_dma_req_bits_status_fs; // @[Controller.scala:188:57] wire [1:0] _load_controller_io_dma_req_bits_status_mpp; // @[Controller.scala:188:57] wire [1:0] _load_controller_io_dma_req_bits_status_vs; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_spp; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_mpie; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_ube; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_spie; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_upie; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_mie; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_hie; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_sie; // @[Controller.scala:188:57] wire _load_controller_io_dma_req_bits_status_uie; // @[Controller.scala:188:57] wire _load_controller_io_completed_valid; // @[Controller.scala:188:57] wire [5:0] _load_controller_io_completed_bits; // @[Controller.scala:188:57] wire _load_controller_io_busy; // @[Controller.scala:188:57] wire _load_controller_io_counter_event_signal_8; // @[Controller.scala:188:57] wire _load_controller_io_counter_event_signal_9; // @[Controller.scala:188:57] wire _load_controller_io_counter_event_signal_10; // @[Controller.scala:188:57] wire _unrolled_cmd_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [6:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_funct; // @[Decoupled.scala:362:21] wire [4:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_rs2; // @[Decoupled.scala:362:21] wire [4:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_rs1; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_inst_xd; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_inst_xs1; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_inst_xs2; // @[Decoupled.scala:362:21] wire [4:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_rd; // @[Decoupled.scala:362:21] wire [6:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_opcode; // @[Decoupled.scala:362:21] wire [63:0] _unrolled_cmd_q_io_deq_bits_cmd_rs1; // @[Decoupled.scala:362:21] wire [63:0] _unrolled_cmd_q_io_deq_bits_cmd_rs2; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_debug; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_cease; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_wfi; // @[Decoupled.scala:362:21] wire [31:0] _unrolled_cmd_q_io_deq_bits_cmd_status_isa; // @[Decoupled.scala:362:21] wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_dprv; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_dv; // @[Decoupled.scala:362:21] wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_prv; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_v; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_sd; // @[Decoupled.scala:362:21] wire [22:0] _unrolled_cmd_q_io_deq_bits_cmd_status_zero2; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_mpv; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_gva; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_mbe; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_sbe; // @[Decoupled.scala:362:21] wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_sxl; // @[Decoupled.scala:362:21] wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_uxl; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_sd_rv32; // @[Decoupled.scala:362:21] wire [7:0] _unrolled_cmd_q_io_deq_bits_cmd_status_zero1; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_tsr; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_tw; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_tvm; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_mxr; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_sum; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_mprv; // @[Decoupled.scala:362:21] wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_xs; // @[Decoupled.scala:362:21] wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_fs; // @[Decoupled.scala:362:21] wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_mpp; // @[Decoupled.scala:362:21] wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_vs; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_spp; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_mpie; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_ube; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_spie; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_upie; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_mie; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_hie; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_sie; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_cmd_status_uie; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_rob_id_valid; // @[Decoupled.scala:362:21] wire [5:0] _unrolled_cmd_q_io_deq_bits_rob_id_bits; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_from_matmul_fsm; // @[Decoupled.scala:362:21] wire _unrolled_cmd_q_io_deq_bits_from_conv_fsm; // @[Decoupled.scala:362:21] wire _mod_1_io_in_ready; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_valid; // @[LoopMatmul.scala:1127:21] wire [6:0] _mod_1_io_out_bits_cmd_inst_funct; // @[LoopMatmul.scala:1127:21] wire [4:0] _mod_1_io_out_bits_cmd_inst_rs2; // @[LoopMatmul.scala:1127:21] wire [4:0] _mod_1_io_out_bits_cmd_inst_rs1; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_inst_xd; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_inst_xs1; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_inst_xs2; // @[LoopMatmul.scala:1127:21] wire [4:0] _mod_1_io_out_bits_cmd_inst_rd; // @[LoopMatmul.scala:1127:21] wire [6:0] _mod_1_io_out_bits_cmd_inst_opcode; // @[LoopMatmul.scala:1127:21] wire [63:0] _mod_1_io_out_bits_cmd_rs1; // @[LoopMatmul.scala:1127:21] wire [63:0] _mod_1_io_out_bits_cmd_rs2; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_debug; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_cease; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_wfi; // @[LoopMatmul.scala:1127:21] wire [31:0] _mod_1_io_out_bits_cmd_status_isa; // @[LoopMatmul.scala:1127:21] wire [1:0] _mod_1_io_out_bits_cmd_status_dprv; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_dv; // @[LoopMatmul.scala:1127:21] wire [1:0] _mod_1_io_out_bits_cmd_status_prv; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_v; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_sd; // @[LoopMatmul.scala:1127:21] wire [22:0] _mod_1_io_out_bits_cmd_status_zero2; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_mpv; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_gva; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_mbe; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_sbe; // @[LoopMatmul.scala:1127:21] wire [1:0] _mod_1_io_out_bits_cmd_status_sxl; // @[LoopMatmul.scala:1127:21] wire [1:0] _mod_1_io_out_bits_cmd_status_uxl; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_sd_rv32; // @[LoopMatmul.scala:1127:21] wire [7:0] _mod_1_io_out_bits_cmd_status_zero1; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_tsr; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_tw; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_tvm; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_mxr; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_sum; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_mprv; // @[LoopMatmul.scala:1127:21] wire [1:0] _mod_1_io_out_bits_cmd_status_xs; // @[LoopMatmul.scala:1127:21] wire [1:0] _mod_1_io_out_bits_cmd_status_fs; // @[LoopMatmul.scala:1127:21] wire [1:0] _mod_1_io_out_bits_cmd_status_mpp; // @[LoopMatmul.scala:1127:21] wire [1:0] _mod_1_io_out_bits_cmd_status_vs; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_spp; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_mpie; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_ube; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_spie; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_upie; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_mie; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_hie; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_sie; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_cmd_status_uie; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_from_matmul_fsm; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_out_bits_from_conv_fsm; // @[LoopMatmul.scala:1127:21] wire _mod_1_io_busy; // @[LoopMatmul.scala:1127:21] wire _mod_io_in_ready; // @[LoopConv.scala:1542:21] wire _mod_io_out_valid; // @[LoopConv.scala:1542:21] wire [6:0] _mod_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:1542:21] wire [4:0] _mod_io_out_bits_cmd_inst_rs2; // @[LoopConv.scala:1542:21] wire [4:0] _mod_io_out_bits_cmd_inst_rs1; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_inst_xd; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_inst_xs1; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_inst_xs2; // @[LoopConv.scala:1542:21] wire [4:0] _mod_io_out_bits_cmd_inst_rd; // @[LoopConv.scala:1542:21] wire [6:0] _mod_io_out_bits_cmd_inst_opcode; // @[LoopConv.scala:1542:21] wire [63:0] _mod_io_out_bits_cmd_rs1; // @[LoopConv.scala:1542:21] wire [63:0] _mod_io_out_bits_cmd_rs2; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_debug; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_cease; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_wfi; // @[LoopConv.scala:1542:21] wire [31:0] _mod_io_out_bits_cmd_status_isa; // @[LoopConv.scala:1542:21] wire [1:0] _mod_io_out_bits_cmd_status_dprv; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_dv; // @[LoopConv.scala:1542:21] wire [1:0] _mod_io_out_bits_cmd_status_prv; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_v; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_sd; // @[LoopConv.scala:1542:21] wire [22:0] _mod_io_out_bits_cmd_status_zero2; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_mpv; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_gva; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_mbe; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_sbe; // @[LoopConv.scala:1542:21] wire [1:0] _mod_io_out_bits_cmd_status_sxl; // @[LoopConv.scala:1542:21] wire [1:0] _mod_io_out_bits_cmd_status_uxl; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_sd_rv32; // @[LoopConv.scala:1542:21] wire [7:0] _mod_io_out_bits_cmd_status_zero1; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_tsr; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_tw; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_tvm; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_mxr; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_sum; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_mprv; // @[LoopConv.scala:1542:21] wire [1:0] _mod_io_out_bits_cmd_status_xs; // @[LoopConv.scala:1542:21] wire [1:0] _mod_io_out_bits_cmd_status_fs; // @[LoopConv.scala:1542:21] wire [1:0] _mod_io_out_bits_cmd_status_mpp; // @[LoopConv.scala:1542:21] wire [1:0] _mod_io_out_bits_cmd_status_vs; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_spp; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_mpie; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_ube; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_spie; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_upie; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_mie; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_hie; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_sie; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_cmd_status_uie; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_from_matmul_fsm; // @[LoopConv.scala:1542:21] wire _mod_io_out_bits_from_conv_fsm; // @[LoopConv.scala:1542:21] wire _mod_io_busy; // @[LoopConv.scala:1542:21] wire _raw_cmd_q_io_deq_valid; // @[Controller.scala:131:25] wire [6:0] _raw_cmd_q_io_deq_bits_cmd_inst_funct; // @[Controller.scala:131:25] wire [4:0] _raw_cmd_q_io_deq_bits_cmd_inst_rs2; // @[Controller.scala:131:25] wire [4:0] _raw_cmd_q_io_deq_bits_cmd_inst_rs1; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_inst_xd; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_inst_xs1; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_inst_xs2; // @[Controller.scala:131:25] wire [4:0] _raw_cmd_q_io_deq_bits_cmd_inst_rd; // @[Controller.scala:131:25] wire [6:0] _raw_cmd_q_io_deq_bits_cmd_inst_opcode; // @[Controller.scala:131:25] wire [63:0] _raw_cmd_q_io_deq_bits_cmd_rs1; // @[Controller.scala:131:25] wire [63:0] _raw_cmd_q_io_deq_bits_cmd_rs2; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_debug; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_cease; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_wfi; // @[Controller.scala:131:25] wire [31:0] _raw_cmd_q_io_deq_bits_cmd_status_isa; // @[Controller.scala:131:25] wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_dprv; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_dv; // @[Controller.scala:131:25] wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_prv; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_v; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_sd; // @[Controller.scala:131:25] wire [22:0] _raw_cmd_q_io_deq_bits_cmd_status_zero2; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_mpv; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_gva; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_mbe; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_sbe; // @[Controller.scala:131:25] wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_sxl; // @[Controller.scala:131:25] wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_uxl; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_sd_rv32; // @[Controller.scala:131:25] wire [7:0] _raw_cmd_q_io_deq_bits_cmd_status_zero1; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_tsr; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_tw; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_tvm; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_mxr; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_sum; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_mprv; // @[Controller.scala:131:25] wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_xs; // @[Controller.scala:131:25] wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_fs; // @[Controller.scala:131:25] wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_mpp; // @[Controller.scala:131:25] wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_vs; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_spp; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_mpie; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_ube; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_spie; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_upie; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_mie; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_hie; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_sie; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_cmd_status_uie; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_rob_id_valid; // @[Controller.scala:131:25] wire [5:0] _raw_cmd_q_io_deq_bits_rob_id_bits; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_from_matmul_fsm; // @[Controller.scala:131:25] wire _raw_cmd_q_io_deq_bits_from_conv_fsm; // @[Controller.scala:131:25] wire _reservation_station_io_alloc_ready; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_valid; // @[Controller.scala:124:61] wire [6:0] _reservation_station_io_issue_ld_cmd_cmd_inst_funct; // @[Controller.scala:124:61] wire [4:0] _reservation_station_io_issue_ld_cmd_cmd_inst_rs2; // @[Controller.scala:124:61] wire [4:0] _reservation_station_io_issue_ld_cmd_cmd_inst_rs1; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_inst_xd; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_inst_xs1; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_inst_xs2; // @[Controller.scala:124:61] wire [4:0] _reservation_station_io_issue_ld_cmd_cmd_inst_rd; // @[Controller.scala:124:61] wire [6:0] _reservation_station_io_issue_ld_cmd_cmd_inst_opcode; // @[Controller.scala:124:61] wire [63:0] _reservation_station_io_issue_ld_cmd_cmd_rs1; // @[Controller.scala:124:61] wire [63:0] _reservation_station_io_issue_ld_cmd_cmd_rs2; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_debug; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_cease; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_wfi; // @[Controller.scala:124:61] wire [31:0] _reservation_station_io_issue_ld_cmd_cmd_status_isa; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_dprv; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_dv; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_prv; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_v; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_sd; // @[Controller.scala:124:61] wire [22:0] _reservation_station_io_issue_ld_cmd_cmd_status_zero2; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_mpv; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_gva; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_mbe; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_sbe; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_sxl; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_uxl; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_sd_rv32; // @[Controller.scala:124:61] wire [7:0] _reservation_station_io_issue_ld_cmd_cmd_status_zero1; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_tsr; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_tw; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_tvm; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_mxr; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_sum; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_mprv; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_xs; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_fs; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_mpp; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_vs; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_spp; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_mpie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_ube; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_spie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_upie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_mie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_hie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_sie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_cmd_status_uie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_from_matmul_fsm; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ld_cmd_from_conv_fsm; // @[Controller.scala:124:61] wire [5:0] _reservation_station_io_issue_ld_rob_id; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_valid; // @[Controller.scala:124:61] wire [6:0] _reservation_station_io_issue_st_cmd_cmd_inst_funct; // @[Controller.scala:124:61] wire [4:0] _reservation_station_io_issue_st_cmd_cmd_inst_rs2; // @[Controller.scala:124:61] wire [4:0] _reservation_station_io_issue_st_cmd_cmd_inst_rs1; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_inst_xd; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_inst_xs1; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_inst_xs2; // @[Controller.scala:124:61] wire [4:0] _reservation_station_io_issue_st_cmd_cmd_inst_rd; // @[Controller.scala:124:61] wire [6:0] _reservation_station_io_issue_st_cmd_cmd_inst_opcode; // @[Controller.scala:124:61] wire [63:0] _reservation_station_io_issue_st_cmd_cmd_rs1; // @[Controller.scala:124:61] wire [63:0] _reservation_station_io_issue_st_cmd_cmd_rs2; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_debug; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_cease; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_wfi; // @[Controller.scala:124:61] wire [31:0] _reservation_station_io_issue_st_cmd_cmd_status_isa; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_dprv; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_dv; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_prv; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_v; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_sd; // @[Controller.scala:124:61] wire [22:0] _reservation_station_io_issue_st_cmd_cmd_status_zero2; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_mpv; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_gva; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_mbe; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_sbe; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_sxl; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_uxl; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_sd_rv32; // @[Controller.scala:124:61] wire [7:0] _reservation_station_io_issue_st_cmd_cmd_status_zero1; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_tsr; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_tw; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_tvm; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_mxr; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_sum; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_mprv; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_xs; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_fs; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_mpp; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_vs; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_spp; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_mpie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_ube; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_spie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_upie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_mie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_hie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_sie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_cmd_status_uie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_from_matmul_fsm; // @[Controller.scala:124:61] wire _reservation_station_io_issue_st_cmd_from_conv_fsm; // @[Controller.scala:124:61] wire [5:0] _reservation_station_io_issue_st_rob_id; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_valid; // @[Controller.scala:124:61] wire [6:0] _reservation_station_io_issue_ex_cmd_cmd_inst_funct; // @[Controller.scala:124:61] wire [4:0] _reservation_station_io_issue_ex_cmd_cmd_inst_rs2; // @[Controller.scala:124:61] wire [4:0] _reservation_station_io_issue_ex_cmd_cmd_inst_rs1; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_inst_xd; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_inst_xs1; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_inst_xs2; // @[Controller.scala:124:61] wire [4:0] _reservation_station_io_issue_ex_cmd_cmd_inst_rd; // @[Controller.scala:124:61] wire [6:0] _reservation_station_io_issue_ex_cmd_cmd_inst_opcode; // @[Controller.scala:124:61] wire [63:0] _reservation_station_io_issue_ex_cmd_cmd_rs1; // @[Controller.scala:124:61] wire [63:0] _reservation_station_io_issue_ex_cmd_cmd_rs2; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_debug; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_cease; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_wfi; // @[Controller.scala:124:61] wire [31:0] _reservation_station_io_issue_ex_cmd_cmd_status_isa; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_dprv; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_dv; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_prv; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_v; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_sd; // @[Controller.scala:124:61] wire [22:0] _reservation_station_io_issue_ex_cmd_cmd_status_zero2; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_mpv; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_gva; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_mbe; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_sbe; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_sxl; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_uxl; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_sd_rv32; // @[Controller.scala:124:61] wire [7:0] _reservation_station_io_issue_ex_cmd_cmd_status_zero1; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_tsr; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_tw; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_tvm; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_mxr; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_sum; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_mprv; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_xs; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_fs; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_mpp; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_vs; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_spp; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_mpie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_ube; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_spie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_upie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_mie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_hie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_sie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_cmd_status_uie; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_from_matmul_fsm; // @[Controller.scala:124:61] wire _reservation_station_io_issue_ex_cmd_from_conv_fsm; // @[Controller.scala:124:61] wire [5:0] _reservation_station_io_issue_ex_rob_id; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_conv_ld_completed; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_conv_ex_completed; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_conv_st_completed; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_matmul_ld_completed; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_matmul_ex_completed; // @[Controller.scala:124:61] wire [1:0] _reservation_station_io_matmul_st_completed; // @[Controller.scala:124:61] wire _reservation_station_io_busy; // @[Controller.scala:124:61] wire _reservation_station_io_counter_event_signal_41; // @[Controller.scala:124:61] wire _reservation_station_io_counter_event_signal_42; // @[Controller.scala:124:61] wire [31:0] _reservation_station_io_counter_external_values_1; // @[Controller.scala:124:61] wire [31:0] _reservation_station_io_counter_external_values_2; // @[Controller.scala:124:61] wire [31:0] _reservation_station_io_counter_external_values_3; // @[Controller.scala:124:61] wire _tlb_io_clients_0_resp_miss; // @[Controller.scala:69:19] wire [31:0] _tlb_io_clients_0_resp_paddr; // @[Controller.scala:69:19] wire [39:0] _tlb_io_clients_0_resp_gpa; // @[Controller.scala:69:19] wire _tlb_io_clients_0_resp_pf_ld; // @[Controller.scala:69:19] wire _tlb_io_clients_0_resp_pf_st; // @[Controller.scala:69:19] wire _tlb_io_clients_0_resp_pf_inst; // @[Controller.scala:69:19] wire _tlb_io_clients_0_resp_ae_ld; // @[Controller.scala:69:19] wire _tlb_io_clients_0_resp_ae_st; // @[Controller.scala:69:19] wire _tlb_io_clients_0_resp_ae_inst; // @[Controller.scala:69:19] wire _tlb_io_clients_0_resp_cacheable; // @[Controller.scala:69:19] wire _tlb_io_clients_0_resp_must_alloc; // @[Controller.scala:69:19] wire _tlb_io_clients_0_resp_prefetchable; // @[Controller.scala:69:19] wire [4:0] _tlb_io_clients_0_resp_cmd; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_miss; // @[Controller.scala:69:19] wire [31:0] _tlb_io_clients_1_resp_paddr; // @[Controller.scala:69:19] wire [39:0] _tlb_io_clients_1_resp_gpa; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_pf_ld; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_pf_st; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_pf_inst; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_ae_ld; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_ae_st; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_ae_inst; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_cacheable; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_must_alloc; // @[Controller.scala:69:19] wire _tlb_io_clients_1_resp_prefetchable; // @[Controller.scala:69:19] wire [4:0] _tlb_io_clients_1_resp_cmd; // @[Controller.scala:69:19] wire _tlb_io_counter_event_signal_15; // @[Controller.scala:69:19] wire _tlb_io_counter_event_signal_16; // @[Controller.scala:69:19] wire _tlb_io_counter_event_signal_17; // @[Controller.scala:69:19] wire _counters_io_in_ready; // @[Controller.scala:59:24] wire _counters_io_event_io_external_reset; // @[Controller.scala:59:24] wire _spad_io_dma_read_req_ready; // @[Controller.scala:36:24] wire _spad_io_dma_read_resp_valid; // @[Controller.scala:36:24] wire [15:0] _spad_io_dma_read_resp_bits_bytesRead; // @[Controller.scala:36:24] wire [7:0] _spad_io_dma_read_resp_bits_cmd_id; // @[Controller.scala:36:24] wire _spad_io_dma_write_req_ready; // @[Controller.scala:36:24] wire _spad_io_dma_write_resp_valid; // @[Controller.scala:36:24] wire [7:0] _spad_io_dma_write_resp_bits_cmd_id; // @[Controller.scala:36:24] wire _spad_io_srams_read_0_req_ready; // @[Controller.scala:36:24] wire _spad_io_srams_read_0_resp_valid; // @[Controller.scala:36:24] wire [127:0] _spad_io_srams_read_0_resp_bits_data; // @[Controller.scala:36:24] wire _spad_io_srams_read_0_resp_bits_fromDMA; // @[Controller.scala:36:24] wire _spad_io_srams_read_1_req_ready; // @[Controller.scala:36:24] wire _spad_io_srams_read_1_resp_valid; // @[Controller.scala:36:24] wire [127:0] _spad_io_srams_read_1_resp_bits_data; // @[Controller.scala:36:24] wire _spad_io_srams_read_1_resp_bits_fromDMA; // @[Controller.scala:36:24] wire _spad_io_srams_read_2_req_ready; // @[Controller.scala:36:24] wire _spad_io_srams_read_2_resp_valid; // @[Controller.scala:36:24] wire [127:0] _spad_io_srams_read_2_resp_bits_data; // @[Controller.scala:36:24] wire _spad_io_srams_read_2_resp_bits_fromDMA; // @[Controller.scala:36:24] wire _spad_io_srams_read_3_req_ready; // @[Controller.scala:36:24] wire _spad_io_srams_read_3_resp_valid; // @[Controller.scala:36:24] wire [127:0] _spad_io_srams_read_3_resp_bits_data; // @[Controller.scala:36:24] wire _spad_io_srams_read_3_resp_bits_fromDMA; // @[Controller.scala:36:24] wire _spad_io_acc_read_req_0_ready; // @[Controller.scala:36:24] wire _spad_io_acc_read_req_1_ready; // @[Controller.scala:36:24] wire _spad_io_acc_read_resp_0_valid; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_0_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_1_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_2_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_3_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_4_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_5_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_6_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_7_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_8_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_9_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_10_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_11_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_12_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_13_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_14_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_0_bits_data_15_0; // @[Controller.scala:36:24] wire [1:0] _spad_io_acc_read_resp_0_bits_acc_bank_id; // @[Controller.scala:36:24] wire _spad_io_acc_read_resp_0_bits_fromDMA; // @[Controller.scala:36:24] wire _spad_io_acc_read_resp_1_valid; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_0_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_1_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_2_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_3_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_4_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_5_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_6_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_7_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_8_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_9_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_10_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_11_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_12_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_13_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_14_0; // @[Controller.scala:36:24] wire [31:0] _spad_io_acc_read_resp_1_bits_data_15_0; // @[Controller.scala:36:24] wire [1:0] _spad_io_acc_read_resp_1_bits_acc_bank_id; // @[Controller.scala:36:24] wire _spad_io_acc_read_resp_1_bits_fromDMA; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_valid; // @[Controller.scala:36:24] wire [39:0] _spad_io_tlb_0_req_bits_tlb_req_vaddr; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_debug; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_cease; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_wfi; // @[Controller.scala:36:24] wire [31:0] _spad_io_tlb_0_req_bits_status_isa; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_0_req_bits_status_dprv; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_dv; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_0_req_bits_status_prv; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_v; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_sd; // @[Controller.scala:36:24] wire [22:0] _spad_io_tlb_0_req_bits_status_zero2; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_mpv; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_gva; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_mbe; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_sbe; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_0_req_bits_status_sxl; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_0_req_bits_status_uxl; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_sd_rv32; // @[Controller.scala:36:24] wire [7:0] _spad_io_tlb_0_req_bits_status_zero1; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_tsr; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_tw; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_tvm; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_mxr; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_sum; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_mprv; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_0_req_bits_status_xs; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_0_req_bits_status_fs; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_0_req_bits_status_mpp; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_0_req_bits_status_vs; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_spp; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_mpie; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_ube; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_spie; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_upie; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_mie; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_hie; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_sie; // @[Controller.scala:36:24] wire _spad_io_tlb_0_req_bits_status_uie; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_valid; // @[Controller.scala:36:24] wire [39:0] _spad_io_tlb_1_req_bits_tlb_req_vaddr; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_debug; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_cease; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_wfi; // @[Controller.scala:36:24] wire [31:0] _spad_io_tlb_1_req_bits_status_isa; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_1_req_bits_status_dprv; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_dv; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_1_req_bits_status_prv; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_v; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_sd; // @[Controller.scala:36:24] wire [22:0] _spad_io_tlb_1_req_bits_status_zero2; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_mpv; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_gva; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_mbe; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_sbe; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_1_req_bits_status_sxl; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_1_req_bits_status_uxl; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_sd_rv32; // @[Controller.scala:36:24] wire [7:0] _spad_io_tlb_1_req_bits_status_zero1; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_tsr; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_tw; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_tvm; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_mxr; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_sum; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_mprv; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_1_req_bits_status_xs; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_1_req_bits_status_fs; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_1_req_bits_status_mpp; // @[Controller.scala:36:24] wire [1:0] _spad_io_tlb_1_req_bits_status_vs; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_spp; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_mpie; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_ube; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_spie; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_upie; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_mie; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_hie; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_sie; // @[Controller.scala:36:24] wire _spad_io_tlb_1_req_bits_status_uie; // @[Controller.scala:36:24] wire _spad_io_busy; // @[Controller.scala:36:24] wire _spad_io_counter_event_signal_18; // @[Controller.scala:36:24] wire _spad_io_counter_event_signal_19; // @[Controller.scala:36:24] wire _spad_io_counter_event_signal_20; // @[Controller.scala:36:24] wire _spad_io_counter_event_signal_21; // @[Controller.scala:36:24] wire _spad_io_counter_event_signal_22; // @[Controller.scala:36:24] wire _spad_io_counter_event_signal_23; // @[Controller.scala:36:24] wire [31:0] _spad_io_counter_external_values_4; // @[Controller.scala:36:24] wire [31:0] _spad_io_counter_external_values_5; // @[Controller.scala:36:24] wire [31:0] _spad_io_counter_external_values_6; // @[Controller.scala:36:24] wire [31:0] _spad_io_counter_external_values_7; // @[Controller.scala:36:24] wire auto_spad_id_out_a_ready_0 = auto_spad_id_out_a_ready; // @[Controller.scala:45:7] wire auto_spad_id_out_d_valid_0 = auto_spad_id_out_d_valid; // @[Controller.scala:45:7] wire [2:0] auto_spad_id_out_d_bits_opcode_0 = auto_spad_id_out_d_bits_opcode; // @[Controller.scala:45:7] wire [1:0] auto_spad_id_out_d_bits_param_0 = auto_spad_id_out_d_bits_param; // @[Controller.scala:45:7] wire [3:0] auto_spad_id_out_d_bits_size_0 = auto_spad_id_out_d_bits_size; // @[Controller.scala:45:7] wire [6:0] auto_spad_id_out_d_bits_source_0 = auto_spad_id_out_d_bits_source; // @[Controller.scala:45:7] wire [3:0] auto_spad_id_out_d_bits_sink_0 = auto_spad_id_out_d_bits_sink; // @[Controller.scala:45:7] wire auto_spad_id_out_d_bits_denied_0 = auto_spad_id_out_d_bits_denied; // @[Controller.scala:45:7] wire [127:0] auto_spad_id_out_d_bits_data_0 = auto_spad_id_out_d_bits_data; // @[Controller.scala:45:7] wire auto_spad_id_out_d_bits_corrupt_0 = auto_spad_id_out_d_bits_corrupt; // @[Controller.scala:45:7] wire io_cmd_valid_0 = io_cmd_valid; // @[Controller.scala:45:7] wire [6:0] io_cmd_bits_inst_funct_0 = io_cmd_bits_inst_funct; // @[Controller.scala:45:7] wire [4:0] io_cmd_bits_inst_rs2_0 = io_cmd_bits_inst_rs2; // @[Controller.scala:45:7] wire [4:0] io_cmd_bits_inst_rs1_0 = io_cmd_bits_inst_rs1; // @[Controller.scala:45:7] wire io_cmd_bits_inst_xd_0 = io_cmd_bits_inst_xd; // @[Controller.scala:45:7] wire io_cmd_bits_inst_xs1_0 = io_cmd_bits_inst_xs1; // @[Controller.scala:45:7] wire io_cmd_bits_inst_xs2_0 = io_cmd_bits_inst_xs2; // @[Controller.scala:45:7] wire [4:0] io_cmd_bits_inst_rd_0 = io_cmd_bits_inst_rd; // @[Controller.scala:45:7] wire [6:0] io_cmd_bits_inst_opcode_0 = io_cmd_bits_inst_opcode; // @[Controller.scala:45:7] wire [63:0] io_cmd_bits_rs1_0 = io_cmd_bits_rs1; // @[Controller.scala:45:7] wire [63:0] io_cmd_bits_rs2_0 = io_cmd_bits_rs2; // @[Controller.scala:45:7] wire io_cmd_bits_status_debug_0 = io_cmd_bits_status_debug; // @[Controller.scala:45:7] wire io_cmd_bits_status_cease_0 = io_cmd_bits_status_cease; // @[Controller.scala:45:7] wire io_cmd_bits_status_wfi_0 = io_cmd_bits_status_wfi; // @[Controller.scala:45:7] wire [31:0] io_cmd_bits_status_isa_0 = io_cmd_bits_status_isa; // @[Controller.scala:45:7] wire [1:0] io_cmd_bits_status_dprv_0 = io_cmd_bits_status_dprv; // @[Controller.scala:45:7] wire io_cmd_bits_status_dv_0 = io_cmd_bits_status_dv; // @[Controller.scala:45:7] wire [1:0] io_cmd_bits_status_prv_0 = io_cmd_bits_status_prv; // @[Controller.scala:45:7] wire io_cmd_bits_status_v_0 = io_cmd_bits_status_v; // @[Controller.scala:45:7] wire io_cmd_bits_status_sd_0 = io_cmd_bits_status_sd; // @[Controller.scala:45:7] wire [22:0] io_cmd_bits_status_zero2_0 = io_cmd_bits_status_zero2; // @[Controller.scala:45:7] wire io_cmd_bits_status_mpv_0 = io_cmd_bits_status_mpv; // @[Controller.scala:45:7] wire io_cmd_bits_status_gva_0 = io_cmd_bits_status_gva; // @[Controller.scala:45:7] wire io_cmd_bits_status_mbe_0 = io_cmd_bits_status_mbe; // @[Controller.scala:45:7] wire io_cmd_bits_status_sbe_0 = io_cmd_bits_status_sbe; // @[Controller.scala:45:7] wire [1:0] io_cmd_bits_status_sxl_0 = io_cmd_bits_status_sxl; // @[Controller.scala:45:7] wire [1:0] io_cmd_bits_status_uxl_0 = io_cmd_bits_status_uxl; // @[Controller.scala:45:7] wire io_cmd_bits_status_sd_rv32_0 = io_cmd_bits_status_sd_rv32; // @[Controller.scala:45:7] wire [7:0] io_cmd_bits_status_zero1_0 = io_cmd_bits_status_zero1; // @[Controller.scala:45:7] wire io_cmd_bits_status_tsr_0 = io_cmd_bits_status_tsr; // @[Controller.scala:45:7] wire io_cmd_bits_status_tw_0 = io_cmd_bits_status_tw; // @[Controller.scala:45:7] wire io_cmd_bits_status_tvm_0 = io_cmd_bits_status_tvm; // @[Controller.scala:45:7] wire io_cmd_bits_status_mxr_0 = io_cmd_bits_status_mxr; // @[Controller.scala:45:7] wire io_cmd_bits_status_sum_0 = io_cmd_bits_status_sum; // @[Controller.scala:45:7] wire io_cmd_bits_status_mprv_0 = io_cmd_bits_status_mprv; // @[Controller.scala:45:7] wire [1:0] io_cmd_bits_status_xs_0 = io_cmd_bits_status_xs; // @[Controller.scala:45:7] wire [1:0] io_cmd_bits_status_fs_0 = io_cmd_bits_status_fs; // @[Controller.scala:45:7] wire [1:0] io_cmd_bits_status_mpp_0 = io_cmd_bits_status_mpp; // @[Controller.scala:45:7] wire [1:0] io_cmd_bits_status_vs_0 = io_cmd_bits_status_vs; // @[Controller.scala:45:7] wire io_cmd_bits_status_spp_0 = io_cmd_bits_status_spp; // @[Controller.scala:45:7] wire io_cmd_bits_status_mpie_0 = io_cmd_bits_status_mpie; // @[Controller.scala:45:7] wire io_cmd_bits_status_ube_0 = io_cmd_bits_status_ube; // @[Controller.scala:45:7] wire io_cmd_bits_status_spie_0 = io_cmd_bits_status_spie; // @[Controller.scala:45:7] wire io_cmd_bits_status_upie_0 = io_cmd_bits_status_upie; // @[Controller.scala:45:7] wire io_cmd_bits_status_mie_0 = io_cmd_bits_status_mie; // @[Controller.scala:45:7] wire io_cmd_bits_status_hie_0 = io_cmd_bits_status_hie; // @[Controller.scala:45:7] wire io_cmd_bits_status_sie_0 = io_cmd_bits_status_sie; // @[Controller.scala:45:7] wire io_cmd_bits_status_uie_0 = io_cmd_bits_status_uie; // @[Controller.scala:45:7] wire io_resp_ready_0 = io_resp_ready; // @[Controller.scala:45:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[Controller.scala:45:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[Controller.scala:45:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[Controller.scala:45:7] wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[Controller.scala:45:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[Controller.scala:45:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[Controller.scala:45:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[Controller.scala:45:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[Controller.scala:45:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[Controller.scala:45:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[Controller.scala:45:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[Controller.scala:45:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[Controller.scala:45:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[Controller.scala:45:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[Controller.scala:45:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[Controller.scala:45:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[Controller.scala:45:7] wire io_exception_0 = io_exception; // @[Controller.scala:45:7] wire io_ptw_0_req_ready_0 = io_ptw_0_req_ready; // @[Controller.scala:45:7] wire io_ptw_0_resp_valid_0 = io_ptw_0_resp_valid; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_ae_ptw_0 = io_ptw_0_resp_bits_ae_ptw; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_ae_final_0 = io_ptw_0_resp_bits_ae_final; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_pf_0 = io_ptw_0_resp_bits_pf; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_gf_0 = io_ptw_0_resp_bits_gf; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_hr_0 = io_ptw_0_resp_bits_hr; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_hw_0 = io_ptw_0_resp_bits_hw; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_hx_0 = io_ptw_0_resp_bits_hx; // @[Controller.scala:45:7] wire [9:0] io_ptw_0_resp_bits_pte_reserved_for_future_0 = io_ptw_0_resp_bits_pte_reserved_for_future; // @[Controller.scala:45:7] wire [43:0] io_ptw_0_resp_bits_pte_ppn_0 = io_ptw_0_resp_bits_pte_ppn; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_resp_bits_pte_reserved_for_software_0 = io_ptw_0_resp_bits_pte_reserved_for_software; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_pte_d_0 = io_ptw_0_resp_bits_pte_d; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_pte_a_0 = io_ptw_0_resp_bits_pte_a; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_pte_g_0 = io_ptw_0_resp_bits_pte_g; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_pte_u_0 = io_ptw_0_resp_bits_pte_u; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_pte_x_0 = io_ptw_0_resp_bits_pte_x; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_pte_w_0 = io_ptw_0_resp_bits_pte_w; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_pte_r_0 = io_ptw_0_resp_bits_pte_r; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_pte_v_0 = io_ptw_0_resp_bits_pte_v; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_resp_bits_level_0 = io_ptw_0_resp_bits_level; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_homogeneous_0 = io_ptw_0_resp_bits_homogeneous; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_gpa_valid_0 = io_ptw_0_resp_bits_gpa_valid; // @[Controller.scala:45:7] wire [38:0] io_ptw_0_resp_bits_gpa_bits_0 = io_ptw_0_resp_bits_gpa_bits; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_gpa_is_pte_0 = io_ptw_0_resp_bits_gpa_is_pte; // @[Controller.scala:45:7] wire [3:0] io_ptw_0_ptbr_mode_0 = io_ptw_0_ptbr_mode; // @[Controller.scala:45:7] wire [43:0] io_ptw_0_ptbr_ppn_0 = io_ptw_0_ptbr_ppn; // @[Controller.scala:45:7] wire io_ptw_0_status_debug_0 = io_ptw_0_status_debug; // @[Controller.scala:45:7] wire io_ptw_0_status_cease_0 = io_ptw_0_status_cease; // @[Controller.scala:45:7] wire io_ptw_0_status_wfi_0 = io_ptw_0_status_wfi; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_status_isa_0 = io_ptw_0_status_isa; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_status_dprv_0 = io_ptw_0_status_dprv; // @[Controller.scala:45:7] wire io_ptw_0_status_dv_0 = io_ptw_0_status_dv; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_status_prv_0 = io_ptw_0_status_prv; // @[Controller.scala:45:7] wire io_ptw_0_status_v_0 = io_ptw_0_status_v; // @[Controller.scala:45:7] wire io_ptw_0_status_mpv_0 = io_ptw_0_status_mpv; // @[Controller.scala:45:7] wire io_ptw_0_status_gva_0 = io_ptw_0_status_gva; // @[Controller.scala:45:7] wire io_ptw_0_status_tsr_0 = io_ptw_0_status_tsr; // @[Controller.scala:45:7] wire io_ptw_0_status_tw_0 = io_ptw_0_status_tw; // @[Controller.scala:45:7] wire io_ptw_0_status_tvm_0 = io_ptw_0_status_tvm; // @[Controller.scala:45:7] wire io_ptw_0_status_mxr_0 = io_ptw_0_status_mxr; // @[Controller.scala:45:7] wire io_ptw_0_status_sum_0 = io_ptw_0_status_sum; // @[Controller.scala:45:7] wire io_ptw_0_status_mprv_0 = io_ptw_0_status_mprv; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_status_fs_0 = io_ptw_0_status_fs; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_status_mpp_0 = io_ptw_0_status_mpp; // @[Controller.scala:45:7] wire io_ptw_0_status_spp_0 = io_ptw_0_status_spp; // @[Controller.scala:45:7] wire io_ptw_0_status_mpie_0 = io_ptw_0_status_mpie; // @[Controller.scala:45:7] wire io_ptw_0_status_spie_0 = io_ptw_0_status_spie; // @[Controller.scala:45:7] wire io_ptw_0_status_mie_0 = io_ptw_0_status_mie; // @[Controller.scala:45:7] wire io_ptw_0_status_sie_0 = io_ptw_0_status_sie; // @[Controller.scala:45:7] wire io_ptw_0_hstatus_spvp_0 = io_ptw_0_hstatus_spvp; // @[Controller.scala:45:7] wire io_ptw_0_hstatus_spv_0 = io_ptw_0_hstatus_spv; // @[Controller.scala:45:7] wire io_ptw_0_hstatus_gva_0 = io_ptw_0_hstatus_gva; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_debug_0 = io_ptw_0_gstatus_debug; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_cease_0 = io_ptw_0_gstatus_cease; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_wfi_0 = io_ptw_0_gstatus_wfi; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_gstatus_isa_0 = io_ptw_0_gstatus_isa; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_gstatus_dprv_0 = io_ptw_0_gstatus_dprv; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_dv_0 = io_ptw_0_gstatus_dv; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_gstatus_prv_0 = io_ptw_0_gstatus_prv; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_v_0 = io_ptw_0_gstatus_v; // @[Controller.scala:45:7] wire [22:0] io_ptw_0_gstatus_zero2_0 = io_ptw_0_gstatus_zero2; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_mpv_0 = io_ptw_0_gstatus_mpv; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_gva_0 = io_ptw_0_gstatus_gva; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_mbe_0 = io_ptw_0_gstatus_mbe; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_sbe_0 = io_ptw_0_gstatus_sbe; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_gstatus_sxl_0 = io_ptw_0_gstatus_sxl; // @[Controller.scala:45:7] wire [7:0] io_ptw_0_gstatus_zero1_0 = io_ptw_0_gstatus_zero1; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_tsr_0 = io_ptw_0_gstatus_tsr; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_tw_0 = io_ptw_0_gstatus_tw; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_tvm_0 = io_ptw_0_gstatus_tvm; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_mxr_0 = io_ptw_0_gstatus_mxr; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_sum_0 = io_ptw_0_gstatus_sum; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_mprv_0 = io_ptw_0_gstatus_mprv; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_gstatus_fs_0 = io_ptw_0_gstatus_fs; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_gstatus_mpp_0 = io_ptw_0_gstatus_mpp; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_gstatus_vs_0 = io_ptw_0_gstatus_vs; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_spp_0 = io_ptw_0_gstatus_spp; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_mpie_0 = io_ptw_0_gstatus_mpie; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_ube_0 = io_ptw_0_gstatus_ube; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_spie_0 = io_ptw_0_gstatus_spie; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_upie_0 = io_ptw_0_gstatus_upie; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_mie_0 = io_ptw_0_gstatus_mie; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_hie_0 = io_ptw_0_gstatus_hie; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_sie_0 = io_ptw_0_gstatus_sie; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_uie_0 = io_ptw_0_gstatus_uie; // @[Controller.scala:45:7] wire io_ptw_0_pmp_0_cfg_l_0 = io_ptw_0_pmp_0_cfg_l; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_0_cfg_a_0 = io_ptw_0_pmp_0_cfg_a; // @[Controller.scala:45:7] wire io_ptw_0_pmp_0_cfg_x_0 = io_ptw_0_pmp_0_cfg_x; // @[Controller.scala:45:7] wire io_ptw_0_pmp_0_cfg_w_0 = io_ptw_0_pmp_0_cfg_w; // @[Controller.scala:45:7] wire io_ptw_0_pmp_0_cfg_r_0 = io_ptw_0_pmp_0_cfg_r; // @[Controller.scala:45:7] wire [29:0] io_ptw_0_pmp_0_addr_0 = io_ptw_0_pmp_0_addr; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_pmp_0_mask_0 = io_ptw_0_pmp_0_mask; // @[Controller.scala:45:7] wire io_ptw_0_pmp_1_cfg_l_0 = io_ptw_0_pmp_1_cfg_l; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_1_cfg_a_0 = io_ptw_0_pmp_1_cfg_a; // @[Controller.scala:45:7] wire io_ptw_0_pmp_1_cfg_x_0 = io_ptw_0_pmp_1_cfg_x; // @[Controller.scala:45:7] wire io_ptw_0_pmp_1_cfg_w_0 = io_ptw_0_pmp_1_cfg_w; // @[Controller.scala:45:7] wire io_ptw_0_pmp_1_cfg_r_0 = io_ptw_0_pmp_1_cfg_r; // @[Controller.scala:45:7] wire [29:0] io_ptw_0_pmp_1_addr_0 = io_ptw_0_pmp_1_addr; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_pmp_1_mask_0 = io_ptw_0_pmp_1_mask; // @[Controller.scala:45:7] wire io_ptw_0_pmp_2_cfg_l_0 = io_ptw_0_pmp_2_cfg_l; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_2_cfg_a_0 = io_ptw_0_pmp_2_cfg_a; // @[Controller.scala:45:7] wire io_ptw_0_pmp_2_cfg_x_0 = io_ptw_0_pmp_2_cfg_x; // @[Controller.scala:45:7] wire io_ptw_0_pmp_2_cfg_w_0 = io_ptw_0_pmp_2_cfg_w; // @[Controller.scala:45:7] wire io_ptw_0_pmp_2_cfg_r_0 = io_ptw_0_pmp_2_cfg_r; // @[Controller.scala:45:7] wire [29:0] io_ptw_0_pmp_2_addr_0 = io_ptw_0_pmp_2_addr; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_pmp_2_mask_0 = io_ptw_0_pmp_2_mask; // @[Controller.scala:45:7] wire io_ptw_0_pmp_3_cfg_l_0 = io_ptw_0_pmp_3_cfg_l; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_3_cfg_a_0 = io_ptw_0_pmp_3_cfg_a; // @[Controller.scala:45:7] wire io_ptw_0_pmp_3_cfg_x_0 = io_ptw_0_pmp_3_cfg_x; // @[Controller.scala:45:7] wire io_ptw_0_pmp_3_cfg_w_0 = io_ptw_0_pmp_3_cfg_w; // @[Controller.scala:45:7] wire io_ptw_0_pmp_3_cfg_r_0 = io_ptw_0_pmp_3_cfg_r; // @[Controller.scala:45:7] wire [29:0] io_ptw_0_pmp_3_addr_0 = io_ptw_0_pmp_3_addr; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_pmp_3_mask_0 = io_ptw_0_pmp_3_mask; // @[Controller.scala:45:7] wire io_ptw_0_pmp_4_cfg_l_0 = io_ptw_0_pmp_4_cfg_l; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_4_cfg_a_0 = io_ptw_0_pmp_4_cfg_a; // @[Controller.scala:45:7] wire io_ptw_0_pmp_4_cfg_x_0 = io_ptw_0_pmp_4_cfg_x; // @[Controller.scala:45:7] wire io_ptw_0_pmp_4_cfg_w_0 = io_ptw_0_pmp_4_cfg_w; // @[Controller.scala:45:7] wire io_ptw_0_pmp_4_cfg_r_0 = io_ptw_0_pmp_4_cfg_r; // @[Controller.scala:45:7] wire [29:0] io_ptw_0_pmp_4_addr_0 = io_ptw_0_pmp_4_addr; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_pmp_4_mask_0 = io_ptw_0_pmp_4_mask; // @[Controller.scala:45:7] wire io_ptw_0_pmp_5_cfg_l_0 = io_ptw_0_pmp_5_cfg_l; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_5_cfg_a_0 = io_ptw_0_pmp_5_cfg_a; // @[Controller.scala:45:7] wire io_ptw_0_pmp_5_cfg_x_0 = io_ptw_0_pmp_5_cfg_x; // @[Controller.scala:45:7] wire io_ptw_0_pmp_5_cfg_w_0 = io_ptw_0_pmp_5_cfg_w; // @[Controller.scala:45:7] wire io_ptw_0_pmp_5_cfg_r_0 = io_ptw_0_pmp_5_cfg_r; // @[Controller.scala:45:7] wire [29:0] io_ptw_0_pmp_5_addr_0 = io_ptw_0_pmp_5_addr; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_pmp_5_mask_0 = io_ptw_0_pmp_5_mask; // @[Controller.scala:45:7] wire io_ptw_0_pmp_6_cfg_l_0 = io_ptw_0_pmp_6_cfg_l; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_6_cfg_a_0 = io_ptw_0_pmp_6_cfg_a; // @[Controller.scala:45:7] wire io_ptw_0_pmp_6_cfg_x_0 = io_ptw_0_pmp_6_cfg_x; // @[Controller.scala:45:7] wire io_ptw_0_pmp_6_cfg_w_0 = io_ptw_0_pmp_6_cfg_w; // @[Controller.scala:45:7] wire io_ptw_0_pmp_6_cfg_r_0 = io_ptw_0_pmp_6_cfg_r; // @[Controller.scala:45:7] wire [29:0] io_ptw_0_pmp_6_addr_0 = io_ptw_0_pmp_6_addr; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_pmp_6_mask_0 = io_ptw_0_pmp_6_mask; // @[Controller.scala:45:7] wire io_ptw_0_pmp_7_cfg_l_0 = io_ptw_0_pmp_7_cfg_l; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_7_cfg_a_0 = io_ptw_0_pmp_7_cfg_a; // @[Controller.scala:45:7] wire io_ptw_0_pmp_7_cfg_x_0 = io_ptw_0_pmp_7_cfg_x; // @[Controller.scala:45:7] wire io_ptw_0_pmp_7_cfg_w_0 = io_ptw_0_pmp_7_cfg_w; // @[Controller.scala:45:7] wire io_ptw_0_pmp_7_cfg_r_0 = io_ptw_0_pmp_7_cfg_r; // @[Controller.scala:45:7] wire [29:0] io_ptw_0_pmp_7_addr_0 = io_ptw_0_pmp_7_addr; // @[Controller.scala:45:7] wire [31:0] io_ptw_0_pmp_7_mask_0 = io_ptw_0_pmp_7_mask; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_0_ren_0 = io_ptw_0_customCSRs_csrs_0_ren; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_0_wen_0 = io_ptw_0_customCSRs_csrs_0_wen; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_0_wdata_0 = io_ptw_0_customCSRs_csrs_0_wdata; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_0_value_0 = io_ptw_0_customCSRs_csrs_0_value; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_1_ren_0 = io_ptw_0_customCSRs_csrs_1_ren; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_1_wen_0 = io_ptw_0_customCSRs_csrs_1_wen; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_1_wdata_0 = io_ptw_0_customCSRs_csrs_1_wdata; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_1_value_0 = io_ptw_0_customCSRs_csrs_1_value; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_2_ren_0 = io_ptw_0_customCSRs_csrs_2_ren; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_2_wen_0 = io_ptw_0_customCSRs_csrs_2_wen; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_2_wdata_0 = io_ptw_0_customCSRs_csrs_2_wdata; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_2_value_0 = io_ptw_0_customCSRs_csrs_2_value; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_3_ren_0 = io_ptw_0_customCSRs_csrs_3_ren; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_3_wen_0 = io_ptw_0_customCSRs_csrs_3_wen; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_3_wdata_0 = io_ptw_0_customCSRs_csrs_3_wdata; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_3_value_0 = io_ptw_0_customCSRs_csrs_3_value; // @[Controller.scala:45:7] wire io_mem_req_valid = 1'h0; // @[Controller.scala:45:7] wire io_mem_req_bits_signed = 1'h0; // @[Controller.scala:45:7] wire io_mem_req_bits_dv = 1'h0; // @[Controller.scala:45:7] wire io_mem_req_bits_phys = 1'h0; // @[Controller.scala:45:7] wire io_mem_req_bits_no_resp = 1'h0; // @[Controller.scala:45:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[Controller.scala:45:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[Controller.scala:45:7] wire io_mem_s1_kill = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_nack = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_nack_cause_raw = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_kill = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_uncached = 1'h0; // @[Controller.scala:45:7] wire io_mem_replay_next = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_xcpt_ma_ld = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_xcpt_ma_st = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_xcpt_pf_ld = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_xcpt_pf_st = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_xcpt_ae_ld = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_xcpt_ae_st = 1'h0; // @[Controller.scala:45:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[Controller.scala:45:7] wire io_mem_ordered = 1'h0; // @[Controller.scala:45:7] wire io_mem_store_pending = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_acquire = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_release = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_grant = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_tlbMiss = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_blocked = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Controller.scala:45:7] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[Controller.scala:45:7] wire io_mem_keep_clock_enabled = 1'h0; // @[Controller.scala:45:7] wire io_mem_clock_enabled = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_req_bits_bits_vstage1 = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_req_bits_bits_stage2 = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_resp_bits_fragmented_superpage = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_status_mbe = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_status_sbe = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_status_sd_rv32 = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_status_ube = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_status_upie = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_status_hie = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_status_uie = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_hstatus_vtsr = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_hstatus_vtw = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_hstatus_vtvm = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_hstatus_hu = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_hstatus_vsbe = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_sd_rv32 = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_0_stall = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_0_set = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_1_stall = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_1_set = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_2_stall = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_2_set = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_3_stall = 1'h0; // @[Controller.scala:45:7] wire io_ptw_0_customCSRs_csrs_3_set = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_ready = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_valid = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_ldst = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_wen = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_ren1 = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_ren2 = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_ren3 = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_swap12 = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_swap23 = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_fromint = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_toint = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_fastpipe = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_fma = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_div = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_sqrt = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_wflags = 1'h0; // @[Controller.scala:45:7] wire io_fpu_req_bits_vec = 1'h0; // @[Controller.scala:45:7] wire io_fpu_resp_ready = 1'h0; // @[Controller.scala:45:7] wire io_fpu_resp_valid = 1'h0; // @[Controller.scala:45:7] wire [15:0] io_ptw_0_ptbr_asid = 16'h0; // @[Controller.scala:45:7] wire [15:0] io_ptw_0_hgatp_asid = 16'h0; // @[Controller.scala:45:7] wire [15:0] io_ptw_0_vsatp_asid = 16'h0; // @[Controller.scala:45:7] wire [3:0] io_ptw_0_hgatp_mode = 4'h0; // @[Controller.scala:45:7] wire [3:0] io_ptw_0_vsatp_mode = 4'h0; // @[Controller.scala:45:7] wire [43:0] io_ptw_0_hgatp_ppn = 44'h0; // @[Controller.scala:45:7] wire [43:0] io_ptw_0_vsatp_ppn = 44'h0; // @[Controller.scala:45:7] wire io_ptw_0_req_bits_valid = 1'h1; // @[Controller.scala:45:7] wire io_ptw_0_status_sd = 1'h1; // @[Controller.scala:45:7] wire io_ptw_0_gstatus_sd = 1'h1; // @[Controller.scala:45:7] wire [22:0] io_ptw_0_status_zero2 = 23'h0; // @[Controller.scala:45:7] wire [7:0] io_mem_req_bits_tag = 8'h0; // @[Controller.scala:45:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[Controller.scala:45:7] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[Controller.scala:45:7] wire [7:0] io_ptw_0_status_zero1 = 8'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_status_xs = 2'h3; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_gstatus_xs = 2'h3; // @[Controller.scala:45:7] wire [1:0] io_mem_req_bits_size = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_mem_req_bits_dprv = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_status_vs = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_hstatus_zero3 = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_hstatus_zero2 = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_0_cfg_res = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_1_cfg_res = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_2_cfg_res = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_3_cfg_res = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_4_cfg_res = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_5_cfg_res = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_6_cfg_res = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_pmp_7_cfg_res = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_fpu_req_bits_typeTagIn = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_fpu_req_bits_typeTagOut = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_fpu_req_bits_fmaCmd = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_fpu_req_bits_typ = 2'h0; // @[Controller.scala:45:7] wire [1:0] io_fpu_req_bits_fmt = 2'h0; // @[Controller.scala:45:7] wire [29:0] io_ptw_0_hstatus_zero6 = 30'h0; // @[Controller.scala:45:7] wire [8:0] io_ptw_0_hstatus_zero5 = 9'h0; // @[Controller.scala:45:7] wire [5:0] io_ptw_0_hstatus_vgein = 6'h0; // @[Controller.scala:45:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[Controller.scala:45:7] wire [4:0] io_ptw_0_hstatus_zero1 = 5'h0; // @[Controller.scala:45:7] wire [4:0] io_fpu_resp_bits_exc = 5'h0; // @[Controller.scala:45:7] wire [39:0] io_mem_req_bits_addr = 40'h0; // @[Controller.scala:45:7] wire [39:0] io_mem_s2_gpa = 40'h0; // @[Controller.scala:45:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[Controller.scala:45:7] wire [63:0] io_mem_s1_data_data = 64'h0; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_0_sdata = 64'h0; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_1_sdata = 64'h0; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_2_sdata = 64'h0; // @[Controller.scala:45:7] wire [63:0] io_ptw_0_customCSRs_csrs_3_sdata = 64'h0; // @[Controller.scala:45:7] wire [31:0] io_mem_s2_paddr = 32'h0; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_status_sxl = 2'h2; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_status_uxl = 2'h2; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_hstatus_vsxl = 2'h2; // @[Controller.scala:45:7] wire [1:0] io_ptw_0_gstatus_uxl = 2'h2; // @[Controller.scala:45:7] wire [2:0] io_fpu_req_bits_rm = 3'h0; // @[Controller.scala:45:7] wire [64:0] io_fpu_req_bits_in1 = 65'h0; // @[Controller.scala:45:7] wire [64:0] io_fpu_req_bits_in2 = 65'h0; // @[Controller.scala:45:7] wire [64:0] io_fpu_req_bits_in3 = 65'h0; // @[Controller.scala:45:7] wire [64:0] io_fpu_resp_bits_data = 65'h0; // @[Controller.scala:45:7] wire _io_busy_T_6; // @[Controller.scala:330:178] wire [2:0] auto_spad_id_out_a_bits_opcode_0; // @[Controller.scala:45:7] wire [2:0] auto_spad_id_out_a_bits_param_0; // @[Controller.scala:45:7] wire [3:0] auto_spad_id_out_a_bits_size_0; // @[Controller.scala:45:7] wire [6:0] auto_spad_id_out_a_bits_source_0; // @[Controller.scala:45:7] wire [31:0] auto_spad_id_out_a_bits_address_0; // @[Controller.scala:45:7] wire [15:0] auto_spad_id_out_a_bits_mask_0; // @[Controller.scala:45:7] wire [127:0] auto_spad_id_out_a_bits_data_0; // @[Controller.scala:45:7] wire auto_spad_id_out_a_bits_corrupt_0; // @[Controller.scala:45:7] wire auto_spad_id_out_a_valid_0; // @[Controller.scala:45:7] wire auto_spad_id_out_d_ready_0; // @[Controller.scala:45:7] wire io_cmd_ready_0; // @[Controller.scala:45:7] wire [4:0] io_resp_bits_rd_0; // @[Controller.scala:45:7] wire [63:0] io_resp_bits_data_0; // @[Controller.scala:45:7] wire io_resp_valid_0; // @[Controller.scala:45:7] wire [26:0] io_ptw_0_req_bits_bits_addr_0; // @[Controller.scala:45:7] wire io_ptw_0_req_bits_bits_need_gpa_0; // @[Controller.scala:45:7] wire io_ptw_0_req_valid_0; // @[Controller.scala:45:7] wire io_busy_0; // @[Controller.scala:45:7] wire io_interrupt_0; // @[Controller.scala:45:7] wire _spad_io_flush_T = tlb_io_exp_0_flush_retry | tlb_io_exp_0_flush_skip; // @[FrontendTLB.scala:25:49] reg clock_en_reg; // @[Controller.scala:81:29] wire _clock_en_reg_T = io_cmd_bits_rs1_0[0]; // @[Controller.scala:45:7, :128:36] wire _io_busy_T = _raw_cmd_q_io_deq_valid | _mod_io_busy; // @[LoopConv.scala:1542:21] wire _io_busy_T_1 = _io_busy_T | _mod_1_io_busy; // @[LoopMatmul.scala:1127:21] wire _io_busy_T_2 = _io_busy_T_1 | _reservation_station_io_busy; // @[Controller.scala:124:61, :330:{55,84}] wire _io_busy_T_3 = _io_busy_T_2 | _spad_io_busy; // @[Controller.scala:36:24, :330:{84,115}] wire _io_busy_T_4 = _io_busy_T_3 | _unrolled_cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _io_busy_T_5 = _io_busy_T_4 | _mod_1_io_out_valid; // @[LoopMatmul.scala:1127:21] assign _io_busy_T_6 = _io_busy_T_5 | _mod_io_out_valid; // @[LoopConv.scala:1542:21] assign io_busy_0 = _io_busy_T_6; // @[Controller.scala:45:7, :330:178] wire _incr_ld_cycles_T = ~_store_controller_io_busy; // @[Controller.scala:189:58, :337:51] wire _incr_ld_cycles_T_1 = _load_controller_io_busy & _incr_ld_cycles_T; // @[Controller.scala:188:57, :337:{48,51}] wire _incr_ld_cycles_T_2 = ~_ex_controller_io_busy; // @[Controller.scala:190:55, :337:80] wire incr_ld_cycles = _incr_ld_cycles_T_1 & _incr_ld_cycles_T_2; // @[Controller.scala:337:{48,77,80}] wire _incr_st_cycles_T = ~_load_controller_io_busy; // @[Controller.scala:188:57, :338:24] wire _incr_st_cycles_T_1 = _incr_st_cycles_T & _store_controller_io_busy; // @[Controller.scala:189:58, :338:{24,49}] wire _incr_st_cycles_T_2 = ~_ex_controller_io_busy; // @[Controller.scala:190:55, :337:80, :338:80] wire incr_st_cycles = _incr_st_cycles_T_1 & _incr_st_cycles_T_2; // @[Controller.scala:338:{49,77,80}] wire _incr_ex_cycles_T = ~_load_controller_io_busy; // @[Controller.scala:188:57, :338:24, :339:24] wire _incr_ex_cycles_T_1 = ~_store_controller_io_busy; // @[Controller.scala:189:58, :337:51, :339:52] wire _incr_ex_cycles_T_2 = _incr_ex_cycles_T & _incr_ex_cycles_T_1; // @[Controller.scala:339:{24,49,52}] wire incr_ex_cycles = _incr_ex_cycles_T_2 & _ex_controller_io_busy; // @[Controller.scala:190:55, :339:{49,78}] wire _GEN = _load_controller_io_busy & _store_controller_io_busy; // @[Controller.scala:188:57, :189:58, :341:51] wire _incr_ld_st_cycles_T; // @[Controller.scala:341:51] assign _incr_ld_st_cycles_T = _GEN; // @[Controller.scala:341:51] wire _incr_ld_st_ex_cycles_T; // @[Controller.scala:345:54] assign _incr_ld_st_ex_cycles_T = _GEN; // @[Controller.scala:341:51, :345:54] wire _incr_ld_st_cycles_T_1 = ~_ex_controller_io_busy; // @[Controller.scala:190:55, :337:80, :341:82] wire incr_ld_st_cycles = _incr_ld_st_cycles_T & _incr_ld_st_cycles_T_1; // @[Controller.scala:341:{51,79,82}] wire _incr_ld_ex_cycles_T = ~_store_controller_io_busy; // @[Controller.scala:189:58, :337:51, :342:54] wire _incr_ld_ex_cycles_T_1 = _load_controller_io_busy & _incr_ld_ex_cycles_T; // @[Controller.scala:188:57, :342:{51,54}] wire incr_ld_ex_cycles = _incr_ld_ex_cycles_T_1 & _ex_controller_io_busy; // @[Controller.scala:190:55, :342:{51,80}] wire _incr_st_ex_cycles_T = ~_load_controller_io_busy; // @[Controller.scala:188:57, :338:24, :343:27] wire _incr_st_ex_cycles_T_1 = _incr_st_ex_cycles_T & _store_controller_io_busy; // @[Controller.scala:189:58, :343:{27,52}] wire incr_st_ex_cycles = _incr_st_ex_cycles_T_1 & _ex_controller_io_busy; // @[Controller.scala:190:55, :343:{52,80}] wire incr_ld_st_ex_cycles = _incr_ld_st_ex_cycles_T & _ex_controller_io_busy; // @[Controller.scala:190:55, :345:{54,82}] wire is_flush = _unrolled_cmd_q_io_deq_bits_cmd_inst_funct == 7'h7; // @[Decoupled.scala:362:21] wire is_counter_op = _unrolled_cmd_q_io_deq_bits_cmd_inst_funct == 7'h7E; // @[Decoupled.scala:362:21] wire is_clock_gate_en = _unrolled_cmd_q_io_deq_bits_cmd_inst_funct == 7'h16; // @[Decoupled.scala:362:21] wire skip = _unrolled_cmd_q_io_deq_bits_cmd_rs1[0]; // @[Decoupled.scala:362:21] wire _GEN_0 = _unrolled_cmd_q_io_deq_valid & is_flush; // @[Decoupled.scala:362:21] assign tlb_io_exp_0_flush_skip = _GEN_0 & skip; // @[Controller.scala:72:35, :358:29, :375:21, :376:43, :377:39] wire _tlb_io_exp_0_flush_retry_T = ~skip; // @[Controller.scala:376:43, :378:43] assign tlb_io_exp_0_flush_retry = _GEN_0 & _tlb_io_exp_0_flush_retry_T; // @[Controller.scala:72:35, :73:36, :358:29, :375:21, :377:39, :378:{40,43}] wire reservation_station_io_alloc_valid = _unrolled_cmd_q_io_deq_valid & ~(is_flush | is_counter_op | is_clock_gate_en); // @[Decoupled.scala:362:21] reg [31:0] pipeline_stall_counter; // @[Controller.scala:405:39] wire [32:0] _pipeline_stall_counter_T = {1'h0, pipeline_stall_counter} + 33'h1; // @[Controller.scala:405:39, :409:54] wire [31:0] _pipeline_stall_counter_T_1 = _pipeline_stall_counter_T[31:0]; // @[Controller.scala:409:54]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_53( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_73 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }
module AsyncResetRegVec_w1_i0_31( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset // @[AsyncResetReg.scala:56:7] ); wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7] wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncQueueSink_TLBundleD_a9d32s1k1z2u( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [2:0] io_deq_bits_opcode, // @[AsyncQueue.scala:139:14] output [1:0] io_deq_bits_param, // @[AsyncQueue.scala:139:14] output [1:0] io_deq_bits_size, // @[AsyncQueue.scala:139:14] output io_deq_bits_source, // @[AsyncQueue.scala:139:14] output io_deq_bits_sink, // @[AsyncQueue.scala:139:14] output io_deq_bits_denied, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_data, // @[AsyncQueue.scala:139:14] output io_deq_bits_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_0_size, // @[AsyncQueue.scala:139:14] input io_async_mem_0_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_data, // @[AsyncQueue.scala:139:14] output io_async_ridx, // @[AsyncQueue.scala:139:14] input io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [2:0] io_async_mem_0_opcode_0 = io_async_mem_0_opcode; // @[AsyncQueue.scala:136:7] wire [1:0] io_async_mem_0_size_0 = io_async_mem_0_size; // @[AsyncQueue.scala:136:7] wire io_async_mem_0_source_0 = io_async_mem_0_source; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_data_0 = io_async_mem_0_data; // @[AsyncQueue.scala:136:7] wire io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire io_async_mem_0_sink = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_0_denied = 1'h0; // @[AsyncQueue.scala:136:7] wire io_async_mem_0_corrupt = 1'h0; // @[AsyncQueue.scala:136:7] wire _ridx_T_3 = 1'h0; // @[AsyncQueue.scala:54:32] wire io_deq_bits_deq_bits_reg_io_d_lo_hi_hi = 1'h0; // @[SynchronizerReg.scala:209:24] wire io_deq_bits_deq_bits_reg_io_d_lo_hi = 1'h0; // @[SynchronizerReg.scala:209:24] wire [1:0] io_async_mem_0_param = 2'h0; // @[AsyncQueue.scala:136:7, :139:14] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [2:0] _io_deq_bits_WIRE_opcode; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_WIRE_param; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_WIRE_size; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_WIRE_source; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_WIRE_sink; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_WIRE_denied; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_data; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_WIRE_corrupt; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [2:0] io_deq_bits_opcode_0; // @[AsyncQueue.scala:136:7] wire [1:0] io_deq_bits_param_0; // @[AsyncQueue.scala:136:7] wire [1:0] io_deq_bits_size_0; // @[AsyncQueue.scala:136:7] wire io_deq_bits_source_0; // @[AsyncQueue.scala:136:7] wire io_deq_bits_sink_0; // @[AsyncQueue.scala:136:7] wire io_deq_bits_denied_0; // @[AsyncQueue.scala:136:7] wire [31:0] io_deq_bits_data_0; // @[AsyncQueue.scala:136:7] wire io_deq_bits_corrupt_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire ridx_incremented; // @[AsyncQueue.scala:51:27] wire ridx = ridx_incremented; // @[AsyncQueue.scala:51:27, :54:17] reg ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [1:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {1'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire _ridx_incremented_T_1 = _ridx_incremented_T[0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = ~_ridx_T_2 & _ridx_incremented_T_1; // @[AsyncQueue.scala:53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [32:0] io_deq_bits_deq_bits_reg_io_d_lo_lo = {io_async_mem_0_data_0, 1'h0}; // @[SynchronizerReg.scala:209:24] wire [33:0] io_deq_bits_deq_bits_reg_io_d_lo = {1'h0, io_deq_bits_deq_bits_reg_io_d_lo_lo}; // @[SynchronizerReg.scala:209:24] wire [1:0] io_deq_bits_deq_bits_reg_io_d_hi_lo = {io_async_mem_0_source_0, 1'h0}; // @[SynchronizerReg.scala:209:24] wire [4:0] io_deq_bits_deq_bits_reg_io_d_hi_hi_hi = {io_async_mem_0_opcode_0, 2'h0}; // @[SynchronizerReg.scala:209:24] wire [6:0] io_deq_bits_deq_bits_reg_io_d_hi_hi = {io_deq_bits_deq_bits_reg_io_d_hi_hi_hi, io_async_mem_0_size_0}; // @[SynchronizerReg.scala:209:24] wire [8:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_deq_bits_deq_bits_reg_io_d_hi_hi, io_deq_bits_deq_bits_reg_io_d_hi_lo}; // @[SynchronizerReg.scala:209:24] wire [42:0] _io_deq_bits_deq_bits_reg_io_d_T = {io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala:209:24] wire [2:0] _io_deq_bits_T_7; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_opcode_0 = _io_deq_bits_WIRE_opcode; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_T_6; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_param_0 = _io_deq_bits_WIRE_param; // @[SynchronizerReg.scala:211:26] wire [1:0] _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_size_0 = _io_deq_bits_WIRE_size; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_source_0 = _io_deq_bits_WIRE_source; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_sink_0 = _io_deq_bits_WIRE_sink; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_denied_0 = _io_deq_bits_WIRE_denied; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_data_0 = _io_deq_bits_WIRE_data; // @[SynchronizerReg.scala:211:26] wire _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_corrupt_0 = _io_deq_bits_WIRE_corrupt; // @[SynchronizerReg.scala:211:26] wire [42:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_corrupt = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_1 = _io_deq_bits_WIRE_1[32:1]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_data = _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_2 = _io_deq_bits_WIRE_1[33]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_denied = _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_3 = _io_deq_bits_WIRE_1[34]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_sink = _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_4 = _io_deq_bits_WIRE_1[35]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_source = _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_5 = _io_deq_bits_WIRE_1[37:36]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_size = _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_6 = _io_deq_bits_WIRE_1[39:38]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_param = _io_deq_bits_T_6; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T_7 = _io_deq_bits_WIRE_1[42:40]; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_opcode = _io_deq_bits_T_7; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 1'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 1'h0; // @[AsyncQueue.scala:168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_59( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_76 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_31( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] a_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] a_first_beats1_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count_1 = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [515:0] _inflight_opcodes_T_4 = 516'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [515:0] _inflight_sizes_T_4 = 516'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [128:0] _inflight_T_4 = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [515:0] d_opcodes_clr_1 = 516'h0; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1 = 516'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [128:0] d_clr_1 = 129'h0; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1 = 129'h0; // @[Monitor.scala:775:34] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_63 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {11'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31] wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_117 = _source_ok_T_116 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_118 = _source_ok_T_117 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_119 = _source_ok_T_118 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_120 = _source_ok_T_119 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_121 = _source_ok_T_120 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_127 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _T_1483 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1483; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1483; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T = a_first ? 3'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_1551 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1551; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1551; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1551; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1 = d_first_beats1_decode; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T_1 = a_first_1 ? 3'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_decode_1; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1416 = _T_1483 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1416 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1416 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1416 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1416 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1416 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_1462 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_4 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1462 ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1429 = _T_1551 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_1429 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1429 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1429 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_decode_2; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [80:0] inflight; // @[Monitor.scala:614:27] reg [323:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [647:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [80:0] inflight_1; // @[Monitor.scala:726:35] reg [647:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_142( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_104( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_119 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File regfile.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Register File (Abstract class and Synthesizable RegFile) //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import scala.collection.mutable.ArrayBuffer import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} /** * IO bundle for a register read port * * @param addrWidth size of register address in bits * @param dataWidth size of register in bits */ class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle { val addr = Input(UInt(addrWidth.W)) val data = Output(UInt(dataWidth.W)) } /** * IO bundle for the register write port * * @param addrWidth size of register address in bits * @param dataWidth size of register in bits */ class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle { val addr = UInt(addrWidth.W) val data = UInt(dataWidth.W) } /** * Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os. */ object WritePort { def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt) (implicit p: Parameters): Valid[RegisterFileWritePort] = { val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth))) wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype wport.bits.addr := enq.bits.uop.pdst wport.bits.data := enq.bits.data enq.ready := true.B wport } } /** * Register file abstract class * * @param numRegisters number of registers * @param numReadPorts number of read ports * @param numWritePorts number of write ports * @param registerWidth size of registers in bits * @param bypassableArray list of write ports from func units to the read port of the regfile */ abstract class RegisterFile( numRegisters: Int, numReadPorts: Int, numWritePorts: Int, registerWidth: Int, bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports? (implicit p: Parameters) extends BoomModule { val io = IO(new BoomBundle { val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth)) val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth)))) }) private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts) private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer" override def toString: String = BoomCoreStringPrefix( "==" + type_str + " Regfile==", "Num RF Read Ports : " + numReadPorts, "Num RF Write Ports : " + numWritePorts, "RF Cost (R+W)*(R+2W) : " + rf_cost, "Bypassable Units : " + bypassableArray) } /** * A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts. * * @param numRegisters number of registers * @param numReadPorts number of read ports * @param numWritePorts number of write ports * @param registerWidth size of registers in bits * @param bypassableArray list of write ports from func units to the read port of the regfile */ class RegisterFileSynthesizable( numRegisters: Int, numReadPorts: Int, numWritePorts: Int, registerWidth: Int, bypassableArray: Seq[Boolean]) (implicit p: Parameters) extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray) { // -------------------------------------------------------------- val regfile = Mem(numRegisters, UInt(registerWidth.W)) // -------------------------------------------------------------- // Read ports. val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W))) // Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired). val read_addrs = io.read_ports.map(p => RegNext(p.addr)) for (i <- 0 until numReadPorts) { read_data(i) := regfile(read_addrs(i)) } // -------------------------------------------------------------- // Bypass out of the ALU's write ports. // We are assuming we cannot bypass a writer to a reader within the regfile memory // for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1. // But since these bypasses are expensive, and not all write ports need to bypass their data, // only perform the w->r bypass on a select number of write ports. require (bypassableArray.length == io.write_ports.length) if (bypassableArray.reduce(_||_)) { val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]() io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} } for (i <- 0 until numReadPorts) { val bypass_ens = bypassable_wports.map(x => x.valid && x.bits.addr === read_addrs(i)) val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq)) io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i)) } } else { for (i <- 0 until numReadPorts) { io.read_ports(i).data := read_data(i) } } // -------------------------------------------------------------- // Write ports. for (wport <- io.write_ports) { when (wport.valid) { regfile(wport.bits.addr) := wport.bits.data } } // ensure there is only 1 writer per register (unless to preg0) if (numWritePorts > 1) { for (i <- 0 until (numWritePorts - 1)) { for (j <- (i + 1) until numWritePorts) { assert(!io.write_ports(i).valid || !io.write_ports(j).valid || (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) || (io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here "[regfile] too many writers a register") } } } }
module RegisterFileSynthesizable_3( // @[regfile.scala:106:7] input clock, // @[regfile.scala:106:7] input reset, // @[regfile.scala:106:7] input [5:0] io_read_ports_0_addr, // @[regfile.scala:82:14] output [64:0] io_read_ports_0_data, // @[regfile.scala:82:14] input [5:0] io_read_ports_1_addr, // @[regfile.scala:82:14] output [64:0] io_read_ports_1_data, // @[regfile.scala:82:14] input [5:0] io_read_ports_2_addr, // @[regfile.scala:82:14] output [64:0] io_read_ports_2_data, // @[regfile.scala:82:14] input io_write_ports_0_valid, // @[regfile.scala:82:14] input [5:0] io_write_ports_0_bits_addr, // @[regfile.scala:82:14] input [64:0] io_write_ports_0_bits_data, // @[regfile.scala:82:14] input io_write_ports_1_valid, // @[regfile.scala:82:14] input [5:0] io_write_ports_1_bits_addr, // @[regfile.scala:82:14] input [64:0] io_write_ports_1_bits_data // @[regfile.scala:82:14] ); wire [5:0] io_read_ports_0_addr_0 = io_read_ports_0_addr; // @[regfile.scala:106:7] wire [5:0] io_read_ports_1_addr_0 = io_read_ports_1_addr; // @[regfile.scala:106:7] wire [5:0] io_read_ports_2_addr_0 = io_read_ports_2_addr; // @[regfile.scala:106:7] wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:106:7] wire [5:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:106:7] wire [64:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:106:7] wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:106:7] wire [5:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:106:7] wire [64:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:106:7] wire [64:0] read_data_0; // @[regfile.scala:122:23] wire [64:0] read_data_1; // @[regfile.scala:122:23] wire [64:0] read_data_2; // @[regfile.scala:122:23] wire [64:0] io_read_ports_0_data_0; // @[regfile.scala:106:7] wire [64:0] io_read_ports_1_data_0; // @[regfile.scala:106:7] wire [64:0] io_read_ports_2_data_0; // @[regfile.scala:106:7] assign io_read_ports_0_data_0 = read_data_0; // @[regfile.scala:106:7, :122:23] assign io_read_ports_1_data_0 = read_data_1; // @[regfile.scala:106:7, :122:23] assign io_read_ports_2_data_0 = read_data_2; // @[regfile.scala:106:7, :122:23] reg [5:0] read_addrs_0; // @[regfile.scala:125:50] wire [5:0] _read_data_0_T = read_addrs_0; // @[regfile.scala:125:50, :128:28] reg [5:0] read_addrs_1; // @[regfile.scala:125:50] wire [5:0] _read_data_1_T = read_addrs_1; // @[regfile.scala:125:50, :128:28] reg [5:0] read_addrs_2; // @[regfile.scala:125:50] wire [5:0] _read_data_2_T = read_addrs_2; // @[regfile.scala:125:50, :128:28] wire [5:0] _read_data_0_T_1 = _read_data_0_T; // @[regfile.scala:128:28] wire [5:0] _read_data_1_T_1 = _read_data_1_T; // @[regfile.scala:128:28] wire [5:0] _read_data_2_T_1 = _read_data_2_T; // @[regfile.scala:128:28]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w4_d3_i0_16( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_169 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_170 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_171 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_172 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Frontend.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tile.{CoreBundle, BaseTile} import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut} import freechips.rocketchip.util.{ClockGate, ShiftQueue, property} import freechips.rocketchip.util.UIntToAugmentedUInt class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val speculative = Bool() } class FrontendExceptions extends Bundle { val pf = new Bundle { val inst = Bool() } val gf = new Bundle { val inst = Bool() } val ae = new Bundle { val inst = Bool() } } class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) { val btb = new BTBResp val pc = UInt(vaddrBitsExtended.W) // ID stage PC val data = UInt((fetchWidth * coreInstBits).W) val mask = Bits(fetchWidth.W) val xcpt = new FrontendExceptions val replay = Bool() } class FrontendPerfEvents extends Bundle { val acquire = Bool() val tlbMiss = Bool() } class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val might_request = Output(Bool()) val clock_enabled = Input(Bool()) val req = Valid(new FrontendReq) val sfence = Valid(new SFenceReq) val resp = Flipped(Decoupled(new FrontendResp)) val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W))) val gpa_is_pte = Input(Bool()) val btb_update = Valid(new BTBUpdate) val bht_update = Valid(new BHTUpdate) val ras_update = Valid(new RASUpdate) val flush_icache = Output(Bool()) val npc = Input(UInt(vaddrBitsExtended.W)) val perf = Input(new FrontendPerfEvents()) val progress = Output(Bool()) } class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) val icache = LazyModule(new ICache(icacheParams, tileId)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) } class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) { val cpu = Flipped(new FrontendIO()) val ptw = new TLBPTWIO() val errors = new ICacheErrors } class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasRocketCoreParameters with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) val fq = withReset(reset.asBool || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cpu.might_request io.cpu.clock_enabled := clock_en assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "icache_clock_gate") icache.clock := gated_clock icache.io.clock_enabled := clock_en withClock (gated_clock) { // entering gated-clock domain val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages))) val s1_valid = Reg(Bool()) val s2_valid = RegInit(false.B) val s0_fq_has_space = !fq.io.mask(fq.io.mask.getWidth-3) || (!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid || !s2_valid)) || (!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid)) val s0_valid = io.cpu.req.valid || s0_fq_has_space s1_valid := s0_valid val s1_pc = Reg(UInt(vaddrBitsExtended.W)) val s1_speculative = Reg(Bool()) val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector)) val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B val s2_btb_resp_bits = Reg(new BTBResp) val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken val s2_tlb_resp = Reg(tlb.io.resp.cloneType) val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst || s2_tlb_resp.gf.inst val s2_speculative = RegInit(false.B) val s2_partial_insn_valid = RegInit(false.B) val s2_partial_insn = Reg(UInt(coreInstBits.W)) val wrong_path = RegInit(false.B) val s1_base_pc = ~(~s1_pc | (fetchBytes - 1).U) val ntpc = s1_base_pc + fetchBytes.U val predicted_npc = WireDefault(ntpc) val predicted_taken = WireDefault(false.B) val s2_replay = Wire(Bool()) s2_replay := (s2_valid && !fq.io.enq.fire) || RegNext(s2_replay && !s0_valid, true.B) val npc = Mux(s2_replay, s2_pc, predicted_npc) s1_pc := io.cpu.npc // consider RVC fetches across blocks to be non-speculative if the first // part was non-speculative val s0_speculative = if (usingCompressed) s1_speculative || s2_valid && !s2_speculative || predicted_taken else true.B s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative)) val s2_redirect = WireDefault(io.cpu.req.valid) s2_valid := false.B when (!s2_replay) { s2_valid := !s2_redirect s2_pc := s1_pc s2_speculative := s1_speculative s2_tlb_resp := tlb.io.resp } val recent_progress_counter_init = 3.U val recent_progress_counter = RegInit(recent_progress_counter_init) val recent_progress = recent_progress_counter > 0.U when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U } when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init } val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress io.ptw <> tlb.io.ptw tlb.io.req.valid := s1_valid && !s2_replay tlb.io.req.bits.cmd := M_XRD // Frontend only reads tlb.io.req.bits.vaddr := s1_pc tlb.io.req.bits.passthrough := false.B tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth).U tlb.io.req.bits.prv := io.ptw.status.prv tlb.io.req.bits.v := io.ptw.status.v tlb.io.sfence := io.cpu.sfence tlb.io.kill := !s2_valid || s2_kill_speculative_tlb_refill icache.io.req.valid := s0_valid icache.io.req.bits.addr := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s2_vaddr := s2_pc icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill || s2_xcpt icache.io.s2_cacheable := s2_tlb_resp.cacheable icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) || (!s2_tlb_resp.miss && icache.io.s2_kill)) fq.io.enq.bits.pc := s2_pc io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)) fq.io.enq.bits.data := icache.io.resp.bits.data fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) fq.io.enq.bits.replay := (icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) fq.io.enq.bits.btb := s2_btb_resp_bits fq.io.enq.bits.btb.taken := s2_btb_taken fq.io.enq.bits.xcpt := s2_tlb_resp assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill)) when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B } if (usingBTB) { val btb = Module(new BTB) btb.io.flush := false.B btb.io.req.valid := false.B btb.io.req.bits.addr := s1_pc btb.io.btb_update := io.cpu.btb_update btb.io.bht_update := io.cpu.bht_update btb.io.ras_update.valid := false.B btb.io.ras_update.bits := DontCare btb.io.bht_advance.valid := false.B btb.io.bht_advance.bits := DontCare when (!s2_replay) { btb.io.req.valid := !s2_redirect s2_btb_resp_valid := btb.io.resp.valid s2_btb_resp_bits := btb.io.resp.bits } when (btb.io.resp.valid && btb.io.resp.bits.taken) { predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended) predicted_taken := true.B } val force_taken = io.ptw.customCSRs.bpmStatic when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B } when (force_taken) { btb.io.bht_update.valid := false.B } val s2_base_pc = ~(~s2_pc | (fetchBytes-1).U) val taken_idx = Wire(UInt()) val after_idx = Wire(UInt()) val useRAS = WireDefault(false.B) val updateBTB = WireDefault(false.B) // If !prevTaken, ras_update / bht_update is always invalid. taken_idx := DontCare after_idx := DontCare def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = { def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U val prevRVI = prevValid && !insnIsRVC(prevBits) val valid = fq.io.enq.bits.mask(idx) && !prevRVI val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx) val rvc = insnIsRVC(bits) val rviBits = Cat(bits, prevBits) val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0) val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0) val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0) val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15) val rviCall = (rviJALR || rviJump) && rviBits(7) val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL val rvcJump = bits === Instructions.C_J || rvcJAL val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt) val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7) val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U val rvcCall = rvcJAL || rvcJALR val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits)) val predict_taken = s2_btb_resp_bits.bht.taken || force_taken val taken = prevRVI && (rviJump || rviJALR || rviBranch && predict_taken) || valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && predict_taken) val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn) val predictJump = prevRVI && rviJump || valid && rvcJump val predictBranch = predict_taken && (prevRVI && rviBranch || valid && rvcBranch) when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) { // The BTB has predicted that the middle of an RVI instruction is // a branch! Flush the BTB and the pipeline. btb.io.flush := true.B fq.io.enq.bits.replay := true.B wrong_path := true.B ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path") } when (!prevTaken) { taken_idx := idx.U after_idx := (idx + 1).U btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn)) btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call, Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch, CFIType.jump))) when (!s2_btb_taken) { when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) { wrong_path := true.B } when (s2_valid && predictReturn) { useRAS := true.B } when (s2_valid && (predictBranch || predictJump)) { val pc = s2_base_pc | (idx*coreInstBytes).U val npc = if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm) else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm) predicted_npc := npc.asUInt } } when (prevRVI && rviBranch || valid && rvcBranch) { btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path btb.io.bht_advance.bits := s2_btb_resp_bits } when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken || predictJump || predictReturn)) { updateBTB := true.B } } if (idx == fetchWidth-1) { when (fq.io.enq.fire) { s2_partial_insn_valid := false.B when (valid && !prevTaken && !rvc) { s2_partial_insn_valid := true.B s2_partial_insn := bits | 0x3.U } } prevTaken || taken } else { scanInsns(idx + 1, valid, bits, prevTaken || taken) } } when (!io.cpu.btb_update.valid) { val fetch_bubble_likely = !fq.io.mask(1) btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U btb.io.btb_update.bits.isValid := true.B btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType btb.io.btb_update.bits.br_pc := s2_base_pc | (taken_idx << log2Ceil(coreInstBytes)) btb.io.btb_update.bits.pc := s2_base_pc } btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes)) val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B) when (useRAS) { predicted_npc := btb.io.ras_head.bits } when (fq.io.enq.fire && (s2_btb_taken || taken)) { s2_partial_insn_valid := false.B } when (!s2_btb_taken) { when (taken) { fq.io.enq.bits.btb.bridx := taken_idx fq.io.enq.bits.btb.taken := true.B fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U when (fq.io.enq.fire) { s2_redirect := true.B } } } assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0)) when (s2_redirect) { s2_partial_insn_valid := false.B } when (io.cpu.req.valid) { wrong_path := false.B } } io.cpu.resp <> fq.io.deq // supply guest physical address to commit stage val gpa_valid = Reg(Bool()) val gpa = Reg(UInt(vaddrBitsExtended.W)) val gpa_is_pte = Reg(Bool()) when (fq.io.enq.fire && s2_tlb_resp.gf.inst) { when (!gpa_valid) { gpa := s2_tlb_resp.gpa gpa_is_pte := s2_tlb_resp.gpa_is_pte } gpa_valid := true.B } when (io.cpu.req.valid) { gpa_valid := false.B } io.cpu.gpa.valid := gpa_valid io.cpu.gpa.bits := gpa io.cpu.gpa_is_pte := gpa_is_pte // performance events io.cpu.perf.acquire := icache.io.perf.acquire io.cpu.perf.tlbMiss := io.ptw.req.fire io.errors := icache.io.errors // gate the clock clock_en_reg := !rocketParams.clockGate.B || io.cpu.might_request || // chicken bit icache.io.keep_clock_enabled || // I$ miss or ITIM access s1_valid || s2_valid || // some fetch in flight !tlb.io.req.ready || // handling TLB miss !fq.io.mask(fq.io.mask.getWidth-1) // queue not full } // leaving gated-clock domain def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1).U) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc) } /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */ trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode } frontend.resetVectorSinkNode := resetVectorNexusNode nPTWPorts += 1 // This should be a None in the case of not having an ITIM address, when we // don't actually use the device that is instantiated in the frontend. private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None } trait HasICacheFrontendModule extends CanHavePTWModule { val outer: HasICacheFrontend ptwPorts += outer.frontend.module.io.ptw } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte || fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 | rocketParams.clockGate.toInt << 1 | rocketParams.clockGate.toInt << 2 | 1 << 3 | // disableSpeculativeICacheRefill haveDCache.toInt << 9 | // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb || take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal || (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') || id_ctrl.amo && !csr.io.status.isa('a'-'a') || id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) || (id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) || id_ctrl.dp && !csr.io.status.isa('d'-'a') || ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') || id_raddr2_illegal && id_ctrl.rxs2 || id_raddr1_illegal && id_ctrl.rxs1 || id_waddr_illegal && id_ctrl.wxd || id_ctrl.rocc && csr.io.decode(0).rocc_illegal || id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) || !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) || (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc || mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) || id_vec_busy && id_ctrl.fence || id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_||_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn || id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready || ex_ctrl.div && !div.io.req.ready || ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack || wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen || ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr || wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr || tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem || io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire || v.wb.xcpt || wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) || (mem_reg_valid && mem_reg_set_vconfig) || (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked) val ctrl_stalld = id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard || id_vconfig_hazard || csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) || id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy || id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy || id_ctrl.fp && id_stall_fpu || id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay !clock_en || id_do_fence || csr.io.csr_stall || id_reg_pause || io.traceStall ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight io.ptw.customCSRs.disableCoreClockGate || // chicken bit !div.io.req.ready || // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight io.dmem.replay_next || // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_||_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_||_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens || en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S || sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File RVC.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class ExpandedInstruction extends Bundle { val bits = UInt(32.W) val rd = UInt(5.W) val rs1 = UInt(5.W) val rs2 = UInt(5.W) val rs3 = UInt(5.W) } class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) { def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = { val res = Wire(new ExpandedInstruction) res.bits := bits res.rd := rd res.rs1 := rs1 res.rs2 := rs2 res.rs3 := rs3 res } def rs1p = Cat(1.U(2.W), x(9,7)) def rs2p = Cat(1.U(2.W), x(4,2)) def rs2 = x(6,2) def rd = x(11,7) def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W)) def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W)) def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W)) def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W)) def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W)) def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W)) def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W)) def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W)) def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W)) def addiImm = Cat(Fill(7, x(12)), x(6,2)) def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W)) def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W)) def shamt = Cat(x(12), x(6,2)) def x0 = 0.U(5.W) def ra = 1.U(5.W) def sp = 2.U(5.W) def q0 = { def addi4spn = { val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W)) inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p) } def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) def flw = { if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) else ld } def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) def fsw = { if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) else sd } Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw) } def q1 = { def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p) def addiw = { val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W)) inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) } def jal = { if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p) else addiw } def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p) def addi16sp = { val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W)) inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) } def lui = { val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W)) val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p) Mux(rd === x0 || rd === sp, addi16sp, me) } def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p) def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0) def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0) def arith = { def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) def srai = srli | (1 << 30).U def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)) def rtype = { val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5))) val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U) val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W)) Cat(rs2p, rs1p, funct, rs1p, opc) | sub } inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p) } Seq(addi, jal, li, lui, arith, j, beqz, bnez) } def q2 = { val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W)) def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2) def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2) def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2) def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) def flwsp = { if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) else ldsp } def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) def fswsp = { if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) else sdsp } def jalr = { val mv = { if (useAddiForMv) inst(Cat(rs2, 0.U(3.W), rd, 0x13.U(7.W)), rd, rs2, x0) else inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2) } val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2) val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W)) val reserved = Cat(jr >> 7, 0x1F.U(7.W)) val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2) val jr_mv = Mux(rs2.orR, mv, jr_reserved) val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W)) val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2) val jalr_add = Mux(rs2.orR, add, jalr_ebreak) Mux(x(12), jalr_add, jr_mv) } Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp) } def q3 = Seq.fill(8)(passthrough) def passthrough = inst(x) def decode = { val s = q0 ++ q1 ++ q2 ++ q3 s(Cat(x(1,0), x(15,13))) } def q0_ill = { def allz = !(x(12, 2).orR) def fld = if (fLen >= 64) false.B else true.B def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B def fsd = if (fLen >= 64) false.B else true.B def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32) } def q1_ill = { def rd0 = if (xLen == 32) false.B else rd === 0.U def immz = !(x(12) | x(6, 2).orR) def arith_res = x(12, 10).andR && (if (xLen == 32) true.B else x(6) === 1.U) Seq(false.B, rd0, false.B, immz, arith_res, false.B, false.B, false.B) } def q2_ill = { def fldsp = if (fLen >= 64) false.B else true.B def rd0 = rd === 0.U def flwsp = if (xLen == 64) rd0 else if (fLen >= 32) false.B else true.B def jr_res = !(x(12 ,2).orR) def fsdsp = if (fLen >= 64) false.B else true.B def fswsp32 = if (xLen == 64) false.B else if (fLen >= 32) false.B else true.B Seq(false.B, fldsp, rd0, flwsp, jr_res, fsdsp, false.B, fswsp32) } def q3_ill = Seq.fill(8)(false.B) def ill = { val s = q0_ill ++ q1_ill ++ q2_ill ++ q3_ill s(Cat(x(1,0), x(15,13))) } } class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) extends Module with HasCoreParameters { val io = IO(new Bundle { val in = Input(UInt(32.W)) val out = Output(new ExpandedInstruction) val rvc = Output(Bool()) val ill = Output(Bool()) }) if (usingCompressed) { io.rvc := io.in(1,0) =/= 3.U val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv) io.out := decoder.decode io.ill := decoder.ill } else { io.rvc := false.B io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough io.ill := false.B // only used for RVC } }
module Frontend( // @[Frontend.scala:82:7] input clock, // @[Frontend.scala:82:7] input reset, // @[Frontend.scala:82:7] input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icache_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_cpu_might_request, // @[Frontend.scala:85:14] input io_cpu_req_valid, // @[Frontend.scala:85:14] input [39:0] io_cpu_req_bits_pc, // @[Frontend.scala:85:14] input io_cpu_req_bits_speculative, // @[Frontend.scala:85:14] input io_cpu_sfence_valid, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_rs1, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_rs2, // @[Frontend.scala:85:14] input [38:0] io_cpu_sfence_bits_addr, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_asid, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_hv, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_hg, // @[Frontend.scala:85:14] input io_cpu_resp_ready, // @[Frontend.scala:85:14] output io_cpu_resp_valid, // @[Frontend.scala:85:14] output [1:0] io_cpu_resp_bits_btb_cfiType, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_taken, // @[Frontend.scala:85:14] output [1:0] io_cpu_resp_bits_btb_mask, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_bridx, // @[Frontend.scala:85:14] output [38:0] io_cpu_resp_bits_btb_target, // @[Frontend.scala:85:14] output [4:0] io_cpu_resp_bits_btb_entry, // @[Frontend.scala:85:14] output [7:0] io_cpu_resp_bits_btb_bht_history, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_bht_value, // @[Frontend.scala:85:14] output [39:0] io_cpu_resp_bits_pc, // @[Frontend.scala:85:14] output [31:0] io_cpu_resp_bits_data, // @[Frontend.scala:85:14] output [1:0] io_cpu_resp_bits_mask, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_pf_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_gf_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_ae_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_replay, // @[Frontend.scala:85:14] output io_cpu_gpa_valid, // @[Frontend.scala:85:14] output [39:0] io_cpu_gpa_bits, // @[Frontend.scala:85:14] output io_cpu_gpa_is_pte, // @[Frontend.scala:85:14] input io_cpu_btb_update_valid, // @[Frontend.scala:85:14] input [1:0] io_cpu_btb_update_bits_prediction_cfiType, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_prediction_taken, // @[Frontend.scala:85:14] input [1:0] io_cpu_btb_update_bits_prediction_mask, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_prediction_bridx, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_prediction_target, // @[Frontend.scala:85:14] input [4:0] io_cpu_btb_update_bits_prediction_entry, // @[Frontend.scala:85:14] input [7:0] io_cpu_btb_update_bits_prediction_bht_history, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_prediction_bht_value, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_pc, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_target, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_isValid, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_br_pc, // @[Frontend.scala:85:14] input [1:0] io_cpu_btb_update_bits_cfiType, // @[Frontend.scala:85:14] input io_cpu_bht_update_valid, // @[Frontend.scala:85:14] input [7:0] io_cpu_bht_update_bits_prediction_history, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_prediction_value, // @[Frontend.scala:85:14] input [38:0] io_cpu_bht_update_bits_pc, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_branch, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_taken, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_mispredict, // @[Frontend.scala:85:14] input io_cpu_flush_icache, // @[Frontend.scala:85:14] output [39:0] io_cpu_npc, // @[Frontend.scala:85:14] output io_cpu_perf_acquire, // @[Frontend.scala:85:14] output io_cpu_perf_tlbMiss, // @[Frontend.scala:85:14] input io_cpu_progress, // @[Frontend.scala:85:14] input io_ptw_req_ready, // @[Frontend.scala:85:14] output io_ptw_req_valid, // @[Frontend.scala:85:14] output io_ptw_req_bits_valid, // @[Frontend.scala:85:14] output [26:0] io_ptw_req_bits_bits_addr, // @[Frontend.scala:85:14] output io_ptw_req_bits_bits_need_gpa, // @[Frontend.scala:85:14] input io_ptw_resp_valid, // @[Frontend.scala:85:14] input io_ptw_resp_bits_ae_ptw, // @[Frontend.scala:85:14] input io_ptw_resp_bits_ae_final, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pf, // @[Frontend.scala:85:14] input io_ptw_resp_bits_gf, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hr, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hw, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hx, // @[Frontend.scala:85:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[Frontend.scala:85:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[Frontend.scala:85:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_d, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_a, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_g, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_u, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_x, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_w, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_r, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_v, // @[Frontend.scala:85:14] input [1:0] io_ptw_resp_bits_level, // @[Frontend.scala:85:14] input io_ptw_resp_bits_homogeneous, // @[Frontend.scala:85:14] input io_ptw_resp_bits_gpa_valid, // @[Frontend.scala:85:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[Frontend.scala:85:14] input io_ptw_resp_bits_gpa_is_pte, // @[Frontend.scala:85:14] input [3:0] io_ptw_ptbr_mode, // @[Frontend.scala:85:14] input [43:0] io_ptw_ptbr_ppn, // @[Frontend.scala:85:14] input io_ptw_status_debug, // @[Frontend.scala:85:14] input io_ptw_status_cease, // @[Frontend.scala:85:14] input io_ptw_status_wfi, // @[Frontend.scala:85:14] input [31:0] io_ptw_status_isa, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_dprv, // @[Frontend.scala:85:14] input io_ptw_status_dv, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_prv, // @[Frontend.scala:85:14] input io_ptw_status_v, // @[Frontend.scala:85:14] input io_ptw_status_mpv, // @[Frontend.scala:85:14] input io_ptw_status_gva, // @[Frontend.scala:85:14] input io_ptw_status_tsr, // @[Frontend.scala:85:14] input io_ptw_status_tw, // @[Frontend.scala:85:14] input io_ptw_status_tvm, // @[Frontend.scala:85:14] input io_ptw_status_mxr, // @[Frontend.scala:85:14] input io_ptw_status_sum, // @[Frontend.scala:85:14] input io_ptw_status_mprv, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_fs, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_mpp, // @[Frontend.scala:85:14] input io_ptw_status_spp, // @[Frontend.scala:85:14] input io_ptw_status_mpie, // @[Frontend.scala:85:14] input io_ptw_status_spie, // @[Frontend.scala:85:14] input io_ptw_status_mie, // @[Frontend.scala:85:14] input io_ptw_status_sie, // @[Frontend.scala:85:14] input io_ptw_hstatus_spvp, // @[Frontend.scala:85:14] input io_ptw_hstatus_spv, // @[Frontend.scala:85:14] input io_ptw_hstatus_gva, // @[Frontend.scala:85:14] input io_ptw_gstatus_debug, // @[Frontend.scala:85:14] input io_ptw_gstatus_cease, // @[Frontend.scala:85:14] input io_ptw_gstatus_wfi, // @[Frontend.scala:85:14] input [31:0] io_ptw_gstatus_isa, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_dprv, // @[Frontend.scala:85:14] input io_ptw_gstatus_dv, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_prv, // @[Frontend.scala:85:14] input io_ptw_gstatus_v, // @[Frontend.scala:85:14] input [22:0] io_ptw_gstatus_zero2, // @[Frontend.scala:85:14] input io_ptw_gstatus_mpv, // @[Frontend.scala:85:14] input io_ptw_gstatus_gva, // @[Frontend.scala:85:14] input io_ptw_gstatus_mbe, // @[Frontend.scala:85:14] input io_ptw_gstatus_sbe, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_sxl, // @[Frontend.scala:85:14] input [7:0] io_ptw_gstatus_zero1, // @[Frontend.scala:85:14] input io_ptw_gstatus_tsr, // @[Frontend.scala:85:14] input io_ptw_gstatus_tw, // @[Frontend.scala:85:14] input io_ptw_gstatus_tvm, // @[Frontend.scala:85:14] input io_ptw_gstatus_mxr, // @[Frontend.scala:85:14] input io_ptw_gstatus_sum, // @[Frontend.scala:85:14] input io_ptw_gstatus_mprv, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_fs, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_mpp, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_vs, // @[Frontend.scala:85:14] input io_ptw_gstatus_spp, // @[Frontend.scala:85:14] input io_ptw_gstatus_mpie, // @[Frontend.scala:85:14] input io_ptw_gstatus_ube, // @[Frontend.scala:85:14] input io_ptw_gstatus_spie, // @[Frontend.scala:85:14] input io_ptw_gstatus_upie, // @[Frontend.scala:85:14] input io_ptw_gstatus_mie, // @[Frontend.scala:85:14] input io_ptw_gstatus_hie, // @[Frontend.scala:85:14] input io_ptw_gstatus_sie, // @[Frontend.scala:85:14] input io_ptw_gstatus_uie, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_0_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_0_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_1_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_1_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_2_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_2_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_3_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_3_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_4_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_4_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_5_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_5_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_6_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_6_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_7_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_7_mask, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_0_ren, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_0_wen, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_1_ren, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_1_wen, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_2_ren, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_2_wen, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_3_ren, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_3_wen, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[Frontend.scala:85:14] ); wire [1:0] btb_io_ras_update_bits_cfiType; // @[Frontend.scala:270:25, :274:40] wire _btb_io_resp_valid; // @[Frontend.scala:198:21] wire [1:0] _btb_io_resp_bits_cfiType; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_taken; // @[Frontend.scala:198:21] wire [1:0] _btb_io_resp_bits_mask; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_bridx; // @[Frontend.scala:198:21] wire [38:0] _btb_io_resp_bits_target; // @[Frontend.scala:198:21] wire [4:0] _btb_io_resp_bits_entry; // @[Frontend.scala:198:21] wire [7:0] _btb_io_resp_bits_bht_history; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_bht_value; // @[Frontend.scala:198:21] wire _btb_io_ras_head_valid; // @[Frontend.scala:198:21] wire [38:0] _btb_io_ras_head_bits; // @[Frontend.scala:198:21] wire _tlb_io_req_ready; // @[Frontend.scala:105:19] wire _tlb_io_resp_miss; // @[Frontend.scala:105:19] wire [31:0] _tlb_io_resp_paddr; // @[Frontend.scala:105:19] wire [39:0] _tlb_io_resp_gpa; // @[Frontend.scala:105:19] wire _tlb_io_resp_pf_ld; // @[Frontend.scala:105:19] wire _tlb_io_resp_pf_inst; // @[Frontend.scala:105:19] wire _tlb_io_resp_ae_ld; // @[Frontend.scala:105:19] wire _tlb_io_resp_ae_inst; // @[Frontend.scala:105:19] wire _tlb_io_resp_ma_ld; // @[Frontend.scala:105:19] wire _tlb_io_resp_cacheable; // @[Frontend.scala:105:19] wire _tlb_io_resp_prefetchable; // @[Frontend.scala:105:19] wire _fq_io_enq_ready; // @[Frontend.scala:91:64] wire [4:0] _fq_io_mask; // @[Frontend.scala:91:64] wire _icache_io_resp_valid; // @[Frontend.scala:70:26] wire [31:0] _icache_io_resp_bits_data; // @[Frontend.scala:70:26] wire _icache_io_resp_bits_ae; // @[Frontend.scala:70:26] wire auto_icache_master_out_a_ready_0 = auto_icache_master_out_a_ready; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_valid_0 = auto_icache_master_out_d_valid; // @[Frontend.scala:82:7] wire [2:0] auto_icache_master_out_d_bits_opcode_0 = auto_icache_master_out_d_bits_opcode; // @[Frontend.scala:82:7] wire [1:0] auto_icache_master_out_d_bits_param_0 = auto_icache_master_out_d_bits_param; // @[Frontend.scala:82:7] wire [3:0] auto_icache_master_out_d_bits_size_0 = auto_icache_master_out_d_bits_size; // @[Frontend.scala:82:7] wire [3:0] auto_icache_master_out_d_bits_sink_0 = auto_icache_master_out_d_bits_sink; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_bits_denied_0 = auto_icache_master_out_d_bits_denied; // @[Frontend.scala:82:7] wire [127:0] auto_icache_master_out_d_bits_data_0 = auto_icache_master_out_d_bits_data; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_bits_corrupt_0 = auto_icache_master_out_d_bits_corrupt; // @[Frontend.scala:82:7] wire io_cpu_might_request_0 = io_cpu_might_request; // @[Frontend.scala:82:7] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[Frontend.scala:82:7] wire [39:0] io_cpu_req_bits_pc_0 = io_cpu_req_bits_pc; // @[Frontend.scala:82:7] wire io_cpu_req_bits_speculative_0 = io_cpu_req_bits_speculative; // @[Frontend.scala:82:7] wire io_cpu_sfence_valid_0 = io_cpu_sfence_valid; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_rs1_0 = io_cpu_sfence_bits_rs1; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_rs2_0 = io_cpu_sfence_bits_rs2; // @[Frontend.scala:82:7] wire [38:0] io_cpu_sfence_bits_addr_0 = io_cpu_sfence_bits_addr; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_asid_0 = io_cpu_sfence_bits_asid; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_hv_0 = io_cpu_sfence_bits_hv; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_hg_0 = io_cpu_sfence_bits_hg; // @[Frontend.scala:82:7] wire io_cpu_resp_ready_0 = io_cpu_resp_ready; // @[Frontend.scala:82:7] wire io_cpu_btb_update_valid_0 = io_cpu_btb_update_valid; // @[Frontend.scala:82:7] wire [1:0] io_cpu_btb_update_bits_prediction_cfiType_0 = io_cpu_btb_update_bits_prediction_cfiType; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_prediction_taken_0 = io_cpu_btb_update_bits_prediction_taken; // @[Frontend.scala:82:7] wire [1:0] io_cpu_btb_update_bits_prediction_mask_0 = io_cpu_btb_update_bits_prediction_mask; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_prediction_bridx_0 = io_cpu_btb_update_bits_prediction_bridx; // @[Frontend.scala:82:7] wire [38:0] io_cpu_btb_update_bits_prediction_target_0 = io_cpu_btb_update_bits_prediction_target; // @[Frontend.scala:82:7] wire [4:0] io_cpu_btb_update_bits_prediction_entry_0 = io_cpu_btb_update_bits_prediction_entry; // @[Frontend.scala:82:7] wire [7:0] io_cpu_btb_update_bits_prediction_bht_history_0 = io_cpu_btb_update_bits_prediction_bht_history; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_prediction_bht_value_0 = io_cpu_btb_update_bits_prediction_bht_value; // @[Frontend.scala:82:7] wire [38:0] io_cpu_btb_update_bits_pc_0 = io_cpu_btb_update_bits_pc; // @[Frontend.scala:82:7] wire [38:0] io_cpu_btb_update_bits_target_0 = io_cpu_btb_update_bits_target; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_isValid_0 = io_cpu_btb_update_bits_isValid; // @[Frontend.scala:82:7] wire [38:0] io_cpu_btb_update_bits_br_pc_0 = io_cpu_btb_update_bits_br_pc; // @[Frontend.scala:82:7] wire [1:0] io_cpu_btb_update_bits_cfiType_0 = io_cpu_btb_update_bits_cfiType; // @[Frontend.scala:82:7] wire io_cpu_bht_update_valid_0 = io_cpu_bht_update_valid; // @[Frontend.scala:82:7] wire [7:0] io_cpu_bht_update_bits_prediction_history_0 = io_cpu_bht_update_bits_prediction_history; // @[Frontend.scala:82:7] wire io_cpu_bht_update_bits_prediction_value_0 = io_cpu_bht_update_bits_prediction_value; // @[Frontend.scala:82:7] wire [38:0] io_cpu_bht_update_bits_pc_0 = io_cpu_bht_update_bits_pc; // @[Frontend.scala:82:7] wire io_cpu_bht_update_bits_branch_0 = io_cpu_bht_update_bits_branch; // @[Frontend.scala:82:7] wire io_cpu_bht_update_bits_taken_0 = io_cpu_bht_update_bits_taken; // @[Frontend.scala:82:7] wire io_cpu_bht_update_bits_mispredict_0 = io_cpu_bht_update_bits_mispredict; // @[Frontend.scala:82:7] wire io_cpu_flush_icache_0 = io_cpu_flush_icache; // @[Frontend.scala:82:7] wire io_cpu_progress_0 = io_cpu_progress; // @[Frontend.scala:82:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[Frontend.scala:82:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[Frontend.scala:82:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[Frontend.scala:82:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[Frontend.scala:82:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[Frontend.scala:82:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[Frontend.scala:82:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[Frontend.scala:82:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[Frontend.scala:82:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[Frontend.scala:82:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[Frontend.scala:82:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[Frontend.scala:82:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[Frontend.scala:82:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[Frontend.scala:82:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[Frontend.scala:82:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[Frontend.scala:82:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[Frontend.scala:82:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[Frontend.scala:82:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[Frontend.scala:82:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[Frontend.scala:82:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[Frontend.scala:82:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[Frontend.scala:82:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[Frontend.scala:82:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[Frontend.scala:82:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[Frontend.scala:82:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[Frontend.scala:82:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[Frontend.scala:82:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[Frontend.scala:82:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[Frontend.scala:82:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[Frontend.scala:82:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[Frontend.scala:82:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[Frontend.scala:82:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[Frontend.scala:82:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[Frontend.scala:82:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[Frontend.scala:82:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[Frontend.scala:82:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[Frontend.scala:82:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[Frontend.scala:82:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[Frontend.scala:82:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[Frontend.scala:82:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[Frontend.scala:82:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[Frontend.scala:82:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[Frontend.scala:82:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[Frontend.scala:82:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[Frontend.scala:82:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[Frontend.scala:82:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_ready = 1'h1; // @[Frontend.scala:82:7] wire io_cpu_clock_enabled = 1'h1; // @[Frontend.scala:82:7] wire io_ptw_status_sd = 1'h1; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sd = 1'h1; // @[Frontend.scala:82:7] wire clock_en = 1'h1; // @[Frontend.scala:94:31] wire _taken_rviImm_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26] wire _taken_rviImm_b11_T_3 = 1'h1; // @[RocketCore.scala:1345:23] wire _taken_rviImm_b19_12_T_5 = 1'h1; // @[RocketCore.scala:1343:26] wire _taken_rviImm_b19_12_T_6 = 1'h1; // @[RocketCore.scala:1343:43] wire _taken_rviImm_b19_12_T_7 = 1'h1; // @[RocketCore.scala:1343:36] wire _taken_rviImm_b11_T_17 = 1'h1; // @[RocketCore.scala:1346:23] wire _taken_rviImm_b4_1_T_12 = 1'h1; // @[RocketCore.scala:1349:41] wire _taken_rviImm_b4_1_T_13 = 1'h1; // @[RocketCore.scala:1349:34] wire _taken_T_6 = 1'h1; // @[Frontend.scala:270:13] wire _taken_btb_io_ras_update_bits_cfiType_T_3 = 1'h1; // @[Frontend.scala:276:85] wire _taken_rviImm_b19_12_T_10 = 1'h1; // @[RocketCore.scala:1343:26] wire _taken_rviImm_b11_T_25 = 1'h1; // @[RocketCore.scala:1345:23] wire _taken_rviImm_b19_12_T_15 = 1'h1; // @[RocketCore.scala:1343:26] wire _taken_rviImm_b19_12_T_16 = 1'h1; // @[RocketCore.scala:1343:43] wire _taken_rviImm_b19_12_T_17 = 1'h1; // @[RocketCore.scala:1343:36] wire _taken_rviImm_b11_T_39 = 1'h1; // @[RocketCore.scala:1346:23] wire _taken_rviImm_b4_1_T_32 = 1'h1; // @[RocketCore.scala:1349:41] wire _taken_rviImm_b4_1_T_33 = 1'h1; // @[RocketCore.scala:1349:34] wire _taken_btb_io_ras_update_bits_cfiType_T_11 = 1'h1; // @[Frontend.scala:276:85] wire _clock_en_reg_T = 1'h1; // @[Frontend.scala:376:19] wire _clock_en_reg_T_1 = 1'h1; // @[Frontend.scala:376:45] wire _clock_en_reg_T_2 = 1'h1; // @[Frontend.scala:377:26] wire _clock_en_reg_T_3 = 1'h1; // @[Frontend.scala:378:34] wire _clock_en_reg_T_4 = 1'h1; // @[Frontend.scala:379:14] wire _clock_en_reg_T_6 = 1'h1; // @[Frontend.scala:379:26] wire _clock_en_reg_T_9 = 1'h1; // @[Frontend.scala:380:23] wire auto_icache_master_out_a_bits_source = 1'h0; // @[Frontend.scala:82:7] wire auto_icache_master_out_a_bits_corrupt = 1'h0; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_bits_source = 1'h0; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_taken = 1'h0; // @[Frontend.scala:82:7] wire io_cpu_ras_update_valid = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_mbe = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_sbe = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_ube = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_upie = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_hie = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_uie = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_vtw = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_hu = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[Frontend.scala:82:7] wire taken_rvcJAL = 1'h0; // @[Frontend.scala:245:35] wire _taken_rviImm_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _taken_rviImm_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _taken_rviImm_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43] wire _taken_rviImm_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36] wire _taken_rviImm_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _taken_rviImm_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _taken_rviImm_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _taken_rviImm_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23] wire _taken_rviImm_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _taken_rviImm_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _taken_rviImm_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _taken_rviImm_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _taken_rviImm_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _taken_rviImm_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41] wire _taken_rviImm_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34] wire _taken_rviImm_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _taken_rviImm_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _taken_rviImm_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _taken_rviImm_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _taken_rviImm_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _taken_rviImm_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire taken_rviImm_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _taken_rviImm_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _taken_rviImm_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _taken_rviImm_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _taken_rviImm_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _taken_rviImm_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _taken_rviImm_b11_T_14 = 1'h0; // @[RocketCore.scala:1345:23] wire _taken_rviImm_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _taken_rviImm_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _taken_rviImm_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _taken_rviImm_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _taken_rviImm_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _taken_rviImm_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _taken_rviImm_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _taken_rviImm_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _taken_rviImm_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _taken_rviImm_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _taken_rviImm_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire taken_rviImm_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire taken_rvcJAL_1 = 1'h0; // @[Frontend.scala:245:35] wire _taken_rviImm_sign_T_6 = 1'h0; // @[RocketCore.scala:1341:24] wire _taken_rviImm_b30_20_T_6 = 1'h0; // @[RocketCore.scala:1342:26] wire _taken_rviImm_b19_12_T_11 = 1'h0; // @[RocketCore.scala:1343:43] wire _taken_rviImm_b19_12_T_12 = 1'h0; // @[RocketCore.scala:1343:36] wire _taken_rviImm_b11_T_22 = 1'h0; // @[RocketCore.scala:1344:23] wire _taken_rviImm_b11_T_23 = 1'h0; // @[RocketCore.scala:1344:40] wire _taken_rviImm_b11_T_24 = 1'h0; // @[RocketCore.scala:1344:33] wire _taken_rviImm_b11_T_28 = 1'h0; // @[RocketCore.scala:1346:23] wire _taken_rviImm_b10_5_T_8 = 1'h0; // @[RocketCore.scala:1347:25] wire _taken_rviImm_b10_5_T_9 = 1'h0; // @[RocketCore.scala:1347:42] wire _taken_rviImm_b10_5_T_10 = 1'h0; // @[RocketCore.scala:1347:35] wire _taken_rviImm_b4_1_T_20 = 1'h0; // @[RocketCore.scala:1348:24] wire _taken_rviImm_b4_1_T_21 = 1'h0; // @[RocketCore.scala:1349:24] wire _taken_rviImm_b4_1_T_22 = 1'h0; // @[RocketCore.scala:1349:41] wire _taken_rviImm_b4_1_T_23 = 1'h0; // @[RocketCore.scala:1349:34] wire _taken_rviImm_b4_1_T_25 = 1'h0; // @[RocketCore.scala:1350:24] wire _taken_rviImm_b0_T_16 = 1'h0; // @[RocketCore.scala:1351:22] wire _taken_rviImm_b0_T_18 = 1'h0; // @[RocketCore.scala:1352:22] wire _taken_rviImm_b0_T_20 = 1'h0; // @[RocketCore.scala:1353:22] wire _taken_rviImm_b0_T_22 = 1'h0; // @[RocketCore.scala:1353:17] wire _taken_rviImm_b0_T_23 = 1'h0; // @[RocketCore.scala:1352:17] wire taken_rviImm_b0_2 = 1'h0; // @[RocketCore.scala:1351:17] wire _taken_rviImm_sign_T_9 = 1'h0; // @[RocketCore.scala:1341:24] wire _taken_rviImm_b30_20_T_9 = 1'h0; // @[RocketCore.scala:1342:26] wire _taken_rviImm_b11_T_33 = 1'h0; // @[RocketCore.scala:1344:23] wire _taken_rviImm_b11_T_34 = 1'h0; // @[RocketCore.scala:1344:40] wire _taken_rviImm_b11_T_35 = 1'h0; // @[RocketCore.scala:1344:33] wire _taken_rviImm_b11_T_36 = 1'h0; // @[RocketCore.scala:1345:23] wire _taken_rviImm_b10_5_T_12 = 1'h0; // @[RocketCore.scala:1347:25] wire _taken_rviImm_b10_5_T_13 = 1'h0; // @[RocketCore.scala:1347:42] wire _taken_rviImm_b10_5_T_14 = 1'h0; // @[RocketCore.scala:1347:35] wire _taken_rviImm_b4_1_T_30 = 1'h0; // @[RocketCore.scala:1348:24] wire _taken_rviImm_b4_1_T_31 = 1'h0; // @[RocketCore.scala:1349:24] wire _taken_rviImm_b4_1_T_35 = 1'h0; // @[RocketCore.scala:1350:24] wire _taken_rviImm_b0_T_24 = 1'h0; // @[RocketCore.scala:1351:22] wire _taken_rviImm_b0_T_26 = 1'h0; // @[RocketCore.scala:1352:22] wire _taken_rviImm_b0_T_28 = 1'h0; // @[RocketCore.scala:1353:22] wire _taken_rviImm_b0_T_30 = 1'h0; // @[RocketCore.scala:1353:17] wire _taken_rviImm_b0_T_31 = 1'h0; // @[RocketCore.scala:1352:17] wire taken_rviImm_b0_3 = 1'h0; // @[RocketCore.scala:1351:17] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[Frontend.scala:82:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[Frontend.scala:82:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[Frontend.scala:82:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Frontend.scala:82:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Frontend.scala:82:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[Frontend.scala:82:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[Frontend.scala:82:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[Frontend.scala:82:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[Frontend.scala:82:7] wire [1:0] io_cpu_ras_update_bits_cfiType = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[Frontend.scala:82:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[Frontend.scala:82:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Frontend.scala:82:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[Frontend.scala:82:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[Frontend.scala:82:7] wire [2:0] auto_icache_master_out_a_bits_opcode = 3'h4; // @[Frontend.scala:82:7] wire [2:0] auto_icache_master_out_a_bits_param = 3'h0; // @[Frontend.scala:82:7] wire [3:0] auto_icache_master_out_a_bits_size = 4'h6; // @[Frontend.scala:82:7] wire [15:0] auto_icache_master_out_a_bits_mask = 16'hFFFF; // @[Frontend.scala:82:7] wire [127:0] auto_icache_master_out_a_bits_data = 128'h0; // @[Frontend.scala:82:7] wire [31:0] auto_reset_vector_sink_in = 32'h10000; // @[Frontend.scala:82:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [31:0] _s2_pc_T_2 = 32'h10000; // @[Frontend.scala:384:27] wire [38:0] io_cpu_ras_update_bits_returnAddr = 39'h0; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[Frontend.scala:82:7] wire [31:0] _s2_pc_T = 32'hFFFEFFFF; // @[Frontend.scala:384:29] wire [31:0] _s2_pc_T_1 = 32'hFFFEFFFF; // @[Frontend.scala:384:33] wire [39:0] _io_cpu_npc_T_3; // @[Frontend.scala:384:27] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire [31:0] auto_icache_master_out_a_bits_address_0; // @[Frontend.scala:82:7] wire auto_icache_master_out_a_valid_0; // @[Frontend.scala:82:7] wire [7:0] io_cpu_resp_bits_btb_bht_history_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_btb_bht_value_0; // @[Frontend.scala:82:7] wire [1:0] io_cpu_resp_bits_btb_cfiType_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_btb_taken_0; // @[Frontend.scala:82:7] wire [1:0] io_cpu_resp_bits_btb_mask_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_btb_bridx_0; // @[Frontend.scala:82:7] wire [38:0] io_cpu_resp_bits_btb_target_0; // @[Frontend.scala:82:7] wire [4:0] io_cpu_resp_bits_btb_entry_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_xcpt_pf_inst_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_xcpt_gf_inst_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_xcpt_ae_inst_0; // @[Frontend.scala:82:7] wire [39:0] io_cpu_resp_bits_pc_0; // @[Frontend.scala:82:7] wire [31:0] io_cpu_resp_bits_data_0; // @[Frontend.scala:82:7] wire [1:0] io_cpu_resp_bits_mask_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_replay_0; // @[Frontend.scala:82:7] wire io_cpu_resp_valid_0; // @[Frontend.scala:82:7] wire io_cpu_gpa_valid_0; // @[Frontend.scala:82:7] wire [39:0] io_cpu_gpa_bits_0; // @[Frontend.scala:82:7] wire io_cpu_perf_acquire_0; // @[Frontend.scala:82:7] wire io_cpu_perf_tlbMiss_0; // @[Frontend.scala:82:7] wire io_cpu_gpa_is_pte_0; // @[Frontend.scala:82:7] wire [39:0] io_cpu_npc_0; // @[Frontend.scala:82:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[Frontend.scala:82:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[Frontend.scala:82:7] wire io_ptw_req_bits_valid_0; // @[Frontend.scala:82:7] wire io_ptw_req_valid_0; // @[Frontend.scala:82:7] wire io_errors_bus_valid; // @[Frontend.scala:82:7] wire [31:0] io_errors_bus_bits; // @[Frontend.scala:82:7] reg s1_valid; // @[Frontend.scala:107:21] reg s2_valid; // @[Frontend.scala:108:25] wire _s0_fq_has_space_T = _fq_io_mask[2]; // @[Frontend.scala:91:64, :110:16] wire _s0_fq_has_space_T_1 = ~_s0_fq_has_space_T; // @[Frontend.scala:110:{5,16}] wire _s0_fq_has_space_T_2 = _fq_io_mask[3]; // @[Frontend.scala:91:64, :111:17] wire _s0_fq_has_space_T_3 = ~_s0_fq_has_space_T_2; // @[Frontend.scala:111:{6,17}] wire _s0_fq_has_space_T_4 = ~s1_valid; // @[Frontend.scala:107:21, :111:45] wire _s0_fq_has_space_T_5 = ~s2_valid; // @[Frontend.scala:108:25, :111:58] wire _s0_fq_has_space_T_6 = _s0_fq_has_space_T_4 | _s0_fq_has_space_T_5; // @[Frontend.scala:111:{45,55,58}] wire _s0_fq_has_space_T_7 = _s0_fq_has_space_T_3 & _s0_fq_has_space_T_6; // @[Frontend.scala:111:{6,41,55}] wire _s0_fq_has_space_T_8 = _s0_fq_has_space_T_1 | _s0_fq_has_space_T_7; // @[Frontend.scala:110:{5,40}, :111:41] wire _s0_fq_has_space_T_9 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17] wire _clock_en_reg_T_7 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17, :381:16] wire _s0_fq_has_space_T_10 = ~_s0_fq_has_space_T_9; // @[Frontend.scala:112:{6,17}] wire _s0_fq_has_space_T_11 = ~s1_valid; // @[Frontend.scala:107:21, :111:45, :112:45] wire _s0_fq_has_space_T_12 = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :112:58] wire _s0_fq_has_space_T_13 = _s0_fq_has_space_T_11 & _s0_fq_has_space_T_12; // @[Frontend.scala:112:{45,55,58}] wire _s0_fq_has_space_T_14 = _s0_fq_has_space_T_10 & _s0_fq_has_space_T_13; // @[Frontend.scala:112:{6,41,55}] wire s0_fq_has_space = _s0_fq_has_space_T_8 | _s0_fq_has_space_T_14; // @[Frontend.scala:110:40, :111:70, :112:41] wire s0_valid = io_cpu_req_valid_0 | s0_fq_has_space; // @[Frontend.scala:82:7, :111:70, :113:35] reg [39:0] s1_pc; // @[Frontend.scala:115:18] reg s1_speculative; // @[Frontend.scala:116:27] reg [39:0] s2_pc; // @[Frontend.scala:117:22] reg s2_btb_resp_valid; // @[Frontend.scala:118:44] reg [1:0] s2_btb_resp_bits_cfiType; // @[Frontend.scala:119:29] reg s2_btb_resp_bits_taken; // @[Frontend.scala:119:29] reg [1:0] s2_btb_resp_bits_mask; // @[Frontend.scala:119:29] reg s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29] wire _taken_T_30 = s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69] reg [38:0] s2_btb_resp_bits_target; // @[Frontend.scala:119:29] reg [4:0] s2_btb_resp_bits_entry; // @[Frontend.scala:119:29] reg [7:0] s2_btb_resp_bits_bht_history; // @[Frontend.scala:119:29] reg s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire _taken_predict_taken_T = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire _taken_T_23 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire _taken_predict_taken_T_1 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire _taken_T_52 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire s2_btb_taken = s2_btb_resp_valid & s2_btb_resp_bits_taken; // @[Frontend.scala:118:44, :119:29, :120:40] reg s2_tlb_resp_miss; // @[Frontend.scala:121:24] reg [31:0] s2_tlb_resp_paddr; // @[Frontend.scala:121:24] reg [39:0] s2_tlb_resp_gpa; // @[Frontend.scala:121:24] reg s2_tlb_resp_pf_ld; // @[Frontend.scala:121:24] reg s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24] reg s2_tlb_resp_ae_ld; // @[Frontend.scala:121:24] reg s2_tlb_resp_ae_inst; // @[Frontend.scala:121:24] reg s2_tlb_resp_ma_ld; // @[Frontend.scala:121:24] reg s2_tlb_resp_cacheable; // @[Frontend.scala:121:24] reg s2_tlb_resp_prefetchable; // @[Frontend.scala:121:24] wire _s2_xcpt_T = s2_tlb_resp_ae_inst | s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24, :122:37] wire s2_xcpt = _s2_xcpt_T; // @[Frontend.scala:122:{37,60}] reg s2_speculative; // @[Frontend.scala:123:31] reg s2_partial_insn_valid; // @[Frontend.scala:124:38] reg [15:0] s2_partial_insn; // @[Frontend.scala:125:28] reg wrong_path; // @[Frontend.scala:126:27] wire [39:0] _s1_base_pc_T = ~s1_pc; // @[Frontend.scala:115:18, :128:22] wire [39:0] _s1_base_pc_T_1 = {_s1_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:128:{22,29}] wire [39:0] s1_base_pc = ~_s1_base_pc_T_1; // @[Frontend.scala:128:{20,29}] wire [40:0] _ntpc_T = {1'h0, s1_base_pc} + 41'h4; // @[Frontend.scala:128:20, :129:25] wire [39:0] ntpc = _ntpc_T[39:0]; // @[Frontend.scala:129:25] wire [39:0] predicted_npc; // @[Frontend.scala:130:34] wire predicted_taken; // @[Frontend.scala:131:36] wire _s2_replay_T_5; // @[Frontend.scala:134:46] wire s2_replay; // @[Frontend.scala:133:23] wire _fq_io_enq_valid_T_6; // @[Frontend.scala:184:52] wire _T_37 = _fq_io_enq_ready & _fq_io_enq_valid_T_6; // @[Decoupled.scala:51:35] wire _s2_replay_T; // @[Decoupled.scala:51:35] assign _s2_replay_T = _T_37; // @[Decoupled.scala:51:35] wire _btb_io_btb_update_valid_T; // @[Decoupled.scala:51:35] assign _btb_io_btb_update_valid_T = _T_37; // @[Decoupled.scala:51:35] wire _taken_btb_io_ras_update_valid_T; // @[Decoupled.scala:51:35] assign _taken_btb_io_ras_update_valid_T = _T_37; // @[Decoupled.scala:51:35] wire _taken_T_8; // @[Decoupled.scala:51:35] assign _taken_T_8 = _T_37; // @[Decoupled.scala:51:35] wire _taken_btb_io_bht_advance_valid_T; // @[Decoupled.scala:51:35] assign _taken_btb_io_bht_advance_valid_T = _T_37; // @[Decoupled.scala:51:35] wire _taken_btb_io_ras_update_valid_T_9; // @[Decoupled.scala:51:35] assign _taken_btb_io_ras_update_valid_T_9 = _T_37; // @[Decoupled.scala:51:35] wire _taken_T_37; // @[Decoupled.scala:51:35] assign _taken_T_37 = _T_37; // @[Decoupled.scala:51:35] wire _taken_btb_io_bht_advance_valid_T_3; // @[Decoupled.scala:51:35] assign _taken_btb_io_bht_advance_valid_T_3 = _T_37; // @[Decoupled.scala:51:35] wire _taken_T_57; // @[Decoupled.scala:51:35] assign _taken_T_57 = _T_37; // @[Decoupled.scala:51:35] wire _s2_replay_T_1 = ~_s2_replay_T; // @[Decoupled.scala:51:35] wire _s2_replay_T_2 = s2_valid & _s2_replay_T_1; // @[Frontend.scala:108:25, :134:{26,29}] wire _s2_replay_T_3 = ~s0_valid; // @[Frontend.scala:113:35, :134:70] wire _s2_replay_T_4 = s2_replay & _s2_replay_T_3; // @[Frontend.scala:133:23, :134:{67,70}] reg s2_replay_REG; // @[Frontend.scala:134:56] assign _s2_replay_T_5 = _s2_replay_T_2 | s2_replay_REG; // @[Frontend.scala:134:{26,46,56}] assign s2_replay = _s2_replay_T_5; // @[Frontend.scala:133:23, :134:46] wire [39:0] npc = s2_replay ? s2_pc : predicted_npc; // @[Frontend.scala:117:22, :130:34, :133:23, :135:16] wire _s0_speculative_T = ~s2_speculative; // @[Frontend.scala:123:31, :141:56] wire _s0_speculative_T_1 = s2_valid & _s0_speculative_T; // @[Frontend.scala:108:25, :141:{53,56}] wire _s0_speculative_T_2 = s1_speculative | _s0_speculative_T_1; // @[Frontend.scala:116:27, :141:{41,53}] wire s0_speculative = _s0_speculative_T_2 | predicted_taken; // @[Frontend.scala:131:36, :141:{41,72}] wire _s1_speculative_T = s2_replay ? s2_speculative : s0_speculative; // @[Frontend.scala:123:31, :133:23, :141:72, :143:75] wire _s1_speculative_T_1 = io_cpu_req_valid_0 ? io_cpu_req_bits_speculative_0 : _s1_speculative_T; // @[Frontend.scala:82:7, :143:{24,75}] wire s2_redirect; // @[Frontend.scala:145:32] wire _s2_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17] reg [1:0] recent_progress_counter; // @[Frontend.scala:155:40] wire recent_progress = |recent_progress_counter; // @[Frontend.scala:155:40, :156:49] assign _io_cpu_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire [2:0] _recent_progress_counter_T = {1'h0, recent_progress_counter} - 3'h1; // @[Frontend.scala:155:40, :157:97] wire [1:0] _recent_progress_counter_T_1 = _recent_progress_counter_T[1:0]; // @[Frontend.scala:157:97] wire _s2_kill_speculative_tlb_refill_T = ~recent_progress; // @[Frontend.scala:156:49, :160:58] wire s2_kill_speculative_tlb_refill = s2_speculative & _s2_kill_speculative_tlb_refill_T; // @[Frontend.scala:123:31, :160:{55,58}] wire _tlb_io_req_valid_T = ~s2_replay; // @[Frontend.scala:133:23, :147:9, :163:35] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[Frontend.scala:107:21, :163:{32,35}] wire _tlb_io_kill_T = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :171:18] wire _tlb_io_kill_T_1 = _tlb_io_kill_T | s2_kill_speculative_tlb_refill; // @[Frontend.scala:160:55, :171:{18,28}] wire _icache_io_s1_kill_T = s2_redirect | _tlb_io_resp_miss; // @[Frontend.scala:105:19, :145:32, :178:36] wire _icache_io_s1_kill_T_1 = _icache_io_s1_kill_T | s2_replay; // @[Frontend.scala:133:23, :178:{36,56}] wire _s2_can_speculatively_refill_T = io_ptw_customCSRs_csrs_0_value_0[3]; // @[CustomCSRs.scala:46:69] wire _s2_can_speculatively_refill_T_1 = ~_s2_can_speculatively_refill_T; // @[CustomCSRs.scala:46:69] wire s2_can_speculatively_refill = s2_tlb_resp_cacheable & _s2_can_speculatively_refill_T_1; // @[Frontend.scala:121:24, :179:{59,62}] wire _icache_io_s2_kill_T = ~s2_can_speculatively_refill; // @[Frontend.scala:179:59, :180:42] wire _icache_io_s2_kill_T_1 = s2_speculative & _icache_io_s2_kill_T; // @[Frontend.scala:123:31, :180:{39,42}] wire _icache_io_s2_kill_T_2 = _icache_io_s2_kill_T_1 | s2_xcpt; // @[Frontend.scala:122:60, :180:{39,71}] wire _icache_io_s2_prefetch_T = io_ptw_customCSRs_csrs_0_value_0[17]; // @[RocketCore.scala:115:60] wire _icache_io_s2_prefetch_T_1 = ~_icache_io_s2_prefetch_T; // @[RocketCore.scala:115:60] wire _icache_io_s2_prefetch_T_2 = s2_tlb_resp_prefetchable & _icache_io_s2_prefetch_T_1; // @[Frontend.scala:121:24, :182:{53,56}] reg fq_io_enq_valid_REG; // @[Frontend.scala:184:29] wire _fq_io_enq_valid_T = fq_io_enq_valid_REG & s2_valid; // @[Frontend.scala:108:25, :184:{29,40}] wire _GEN = s2_kill_speculative_tlb_refill & s2_tlb_resp_miss; // @[Frontend.scala:121:24, :160:55, :184:112] wire _fq_io_enq_valid_T_1; // @[Frontend.scala:184:112] assign _fq_io_enq_valid_T_1 = _GEN; // @[Frontend.scala:184:112] wire _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:150] assign _fq_io_enq_bits_replay_T_5 = _GEN; // @[Frontend.scala:184:112, :190:150] wire _fq_io_enq_valid_T_2 = _icache_io_resp_valid | _fq_io_enq_valid_T_1; // @[Frontend.scala:70:26, :184:{77,112}] wire _fq_io_enq_valid_T_3 = ~s2_tlb_resp_miss; // @[Frontend.scala:121:24, :184:137] wire _fq_io_enq_valid_T_4 = _fq_io_enq_valid_T_3 & _icache_io_s2_kill_T_2; // @[Frontend.scala:180:71, :184:{137,155}] wire _fq_io_enq_valid_T_5 = _fq_io_enq_valid_T_2 | _fq_io_enq_valid_T_4; // @[Frontend.scala:184:{77,133,155}] assign _fq_io_enq_valid_T_6 = _fq_io_enq_valid_T & _fq_io_enq_valid_T_5; // @[Frontend.scala:184:{40,52,133}] wire [39:0] _io_cpu_npc_T = io_cpu_req_valid_0 ? io_cpu_req_bits_pc_0 : npc; // @[Frontend.scala:82:7, :135:16, :186:28] wire [39:0] _io_cpu_npc_T_1 = ~_io_cpu_npc_T; // @[Frontend.scala:186:28, :384:29] wire [39:0] _io_cpu_npc_T_2 = {_io_cpu_npc_T_1[39:1], 1'h1}; // @[Frontend.scala:384:{29,33}] assign _io_cpu_npc_T_3 = ~_io_cpu_npc_T_2; // @[Frontend.scala:384:{27,33}] assign io_cpu_npc_0 = _io_cpu_npc_T_3; // @[Frontend.scala:82:7, :384:27] wire _fq_io_enq_bits_mask_T = s2_pc[1]; // @[package.scala:163:13] wire [2:0] _fq_io_enq_bits_mask_T_1 = 3'h3 << _fq_io_enq_bits_mask_T; // @[package.scala:163:13] wire _fq_io_enq_bits_replay_T = ~_icache_io_resp_valid; // @[Frontend.scala:70:26, :190:80] wire _fq_io_enq_bits_replay_T_1 = _icache_io_s2_kill_T_2 & _fq_io_enq_bits_replay_T; // @[Frontend.scala:180:71, :190:{77,80}] wire _fq_io_enq_bits_replay_T_2 = ~s2_xcpt; // @[Frontend.scala:122:60, :190:105] wire _fq_io_enq_bits_replay_T_3 = _fq_io_enq_bits_replay_T_1 & _fq_io_enq_bits_replay_T_2; // @[Frontend.scala:190:{77,102,105}] wire _fq_io_enq_bits_replay_T_4 = _fq_io_enq_bits_replay_T_3; // @[Frontend.scala:190:{56,102}] wire _fq_io_enq_bits_replay_T_6 = _fq_io_enq_bits_replay_T_4 | _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:{56,115,150}] wire _btb_io_req_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17, :209:27] assign predicted_taken = _btb_io_resp_valid & _btb_io_resp_bits_taken; // @[Frontend.scala:131:36, :198:21, :213:29] wire _predicted_npc_T = _btb_io_resp_bits_target[38]; // @[package.scala:132:38] wire [39:0] _predicted_npc_T_1 = {_predicted_npc_T, _btb_io_resp_bits_target}; // @[package.scala:132:{15,38}] wire [39:0] _s2_base_pc_T = ~s2_pc; // @[Frontend.scala:117:22, :222:24] wire [39:0] _s2_base_pc_T_1 = {_s2_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:222:{24,31}] wire [39:0] s2_base_pc = ~_s2_base_pc_T_1; // @[Frontend.scala:222:{22,31}] wire [39:0] taken_pc = s2_base_pc; // @[Frontend.scala:222:22, :287:33] wire _taken_T_35; // @[Frontend.scala:270:13] wire taken_idx; // @[Frontend.scala:223:25] wire [1:0] after_idx; // @[Frontend.scala:224:25] wire useRAS; // @[Frontend.scala:225:29] wire updateBTB; // @[Frontend.scala:226:32] wire _fetch_bubble_likely_T = _fq_io_mask[1]; // @[Frontend.scala:91:64, :318:44] wire fetch_bubble_likely = ~_fetch_bubble_likely_T; // @[Frontend.scala:318:{33,44}] wire _btb_io_btb_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :319:52] wire _btb_io_btb_update_valid_T_2 = _btb_io_btb_update_valid_T & _btb_io_btb_update_valid_T_1; // @[Decoupled.scala:51:35] wire _btb_io_btb_update_valid_T_3 = _btb_io_btb_update_valid_T_2 & fetch_bubble_likely; // @[Frontend.scala:318:33, :319:{49,64}] wire _btb_io_btb_update_valid_T_4 = _btb_io_btb_update_valid_T_3 & updateBTB; // @[Frontend.scala:226:32, :319:{64,87}] wire [1:0] _btb_io_btb_update_bits_br_pc_T = {taken_idx, 1'h0}; // @[Frontend.scala:223:25, :323:63] wire [39:0] _btb_io_btb_update_bits_br_pc_T_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | _btb_io_btb_update_bits_br_pc_T}; // @[Frontend.scala:222:22, :323:{50,63}] wire [2:0] _btb_io_ras_update_bits_returnAddr_T = {after_idx, 1'h0}; // @[Frontend.scala:224:25, :327:66] wire [40:0] _btb_io_ras_update_bits_returnAddr_T_1 = {1'h0, s2_base_pc} + {38'h0, _btb_io_ras_update_bits_returnAddr_T}; // @[Frontend.scala:129:25, :222:22, :327:{53,66}] wire [39:0] _btb_io_ras_update_bits_returnAddr_T_2 = _btb_io_ras_update_bits_returnAddr_T_1[39:0]; // @[Frontend.scala:327:53] wire [1:0] _taken_prevRVI_T = s2_partial_insn[1:0]; // @[Frontend.scala:125:28, :233:39] wire _taken_prevRVI_T_1 = _taken_prevRVI_T != 2'h3; // @[Frontend.scala:233:{39,45}] wire _taken_prevRVI_T_2 = ~_taken_prevRVI_T_1; // @[Frontend.scala:233:45, :234:34] wire taken_prevRVI = s2_partial_insn_valid & _taken_prevRVI_T_2; // @[Frontend.scala:124:38, :234:{31,34}] wire _taken_valid_T = _fq_io_enq_bits_mask_T_1[0]; // @[Frontend.scala:189:50, :235:38] wire _taken_valid_T_1 = ~taken_prevRVI; // @[Frontend.scala:234:31, :235:47] wire taken_valid = _taken_valid_T & _taken_valid_T_1; // @[Frontend.scala:235:{38,44,47}] wire [15:0] taken_bits = _icache_io_resp_bits_data[15:0]; // @[Frontend.scala:70:26, :236:37] wire [1:0] _taken_rvc_T = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37] wire [1:0] _taken_prevRVI_T_3 = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37] wire taken_rvc = _taken_rvc_T != 2'h3; // @[Frontend.scala:233:{39,45}] wire [31:0] taken_rviBits = {taken_bits, s2_partial_insn}; // @[Frontend.scala:125:28, :236:37, :238:24] wire [6:0] _taken_rviBranch_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30] wire [6:0] _taken_rviJump_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28] wire [6:0] _taken_rviJALR_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28] wire taken_rviBranch = _taken_rviBranch_T == 7'h63; // @[Frontend.scala:239:{30,36}] wire taken_rviJump = _taken_rviJump_T == 7'h6F; // @[Frontend.scala:240:{28,34}] wire taken_rviJALR = _taken_rviJALR_T == 7'h67; // @[Frontend.scala:241:{28,34}] wire _taken_rviReturn_T = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42] wire _taken_rviCall_T_1 = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42, :243:52] wire _taken_rviImm_b11_T_7 = taken_rviBits[7]; // @[RocketCore.scala:1346:39] wire _taken_rviImm_b0_T_1 = taken_rviBits[7]; // @[RocketCore.scala:1351:37] wire _taken_rviImm_b11_T_18 = taken_rviBits[7]; // @[RocketCore.scala:1346:39] wire _taken_rviImm_b0_T_9 = taken_rviBits[7]; // @[RocketCore.scala:1351:37] wire _taken_rviReturn_T_1 = ~_taken_rviReturn_T; // @[Frontend.scala:242:{34,42}] wire _taken_rviReturn_T_2 = taken_rviJALR & _taken_rviReturn_T_1; // @[Frontend.scala:241:34, :242:{31,34}] wire [4:0] _taken_rviReturn_T_3 = taken_rviBits[19:15]; // @[Frontend.scala:238:24, :242:77] wire [4:0] _taken_rviReturn_T_4 = _taken_rviReturn_T_3 & 5'h1B; // @[Frontend.scala:242:{66,77}] wire _taken_rviReturn_T_5 = _taken_rviReturn_T_4 == 5'h1; // @[Frontend.scala:242:66] wire taken_rviReturn = _taken_rviReturn_T_2 & _taken_rviReturn_T_5; // @[Frontend.scala:242:{31,46,66}] wire _GEN_0 = taken_rviJALR | taken_rviJump; // @[Frontend.scala:240:34, :241:34, :243:30] wire _taken_rviCall_T; // @[Frontend.scala:243:30] assign _taken_rviCall_T = _GEN_0; // @[Frontend.scala:243:30] wire _taken_taken_T; // @[Frontend.scala:255:29] assign _taken_taken_T = _GEN_0; // @[Frontend.scala:243:30, :255:29] wire taken_rviCall = _taken_rviCall_T & _taken_rviCall_T_1; // @[Frontend.scala:243:{30,42,52}] wire [15:0] _GEN_1 = taken_bits & 16'hE003; // @[Frontend.scala:236:37, :244:28] wire [15:0] _taken_rvcBranch_T; // @[Frontend.scala:244:28] assign _taken_rvcBranch_T = _GEN_1; // @[Frontend.scala:244:28] wire [15:0] _taken_rvcBranch_T_2; // @[Frontend.scala:244:60] assign _taken_rvcBranch_T_2 = _GEN_1; // @[Frontend.scala:244:{28,60}] wire [15:0] _taken_rvcJAL_T; // @[Frontend.scala:245:43] assign _taken_rvcJAL_T = _GEN_1; // @[Frontend.scala:244:28, :245:43] wire [15:0] _taken_rvcJump_T; // @[Frontend.scala:246:26] assign _taken_rvcJump_T = _GEN_1; // @[Frontend.scala:244:28, :246:26] wire _taken_rvcBranch_T_1 = _taken_rvcBranch_T == 16'hC001; // @[Frontend.scala:244:28] wire _taken_rvcBranch_T_3 = _taken_rvcBranch_T_2 == 16'hE001; // @[Frontend.scala:244:60] wire taken_rvcBranch = _taken_rvcBranch_T_1 | _taken_rvcBranch_T_3; // @[Frontend.scala:244:{28,52,60}] wire _taken_rvcJAL_T_1 = _taken_rvcJAL_T == 16'h2001; // @[Frontend.scala:245:43] wire _taken_rvcJump_T_1 = _taken_rvcJump_T == 16'hA001; // @[Frontend.scala:246:26] wire taken_rvcJump = _taken_rvcJump_T_1; // @[Frontend.scala:246:{26,47}] wire _taken_rvcImm_T = taken_bits[14]; // @[Frontend.scala:236:37, :247:28] wire _taken_rvcImm_T_1 = taken_bits[12]; // @[RVC.scala:45:27] wire _taken_rvcImm_T_9 = taken_bits[12]; // @[RVC.scala:44:28, :45:27] wire [4:0] _taken_rvcImm_T_2 = {5{_taken_rvcImm_T_1}}; // @[RVC.scala:45:{22,27}] wire [1:0] _taken_rvcImm_T_3 = taken_bits[6:5]; // @[RVC.scala:45:35] wire _taken_rvcImm_T_4 = taken_bits[2]; // @[RVC.scala:45:43] wire _taken_rvcImm_T_15 = taken_bits[2]; // @[RVC.scala:44:63, :45:43] wire [1:0] _taken_rvcImm_T_5 = taken_bits[11:10]; // @[RVC.scala:45:49] wire [1:0] _taken_rvcImm_T_6 = taken_bits[4:3]; // @[RVC.scala:45:59] wire [3:0] taken_rvcImm_lo_hi = {_taken_rvcImm_T_5, _taken_rvcImm_T_6}; // @[RVC.scala:45:{17,49,59}] wire [4:0] taken_rvcImm_lo = {taken_rvcImm_lo_hi, 1'h0}; // @[RVC.scala:45:17] wire [6:0] taken_rvcImm_hi_hi = {_taken_rvcImm_T_2, _taken_rvcImm_T_3}; // @[RVC.scala:45:{17,22,35}] wire [7:0] taken_rvcImm_hi = {taken_rvcImm_hi_hi, _taken_rvcImm_T_4}; // @[RVC.scala:45:{17,43}] wire [12:0] _taken_rvcImm_T_7 = {taken_rvcImm_hi, taken_rvcImm_lo}; // @[RVC.scala:45:17] wire [12:0] _taken_rvcImm_T_8 = _taken_rvcImm_T_7; // @[RVC.scala:45:17] wire [9:0] _taken_rvcImm_T_10 = {10{_taken_rvcImm_T_9}}; // @[RVC.scala:44:{22,28}] wire _taken_rvcImm_T_11 = taken_bits[8]; // @[RVC.scala:44:36] wire [1:0] _taken_rvcImm_T_12 = taken_bits[10:9]; // @[RVC.scala:44:42] wire _taken_rvcImm_T_13 = taken_bits[6]; // @[RVC.scala:44:51] wire _taken_rvcImm_T_14 = taken_bits[7]; // @[RVC.scala:44:57] wire _taken_rvcImm_T_16 = taken_bits[11]; // @[RVC.scala:44:69] wire [2:0] _taken_rvcImm_T_17 = taken_bits[5:3]; // @[RVC.scala:44:76] wire [3:0] taken_rvcImm_lo_lo = {_taken_rvcImm_T_17, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] taken_rvcImm_lo_hi_1 = {_taken_rvcImm_T_15, _taken_rvcImm_T_16}; // @[RVC.scala:44:{17,63,69}] wire [5:0] taken_rvcImm_lo_1 = {taken_rvcImm_lo_hi_1, taken_rvcImm_lo_lo}; // @[RVC.scala:44:17] wire [1:0] taken_rvcImm_hi_lo = {_taken_rvcImm_T_13, _taken_rvcImm_T_14}; // @[RVC.scala:44:{17,51,57}] wire [10:0] taken_rvcImm_hi_hi_hi = {_taken_rvcImm_T_10, _taken_rvcImm_T_11}; // @[RVC.scala:44:{17,22,36}] wire [12:0] taken_rvcImm_hi_hi_1 = {taken_rvcImm_hi_hi_hi, _taken_rvcImm_T_12}; // @[RVC.scala:44:{17,42}] wire [14:0] taken_rvcImm_hi_1 = {taken_rvcImm_hi_hi_1, taken_rvcImm_hi_lo}; // @[RVC.scala:44:17] wire [20:0] _taken_rvcImm_T_18 = {taken_rvcImm_hi_1, taken_rvcImm_lo_1}; // @[RVC.scala:44:17] wire [20:0] _taken_rvcImm_T_19 = _taken_rvcImm_T_18; // @[RVC.scala:44:17] wire [20:0] taken_rvcImm = _taken_rvcImm_T ? {{8{_taken_rvcImm_T_8[12]}}, _taken_rvcImm_T_8} : _taken_rvcImm_T_19; // @[Frontend.scala:247:{23,28,72,118}] wire [15:0] _GEN_2 = taken_bits & 16'hF003; // @[Frontend.scala:236:37, :248:24] wire [15:0] _taken_rvcJR_T; // @[Frontend.scala:248:24] assign _taken_rvcJR_T = _GEN_2; // @[Frontend.scala:248:24] wire [15:0] _taken_rvcJALR_T; // @[Frontend.scala:250:26] assign _taken_rvcJALR_T = _GEN_2; // @[Frontend.scala:248:24, :250:26] wire _taken_rvcJR_T_1 = _taken_rvcJR_T == 16'h8002; // @[Frontend.scala:248:24] wire [4:0] _taken_rvcJR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53] wire [4:0] _taken_rvcJALR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56] wire _taken_rvcJR_T_3 = _taken_rvcJR_T_2 == 5'h0; // @[Frontend.scala:248:{53,59}] wire taken_rvcJR = _taken_rvcJR_T_1 & _taken_rvcJR_T_3; // @[Frontend.scala:248:{24,46,59}] wire [4:0] _taken_rvcReturn_T = taken_bits[11:7]; // @[Frontend.scala:236:37, :249:57] wire [4:0] _taken_rvcReturn_T_1 = _taken_rvcReturn_T & 5'h1B; // @[Frontend.scala:249:{49,57}] wire _taken_rvcReturn_T_2 = _taken_rvcReturn_T_1 == 5'h1; // @[Frontend.scala:249:49] wire taken_rvcReturn = taken_rvcJR & _taken_rvcReturn_T_2; // @[Frontend.scala:248:46, :249:{29,49}] wire _taken_rvcJALR_T_1 = _taken_rvcJALR_T == 16'h9002; // @[Frontend.scala:250:26] wire _taken_rvcJALR_T_3 = _taken_rvcJALR_T_2 == 5'h0; // @[Frontend.scala:250:{56,62}] wire taken_rvcJALR = _taken_rvcJALR_T_1 & _taken_rvcJALR_T_3; // @[Frontend.scala:250:{26,49,62}] wire taken_rvcCall = taken_rvcJALR; // @[Frontend.scala:250:49, :251:28] wire _taken_rviImm_T = taken_rviBits[3]; // @[Frontend.scala:238:24, :252:31] wire _taken_rviImm_sign_T_1 = taken_rviBits[31]; // @[RocketCore.scala:1341:44] wire _taken_rviImm_sign_T_4 = taken_rviBits[31]; // @[RocketCore.scala:1341:44] wire _taken_rviImm_sign_T_2 = _taken_rviImm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire taken_rviImm_sign = _taken_rviImm_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire _taken_rviImm_b11_T_9 = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1346:18] wire taken_rviImm_hi_hi_hi = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _taken_rviImm_b30_20_T_1 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41] wire [10:0] _taken_rviImm_b30_20_T_4 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41] wire [10:0] _taken_rviImm_b30_20_T_2 = _taken_rviImm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] taken_rviImm_b30_20 = {11{taken_rviImm_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] taken_rviImm_hi_hi_lo = taken_rviImm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _taken_rviImm_b19_12_T_3 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65] wire [7:0] _taken_rviImm_b19_12_T_8 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65] wire [7:0] _taken_rviImm_b19_12_T_4 = _taken_rviImm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] taken_rviImm_b19_12 = _taken_rviImm_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}] wire [7:0] taken_rviImm_hi_lo_hi = taken_rviImm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _taken_rviImm_b11_T_4 = taken_rviBits[20]; // @[RocketCore.scala:1345:39] wire _taken_rviImm_b0_T_3 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37] wire _taken_rviImm_b11_T_15 = taken_rviBits[20]; // @[RocketCore.scala:1345:39] wire _taken_rviImm_b0_T_11 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37] wire _taken_rviImm_b11_T_5 = _taken_rviImm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _taken_rviImm_b11_T_10 = _taken_rviImm_b11_T_5; // @[RocketCore.scala:1345:{18,44}] wire _taken_rviImm_b11_T_8 = _taken_rviImm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire taken_rviImm_b11 = _taken_rviImm_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire taken_rviImm_hi_lo_lo = taken_rviImm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _taken_rviImm_b10_5_T_3 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62] wire [5:0] _taken_rviImm_b10_5_T_7 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62] wire [5:0] taken_rviImm_b10_5 = _taken_rviImm_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _taken_rviImm_b4_1_T_4 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57] wire [3:0] _taken_rviImm_b4_1_T_14 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57] wire [3:0] _taken_rviImm_b4_1_T_6 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39] wire [3:0] _taken_rviImm_b4_1_T_16 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39] wire [3:0] _taken_rviImm_b4_1_T_7 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52] wire [3:0] _taken_rviImm_b4_1_T_17 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52] wire [3:0] _taken_rviImm_b4_1_T_8 = _taken_rviImm_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _taken_rviImm_b4_1_T_9 = _taken_rviImm_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] taken_rviImm_b4_1 = _taken_rviImm_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _taken_rviImm_b0_T_5 = taken_rviBits[15]; // @[RocketCore.scala:1353:37] wire _taken_rviImm_b0_T_13 = taken_rviBits[15]; // @[RocketCore.scala:1353:37] wire [9:0] taken_rviImm_lo_hi = {taken_rviImm_b10_5, taken_rviImm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] taken_rviImm_lo = {taken_rviImm_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] taken_rviImm_hi_lo = {taken_rviImm_hi_lo_hi, taken_rviImm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] taken_rviImm_hi_hi = {taken_rviImm_hi_hi_hi, taken_rviImm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] taken_rviImm_hi = {taken_rviImm_hi_hi, taken_rviImm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_1 = {taken_rviImm_hi, taken_rviImm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_2 = _taken_rviImm_T_1; // @[RocketCore.scala:1355:{8,53}] wire _taken_rviImm_sign_T_5 = _taken_rviImm_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire taken_rviImm_sign_1 = _taken_rviImm_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire taken_rviImm_hi_hi_hi_1 = taken_rviImm_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _taken_rviImm_b30_20_T_5 = _taken_rviImm_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] taken_rviImm_b30_20_1 = {11{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] taken_rviImm_hi_hi_lo_1 = taken_rviImm_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _taken_rviImm_b19_12_T_9 = _taken_rviImm_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] taken_rviImm_b19_12_1 = {8{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] taken_rviImm_hi_lo_hi_1 = taken_rviImm_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _taken_rviImm_b11_T_16 = _taken_rviImm_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _taken_rviImm_b11_T_19 = _taken_rviImm_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire _taken_rviImm_b11_T_20 = _taken_rviImm_b11_T_19; // @[RocketCore.scala:1346:{18,43}] wire _taken_rviImm_b11_T_21 = _taken_rviImm_b11_T_20; // @[RocketCore.scala:1345:18, :1346:18] wire taken_rviImm_b11_1 = _taken_rviImm_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire taken_rviImm_hi_lo_lo_1 = taken_rviImm_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] taken_rviImm_b10_5_1 = _taken_rviImm_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _taken_rviImm_b4_1_T_19 = _taken_rviImm_b4_1_T_14; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _taken_rviImm_b4_1_T_18 = _taken_rviImm_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] taken_rviImm_b4_1_1 = _taken_rviImm_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] taken_rviImm_lo_hi_1 = {taken_rviImm_b10_5_1, taken_rviImm_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] taken_rviImm_lo_1 = {taken_rviImm_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] taken_rviImm_hi_lo_1 = {taken_rviImm_hi_lo_hi_1, taken_rviImm_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] taken_rviImm_hi_hi_1 = {taken_rviImm_hi_hi_hi_1, taken_rviImm_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] taken_rviImm_hi_1 = {taken_rviImm_hi_hi_1, taken_rviImm_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_3 = {taken_rviImm_hi_1, taken_rviImm_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_4 = _taken_rviImm_T_3; // @[RocketCore.scala:1355:{8,53}] wire [31:0] taken_rviImm = _taken_rviImm_T ? _taken_rviImm_T_2 : _taken_rviImm_T_4; // @[RocketCore.scala:1355:53] wire taken_predict_taken = _taken_predict_taken_T; // @[Frontend.scala:253:54] wire _taken_taken_T_1 = taken_rviBranch & taken_predict_taken; // @[Frontend.scala:239:36, :253:54, :255:53] wire _taken_taken_T_2 = _taken_taken_T | _taken_taken_T_1; // @[Frontend.scala:255:{29,40,53}] wire _taken_taken_T_3 = taken_prevRVI & _taken_taken_T_2; // @[Frontend.scala:234:31, :255:{17,40}] wire _taken_taken_T_4 = taken_rvcJump | taken_rvcJALR; // @[Frontend.scala:246:47, :250:49, :256:27] wire _taken_taken_T_5 = _taken_taken_T_4 | taken_rvcJR; // @[Frontend.scala:248:46, :256:{27,38}] wire _taken_taken_T_6 = taken_rvcBranch & taken_predict_taken; // @[Frontend.scala:244:52, :253:54, :256:60] wire _taken_taken_T_7 = _taken_taken_T_5 | _taken_taken_T_6; // @[Frontend.scala:256:{38,47,60}] wire _taken_taken_T_8 = taken_valid & _taken_taken_T_7; // @[Frontend.scala:235:44, :256:{15,47}] wire taken_taken = _taken_taken_T_3 | _taken_taken_T_8; // @[Frontend.scala:255:{17,71}, :256:15] wire _taken_T_28 = taken_taken; // @[Frontend.scala:255:71, :313:51] wire _taken_predictReturn_T = taken_prevRVI & taken_rviReturn; // @[Frontend.scala:234:31, :242:46, :257:61] wire _taken_predictReturn_T_1 = taken_valid & taken_rvcReturn; // @[Frontend.scala:235:44, :249:29, :257:83] wire _taken_predictReturn_T_2 = _taken_predictReturn_T | _taken_predictReturn_T_1; // @[Frontend.scala:257:{61,74,83}] wire taken_predictReturn = _btb_io_ras_head_valid & _taken_predictReturn_T_2; // @[Frontend.scala:198:21, :257:{49,74}] wire _taken_predictJump_T = taken_prevRVI & taken_rviJump; // @[Frontend.scala:234:31, :240:34, :258:33] wire _taken_predictJump_T_1 = taken_valid & taken_rvcJump; // @[Frontend.scala:235:44, :246:47, :258:53] wire taken_predictJump = _taken_predictJump_T | _taken_predictJump_T_1; // @[Frontend.scala:258:{33,44,53}] wire _GEN_3 = taken_prevRVI & taken_rviBranch; // @[Frontend.scala:234:31, :239:36, :259:53] wire _taken_predictBranch_T; // @[Frontend.scala:259:53] assign _taken_predictBranch_T = _GEN_3; // @[Frontend.scala:259:53] wire _taken_T_19; // @[Frontend.scala:294:23] assign _taken_T_19 = _GEN_3; // @[Frontend.scala:259:53, :294:23] wire _GEN_4 = taken_valid & taken_rvcBranch; // @[Frontend.scala:235:44, :244:52, :259:75] wire _taken_predictBranch_T_1; // @[Frontend.scala:259:75] assign _taken_predictBranch_T_1 = _GEN_4; // @[Frontend.scala:259:75] wire _taken_T_20; // @[Frontend.scala:294:45] assign _taken_T_20 = _GEN_4; // @[Frontend.scala:259:75, :294:45] wire _taken_predictBranch_T_2 = _taken_predictBranch_T | _taken_predictBranch_T_1; // @[Frontend.scala:259:{53,66,75}] wire taken_predictBranch = taken_predict_taken & _taken_predictBranch_T_2; // @[Frontend.scala:253:54, :259:{41,66}] wire _GEN_5 = s2_valid & s2_btb_resp_valid; // @[Frontend.scala:108:25, :118:44, :261:22] wire _taken_T; // @[Frontend.scala:261:22] assign _taken_T = _GEN_5; // @[Frontend.scala:261:22] wire _taken_T_29; // @[Frontend.scala:261:22] assign _taken_T_29 = _GEN_5; // @[Frontend.scala:261:22] wire _taken_T_1 = ~s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69] wire _taken_T_2 = _taken_T & _taken_T_1; // @[Frontend.scala:261:{22,43,69}] wire _taken_T_3 = _taken_T_2 & taken_valid; // @[Frontend.scala:235:44, :261:{43,79}] wire _taken_T_4 = ~taken_rvc; // @[Frontend.scala:233:45, :261:91] wire _taken_T_5 = _taken_T_3 & _taken_T_4; // @[Frontend.scala:261:{79,88,91}] wire _taken_btb_io_ras_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52] wire _taken_btb_io_ras_update_valid_T_2 = _taken_btb_io_ras_update_valid_T & _taken_btb_io_ras_update_valid_T_1; // @[Decoupled.scala:51:35] wire _taken_btb_io_ras_update_valid_T_3 = taken_rviCall | taken_rviReturn; // @[Frontend.scala:242:46, :243:42, :273:90] wire _taken_btb_io_ras_update_valid_T_4 = taken_prevRVI & _taken_btb_io_ras_update_valid_T_3; // @[Frontend.scala:234:31, :273:{78,90}] wire _taken_btb_io_ras_update_valid_T_5 = taken_rvcCall | taken_rvcReturn; // @[Frontend.scala:249:29, :251:28, :273:125] wire _taken_btb_io_ras_update_valid_T_6 = taken_valid & _taken_btb_io_ras_update_valid_T_5; // @[Frontend.scala:235:44, :273:{113,125}] wire _taken_btb_io_ras_update_valid_T_7 = _taken_btb_io_ras_update_valid_T_4 | _taken_btb_io_ras_update_valid_T_6; // @[Frontend.scala:273:{78,104,113}] wire _taken_btb_io_ras_update_valid_T_8 = _taken_btb_io_ras_update_valid_T_2 & _taken_btb_io_ras_update_valid_T_7; // @[Frontend.scala:273:{51,66,104}] wire _taken_btb_io_ras_update_bits_cfiType_T = taken_prevRVI ? taken_rviReturn : taken_rvcReturn; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50] wire _taken_btb_io_ras_update_bits_cfiType_T_1 = taken_prevRVI ? taken_rviCall : taken_rvcCall; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50] wire _taken_btb_io_ras_update_bits_cfiType_T_2 = taken_prevRVI ? taken_rviBranch : taken_rvcBranch; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50] wire _taken_btb_io_ras_update_bits_cfiType_T_4 = _taken_btb_io_ras_update_bits_cfiType_T_2; // @[Frontend.scala:276:{50,82}] wire _taken_btb_io_ras_update_bits_cfiType_T_5 = ~_taken_btb_io_ras_update_bits_cfiType_T_4; // @[Frontend.scala:276:{46,82}] wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_6 = _taken_btb_io_ras_update_bits_cfiType_T_1 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_5}; // @[Frontend.scala:275:{46,50}, :276:46] wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_7 = _taken_btb_io_ras_update_bits_cfiType_T ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_6; // @[Frontend.scala:274:{46,50}, :275:46] wire _taken_T_7 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15] wire _taken_T_9 = _taken_T_8 & taken_taken; // @[Decoupled.scala:51:35] wire _taken_T_10 = ~taken_predictBranch; // @[Frontend.scala:259:41, :280:44] wire _taken_T_11 = _taken_T_9 & _taken_T_10; // @[Frontend.scala:280:{32,41,44}] wire _taken_T_12 = ~taken_predictJump; // @[Frontend.scala:258:44, :280:62] wire _taken_T_13 = _taken_T_11 & _taken_T_12; // @[Frontend.scala:280:{41,59,62}] wire _taken_T_14 = ~taken_predictReturn; // @[Frontend.scala:257:49, :280:78] wire _taken_T_15 = _taken_T_13 & _taken_T_14; // @[Frontend.scala:280:{59,75,78}] wire _taken_T_16 = s2_valid & taken_predictReturn; // @[Frontend.scala:108:25, :257:49, :283:26] wire _taken_T_17 = taken_predictBranch | taken_predictJump; // @[Frontend.scala:258:44, :259:41, :286:44] wire _taken_T_18 = s2_valid & _taken_T_17; // @[Frontend.scala:108:25, :286:{26,44}] wire [39:0] _taken_npc_T = taken_pc; // @[Frontend.scala:287:33, :289:32] wire [32:0] _taken_npc_T_1 = {taken_rviImm[31], taken_rviImm} - 33'h2; // @[Frontend.scala:252:23, :289:61] wire [32:0] _taken_npc_T_2 = taken_prevRVI ? _taken_npc_T_1 : {{12{taken_rvcImm[20]}}, taken_rvcImm}; // @[Frontend.scala:234:31, :247:23, :289:{44,61}] wire [40:0] _taken_npc_T_3 = {_taken_npc_T[39], _taken_npc_T} + {{8{_taken_npc_T_2[32]}}, _taken_npc_T_2}; // @[Frontend.scala:289:{32,39,44}] wire [39:0] _taken_npc_T_4 = _taken_npc_T_3[39:0]; // @[Frontend.scala:289:39] wire [39:0] taken_npc = _taken_npc_T_4; // @[Frontend.scala:289:39] wire [39:0] _taken_predicted_npc_T = taken_npc; // @[Frontend.scala:289:39, :291:34] wire _taken_T_21 = _taken_T_19 | _taken_T_20; // @[Frontend.scala:294:{23,36,45}] wire _taken_btb_io_bht_advance_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52] wire _taken_btb_io_bht_advance_valid_T_2 = _taken_btb_io_bht_advance_valid_T & _taken_btb_io_bht_advance_valid_T_1; // @[Decoupled.scala:51:35] wire _taken_T_22 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15] wire _taken_T_24 = taken_predictBranch & _taken_T_23; // @[Frontend.scala:259:41, :298:52] wire _taken_T_25 = _taken_T_24 | taken_predictJump; // @[Frontend.scala:258:44, :298:{52,91}] wire _taken_T_26 = _taken_T_25 | taken_predictReturn; // @[Frontend.scala:257:49, :298:{91,106}] wire _taken_T_27 = _taken_T_22 & _taken_T_26; // @[Frontend.scala:298:{15,34,106}] wire _taken_prevRVI_T_4 = _taken_prevRVI_T_3 != 2'h3; // @[Frontend.scala:233:{39,45}] wire _taken_prevRVI_T_5 = ~_taken_prevRVI_T_4; // @[Frontend.scala:233:45, :234:34] wire taken_prevRVI_1 = taken_valid & _taken_prevRVI_T_5; // @[Frontend.scala:234:{31,34}, :235:44] wire _taken_valid_T_2 = _fq_io_enq_bits_mask_T_1[1]; // @[Frontend.scala:189:50, :235:38] wire _taken_valid_T_3 = ~taken_prevRVI_1; // @[Frontend.scala:234:31, :235:47] wire taken_valid_1 = _taken_valid_T_2 & _taken_valid_T_3; // @[Frontend.scala:235:{38,44,47}] wire [15:0] taken_bits_1 = _icache_io_resp_bits_data[31:16]; // @[Frontend.scala:70:26, :236:37] wire [1:0] _taken_rvc_T_1 = taken_bits_1[1:0]; // @[Frontend.scala:233:39, :236:37] wire taken_rvc_1 = _taken_rvc_T_1 != 2'h3; // @[Frontend.scala:233:{39,45}] wire [31:0] taken_rviBits_1 = {taken_bits_1, taken_bits}; // @[Frontend.scala:236:37, :238:24] wire [6:0] _taken_rviBranch_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30] wire [6:0] _taken_rviJump_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28] wire [6:0] _taken_rviJALR_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28] wire taken_rviBranch_1 = _taken_rviBranch_T_1 == 7'h63; // @[Frontend.scala:239:{30,36}] wire taken_rviJump_1 = _taken_rviJump_T_1 == 7'h6F; // @[Frontend.scala:240:{28,34}] wire taken_rviJALR_1 = _taken_rviJALR_T_1 == 7'h67; // @[Frontend.scala:241:{28,34}] wire _taken_rviReturn_T_6 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42] wire _taken_rviCall_T_3 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42, :243:52] wire _taken_rviImm_b11_T_29 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39] wire _taken_rviImm_b0_T_17 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37] wire _taken_rviImm_b11_T_40 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39] wire _taken_rviImm_b0_T_25 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37] wire _taken_rviReturn_T_7 = ~_taken_rviReturn_T_6; // @[Frontend.scala:242:{34,42}] wire _taken_rviReturn_T_8 = taken_rviJALR_1 & _taken_rviReturn_T_7; // @[Frontend.scala:241:34, :242:{31,34}] wire [4:0] _taken_rviReturn_T_9 = taken_rviBits_1[19:15]; // @[Frontend.scala:238:24, :242:77] wire [4:0] _taken_rviReturn_T_10 = _taken_rviReturn_T_9 & 5'h1B; // @[Frontend.scala:242:{66,77}] wire _taken_rviReturn_T_11 = _taken_rviReturn_T_10 == 5'h1; // @[Frontend.scala:242:66] wire taken_rviReturn_1 = _taken_rviReturn_T_8 & _taken_rviReturn_T_11; // @[Frontend.scala:242:{31,46,66}] wire _GEN_6 = taken_rviJALR_1 | taken_rviJump_1; // @[Frontend.scala:240:34, :241:34, :243:30] wire _taken_rviCall_T_2; // @[Frontend.scala:243:30] assign _taken_rviCall_T_2 = _GEN_6; // @[Frontend.scala:243:30] wire _taken_taken_T_9; // @[Frontend.scala:255:29] assign _taken_taken_T_9 = _GEN_6; // @[Frontend.scala:243:30, :255:29] wire taken_rviCall_1 = _taken_rviCall_T_2 & _taken_rviCall_T_3; // @[Frontend.scala:243:{30,42,52}] wire [15:0] _GEN_7 = taken_bits_1 & 16'hE003; // @[Frontend.scala:236:37, :244:28] wire [15:0] _taken_rvcBranch_T_4; // @[Frontend.scala:244:28] assign _taken_rvcBranch_T_4 = _GEN_7; // @[Frontend.scala:244:28] wire [15:0] _taken_rvcBranch_T_6; // @[Frontend.scala:244:60] assign _taken_rvcBranch_T_6 = _GEN_7; // @[Frontend.scala:244:{28,60}] wire [15:0] _taken_rvcJAL_T_2; // @[Frontend.scala:245:43] assign _taken_rvcJAL_T_2 = _GEN_7; // @[Frontend.scala:244:28, :245:43] wire [15:0] _taken_rvcJump_T_2; // @[Frontend.scala:246:26] assign _taken_rvcJump_T_2 = _GEN_7; // @[Frontend.scala:244:28, :246:26] wire _taken_rvcBranch_T_5 = _taken_rvcBranch_T_4 == 16'hC001; // @[Frontend.scala:244:28] wire _taken_rvcBranch_T_7 = _taken_rvcBranch_T_6 == 16'hE001; // @[Frontend.scala:244:60] wire taken_rvcBranch_1 = _taken_rvcBranch_T_5 | _taken_rvcBranch_T_7; // @[Frontend.scala:244:{28,52,60}] wire _taken_rvcJAL_T_3 = _taken_rvcJAL_T_2 == 16'h2001; // @[Frontend.scala:245:43] wire _taken_rvcJump_T_3 = _taken_rvcJump_T_2 == 16'hA001; // @[Frontend.scala:246:26] wire taken_rvcJump_1 = _taken_rvcJump_T_3; // @[Frontend.scala:246:{26,47}] wire _taken_rvcImm_T_20 = taken_bits_1[14]; // @[Frontend.scala:236:37, :247:28] wire _taken_rvcImm_T_21 = taken_bits_1[12]; // @[RVC.scala:45:27] wire _taken_rvcImm_T_29 = taken_bits_1[12]; // @[RVC.scala:44:28, :45:27] wire [4:0] _taken_rvcImm_T_22 = {5{_taken_rvcImm_T_21}}; // @[RVC.scala:45:{22,27}] wire [1:0] _taken_rvcImm_T_23 = taken_bits_1[6:5]; // @[RVC.scala:45:35] wire _taken_rvcImm_T_24 = taken_bits_1[2]; // @[RVC.scala:45:43] wire _taken_rvcImm_T_35 = taken_bits_1[2]; // @[RVC.scala:44:63, :45:43] wire [1:0] _taken_rvcImm_T_25 = taken_bits_1[11:10]; // @[RVC.scala:45:49] wire [1:0] _taken_rvcImm_T_26 = taken_bits_1[4:3]; // @[RVC.scala:45:59] wire [3:0] taken_rvcImm_lo_hi_2 = {_taken_rvcImm_T_25, _taken_rvcImm_T_26}; // @[RVC.scala:45:{17,49,59}] wire [4:0] taken_rvcImm_lo_2 = {taken_rvcImm_lo_hi_2, 1'h0}; // @[RVC.scala:45:17] wire [6:0] taken_rvcImm_hi_hi_2 = {_taken_rvcImm_T_22, _taken_rvcImm_T_23}; // @[RVC.scala:45:{17,22,35}] wire [7:0] taken_rvcImm_hi_2 = {taken_rvcImm_hi_hi_2, _taken_rvcImm_T_24}; // @[RVC.scala:45:{17,43}] wire [12:0] _taken_rvcImm_T_27 = {taken_rvcImm_hi_2, taken_rvcImm_lo_2}; // @[RVC.scala:45:17] wire [12:0] _taken_rvcImm_T_28 = _taken_rvcImm_T_27; // @[RVC.scala:45:17] wire [9:0] _taken_rvcImm_T_30 = {10{_taken_rvcImm_T_29}}; // @[RVC.scala:44:{22,28}] wire _taken_rvcImm_T_31 = taken_bits_1[8]; // @[RVC.scala:44:36] wire [1:0] _taken_rvcImm_T_32 = taken_bits_1[10:9]; // @[RVC.scala:44:42] wire _taken_rvcImm_T_33 = taken_bits_1[6]; // @[RVC.scala:44:51] wire _taken_rvcImm_T_34 = taken_bits_1[7]; // @[RVC.scala:44:57] wire _taken_rvcImm_T_36 = taken_bits_1[11]; // @[RVC.scala:44:69] wire [2:0] _taken_rvcImm_T_37 = taken_bits_1[5:3]; // @[RVC.scala:44:76] wire [3:0] taken_rvcImm_lo_lo_1 = {_taken_rvcImm_T_37, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] taken_rvcImm_lo_hi_3 = {_taken_rvcImm_T_35, _taken_rvcImm_T_36}; // @[RVC.scala:44:{17,63,69}] wire [5:0] taken_rvcImm_lo_3 = {taken_rvcImm_lo_hi_3, taken_rvcImm_lo_lo_1}; // @[RVC.scala:44:17] wire [1:0] taken_rvcImm_hi_lo_1 = {_taken_rvcImm_T_33, _taken_rvcImm_T_34}; // @[RVC.scala:44:{17,51,57}] wire [10:0] taken_rvcImm_hi_hi_hi_1 = {_taken_rvcImm_T_30, _taken_rvcImm_T_31}; // @[RVC.scala:44:{17,22,36}] wire [12:0] taken_rvcImm_hi_hi_3 = {taken_rvcImm_hi_hi_hi_1, _taken_rvcImm_T_32}; // @[RVC.scala:44:{17,42}] wire [14:0] taken_rvcImm_hi_3 = {taken_rvcImm_hi_hi_3, taken_rvcImm_hi_lo_1}; // @[RVC.scala:44:17] wire [20:0] _taken_rvcImm_T_38 = {taken_rvcImm_hi_3, taken_rvcImm_lo_3}; // @[RVC.scala:44:17] wire [20:0] _taken_rvcImm_T_39 = _taken_rvcImm_T_38; // @[RVC.scala:44:17] wire [20:0] taken_rvcImm_1 = _taken_rvcImm_T_20 ? {{8{_taken_rvcImm_T_28[12]}}, _taken_rvcImm_T_28} : _taken_rvcImm_T_39; // @[Frontend.scala:247:{23,28,72,118}] wire [15:0] _GEN_8 = taken_bits_1 & 16'hF003; // @[Frontend.scala:236:37, :248:24] wire [15:0] _taken_rvcJR_T_4; // @[Frontend.scala:248:24] assign _taken_rvcJR_T_4 = _GEN_8; // @[Frontend.scala:248:24] wire [15:0] _taken_rvcJALR_T_4; // @[Frontend.scala:250:26] assign _taken_rvcJALR_T_4 = _GEN_8; // @[Frontend.scala:248:24, :250:26] wire _taken_rvcJR_T_5 = _taken_rvcJR_T_4 == 16'h8002; // @[Frontend.scala:248:24] wire [4:0] _taken_rvcJR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53] wire [4:0] _taken_rvcJALR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56] wire _taken_rvcJR_T_7 = _taken_rvcJR_T_6 == 5'h0; // @[Frontend.scala:248:{53,59}] wire taken_rvcJR_1 = _taken_rvcJR_T_5 & _taken_rvcJR_T_7; // @[Frontend.scala:248:{24,46,59}] wire [4:0] _taken_rvcReturn_T_3 = taken_bits_1[11:7]; // @[Frontend.scala:236:37, :249:57] wire [4:0] _taken_rvcReturn_T_4 = _taken_rvcReturn_T_3 & 5'h1B; // @[Frontend.scala:249:{49,57}] wire _taken_rvcReturn_T_5 = _taken_rvcReturn_T_4 == 5'h1; // @[Frontend.scala:249:49] wire taken_rvcReturn_1 = taken_rvcJR_1 & _taken_rvcReturn_T_5; // @[Frontend.scala:248:46, :249:{29,49}] wire _taken_rvcJALR_T_5 = _taken_rvcJALR_T_4 == 16'h9002; // @[Frontend.scala:250:26] wire _taken_rvcJALR_T_7 = _taken_rvcJALR_T_6 == 5'h0; // @[Frontend.scala:250:{56,62}] wire taken_rvcJALR_1 = _taken_rvcJALR_T_5 & _taken_rvcJALR_T_7; // @[Frontend.scala:250:{26,49,62}] wire taken_rvcCall_1 = taken_rvcJALR_1; // @[Frontend.scala:250:49, :251:28] wire _taken_rviImm_T_5 = taken_rviBits_1[3]; // @[Frontend.scala:238:24, :252:31] wire _taken_rviImm_sign_T_7 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44] wire _taken_rviImm_sign_T_10 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44] wire _taken_rviImm_sign_T_8 = _taken_rviImm_sign_T_7; // @[RocketCore.scala:1341:{44,49}] wire taken_rviImm_sign_2 = _taken_rviImm_sign_T_8; // @[RocketCore.scala:1341:{19,49}] wire _taken_rviImm_b11_T_31 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1346:18] wire taken_rviImm_hi_hi_hi_2 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _taken_rviImm_b30_20_T_7 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41] wire [10:0] _taken_rviImm_b30_20_T_10 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41] wire [10:0] _taken_rviImm_b30_20_T_8 = _taken_rviImm_b30_20_T_7; // @[RocketCore.scala:1342:{41,49}] wire [10:0] taken_rviImm_b30_20_2 = {11{taken_rviImm_sign_2}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] taken_rviImm_hi_hi_lo_2 = taken_rviImm_b30_20_2; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _taken_rviImm_b19_12_T_13 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65] wire [7:0] _taken_rviImm_b19_12_T_18 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65] wire [7:0] _taken_rviImm_b19_12_T_14 = _taken_rviImm_b19_12_T_13; // @[RocketCore.scala:1343:{65,73}] wire [7:0] taken_rviImm_b19_12_2 = _taken_rviImm_b19_12_T_14; // @[RocketCore.scala:1343:{21,73}] wire [7:0] taken_rviImm_hi_lo_hi_2 = taken_rviImm_b19_12_2; // @[RocketCore.scala:1343:21, :1355:8] wire _taken_rviImm_b11_T_26 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39] wire _taken_rviImm_b0_T_19 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37] wire _taken_rviImm_b11_T_37 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39] wire _taken_rviImm_b0_T_27 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37] wire _taken_rviImm_b11_T_27 = _taken_rviImm_b11_T_26; // @[RocketCore.scala:1345:{39,44}] wire _taken_rviImm_b11_T_32 = _taken_rviImm_b11_T_27; // @[RocketCore.scala:1345:{18,44}] wire _taken_rviImm_b11_T_30 = _taken_rviImm_b11_T_29; // @[RocketCore.scala:1346:{39,43}] wire taken_rviImm_b11_2 = _taken_rviImm_b11_T_32; // @[RocketCore.scala:1344:18, :1345:18] wire taken_rviImm_hi_lo_lo_2 = taken_rviImm_b11_2; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _taken_rviImm_b10_5_T_11 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62] wire [5:0] _taken_rviImm_b10_5_T_15 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62] wire [5:0] taken_rviImm_b10_5_2 = _taken_rviImm_b10_5_T_11; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _taken_rviImm_b4_1_T_24 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57] wire [3:0] _taken_rviImm_b4_1_T_34 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57] wire [3:0] _taken_rviImm_b4_1_T_26 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39] wire [3:0] _taken_rviImm_b4_1_T_36 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39] wire [3:0] _taken_rviImm_b4_1_T_27 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52] wire [3:0] _taken_rviImm_b4_1_T_37 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52] wire [3:0] _taken_rviImm_b4_1_T_28 = _taken_rviImm_b4_1_T_27; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _taken_rviImm_b4_1_T_29 = _taken_rviImm_b4_1_T_28; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] taken_rviImm_b4_1_2 = _taken_rviImm_b4_1_T_29; // @[RocketCore.scala:1348:19, :1349:19] wire _taken_rviImm_b0_T_21 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37] wire _taken_rviImm_b0_T_29 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37] wire [9:0] taken_rviImm_lo_hi_2 = {taken_rviImm_b10_5_2, taken_rviImm_b4_1_2}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] taken_rviImm_lo_2 = {taken_rviImm_lo_hi_2, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] taken_rviImm_hi_lo_2 = {taken_rviImm_hi_lo_hi_2, taken_rviImm_hi_lo_lo_2}; // @[RocketCore.scala:1355:8] wire [11:0] taken_rviImm_hi_hi_2 = {taken_rviImm_hi_hi_hi_2, taken_rviImm_hi_hi_lo_2}; // @[RocketCore.scala:1355:8] wire [20:0] taken_rviImm_hi_2 = {taken_rviImm_hi_hi_2, taken_rviImm_hi_lo_2}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_6 = {taken_rviImm_hi_2, taken_rviImm_lo_2}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_7 = _taken_rviImm_T_6; // @[RocketCore.scala:1355:{8,53}] wire _taken_rviImm_sign_T_11 = _taken_rviImm_sign_T_10; // @[RocketCore.scala:1341:{44,49}] wire taken_rviImm_sign_3 = _taken_rviImm_sign_T_11; // @[RocketCore.scala:1341:{19,49}] wire taken_rviImm_hi_hi_hi_3 = taken_rviImm_sign_3; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _taken_rviImm_b30_20_T_11 = _taken_rviImm_b30_20_T_10; // @[RocketCore.scala:1342:{41,49}] wire [10:0] taken_rviImm_b30_20_3 = {11{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] taken_rviImm_hi_hi_lo_3 = taken_rviImm_b30_20_3; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _taken_rviImm_b19_12_T_19 = _taken_rviImm_b19_12_T_18; // @[RocketCore.scala:1343:{65,73}] wire [7:0] taken_rviImm_b19_12_3 = {8{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] taken_rviImm_hi_lo_hi_3 = taken_rviImm_b19_12_3; // @[RocketCore.scala:1343:21, :1355:8] wire _taken_rviImm_b11_T_38 = _taken_rviImm_b11_T_37; // @[RocketCore.scala:1345:{39,44}] wire _taken_rviImm_b11_T_41 = _taken_rviImm_b11_T_40; // @[RocketCore.scala:1346:{39,43}] wire _taken_rviImm_b11_T_42 = _taken_rviImm_b11_T_41; // @[RocketCore.scala:1346:{18,43}] wire _taken_rviImm_b11_T_43 = _taken_rviImm_b11_T_42; // @[RocketCore.scala:1345:18, :1346:18] wire taken_rviImm_b11_3 = _taken_rviImm_b11_T_43; // @[RocketCore.scala:1344:18, :1345:18] wire taken_rviImm_hi_lo_lo_3 = taken_rviImm_b11_3; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] taken_rviImm_b10_5_3 = _taken_rviImm_b10_5_T_15; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _taken_rviImm_b4_1_T_39 = _taken_rviImm_b4_1_T_34; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _taken_rviImm_b4_1_T_38 = _taken_rviImm_b4_1_T_37; // @[RocketCore.scala:1350:{19,52}] wire [3:0] taken_rviImm_b4_1_3 = _taken_rviImm_b4_1_T_39; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] taken_rviImm_lo_hi_3 = {taken_rviImm_b10_5_3, taken_rviImm_b4_1_3}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] taken_rviImm_lo_3 = {taken_rviImm_lo_hi_3, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] taken_rviImm_hi_lo_3 = {taken_rviImm_hi_lo_hi_3, taken_rviImm_hi_lo_lo_3}; // @[RocketCore.scala:1355:8] wire [11:0] taken_rviImm_hi_hi_3 = {taken_rviImm_hi_hi_hi_3, taken_rviImm_hi_hi_lo_3}; // @[RocketCore.scala:1355:8] wire [20:0] taken_rviImm_hi_3 = {taken_rviImm_hi_hi_3, taken_rviImm_hi_lo_3}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_8 = {taken_rviImm_hi_3, taken_rviImm_lo_3}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_9 = _taken_rviImm_T_8; // @[RocketCore.scala:1355:{8,53}] wire [31:0] taken_rviImm_1 = _taken_rviImm_T_5 ? _taken_rviImm_T_7 : _taken_rviImm_T_9; // @[RocketCore.scala:1355:53] wire taken_predict_taken_1 = _taken_predict_taken_T_1; // @[Frontend.scala:253:54] wire _taken_taken_T_10 = taken_rviBranch_1 & taken_predict_taken_1; // @[Frontend.scala:239:36, :253:54, :255:53] wire _taken_taken_T_11 = _taken_taken_T_9 | _taken_taken_T_10; // @[Frontend.scala:255:{29,40,53}] wire _taken_taken_T_12 = taken_prevRVI_1 & _taken_taken_T_11; // @[Frontend.scala:234:31, :255:{17,40}] wire _taken_taken_T_13 = taken_rvcJump_1 | taken_rvcJALR_1; // @[Frontend.scala:246:47, :250:49, :256:27] wire _taken_taken_T_14 = _taken_taken_T_13 | taken_rvcJR_1; // @[Frontend.scala:248:46, :256:{27,38}] wire _taken_taken_T_15 = taken_rvcBranch_1 & taken_predict_taken_1; // @[Frontend.scala:244:52, :253:54, :256:60] wire _taken_taken_T_16 = _taken_taken_T_14 | _taken_taken_T_15; // @[Frontend.scala:256:{38,47,60}] wire _taken_taken_T_17 = taken_valid_1 & _taken_taken_T_16; // @[Frontend.scala:235:44, :256:{15,47}] wire taken_taken_1 = _taken_taken_T_12 | _taken_taken_T_17; // @[Frontend.scala:255:{17,71}, :256:15] wire _taken_predictReturn_T_3 = taken_prevRVI_1 & taken_rviReturn_1; // @[Frontend.scala:234:31, :242:46, :257:61] wire _taken_predictReturn_T_4 = taken_valid_1 & taken_rvcReturn_1; // @[Frontend.scala:235:44, :249:29, :257:83] wire _taken_predictReturn_T_5 = _taken_predictReturn_T_3 | _taken_predictReturn_T_4; // @[Frontend.scala:257:{61,74,83}] wire taken_predictReturn_1 = _btb_io_ras_head_valid & _taken_predictReturn_T_5; // @[Frontend.scala:198:21, :257:{49,74}] wire _taken_predictJump_T_2 = taken_prevRVI_1 & taken_rviJump_1; // @[Frontend.scala:234:31, :240:34, :258:33] wire _taken_predictJump_T_3 = taken_valid_1 & taken_rvcJump_1; // @[Frontend.scala:235:44, :246:47, :258:53] wire taken_predictJump_1 = _taken_predictJump_T_2 | _taken_predictJump_T_3; // @[Frontend.scala:258:{33,44,53}] wire _GEN_9 = taken_prevRVI_1 & taken_rviBranch_1; // @[Frontend.scala:234:31, :239:36, :259:53] wire _taken_predictBranch_T_3; // @[Frontend.scala:259:53] assign _taken_predictBranch_T_3 = _GEN_9; // @[Frontend.scala:259:53] wire _taken_T_48; // @[Frontend.scala:294:23] assign _taken_T_48 = _GEN_9; // @[Frontend.scala:259:53, :294:23] wire _GEN_10 = taken_valid_1 & taken_rvcBranch_1; // @[Frontend.scala:235:44, :244:52, :259:75] wire _taken_predictBranch_T_4; // @[Frontend.scala:259:75] assign _taken_predictBranch_T_4 = _GEN_10; // @[Frontend.scala:259:75] wire _taken_T_49; // @[Frontend.scala:294:45] assign _taken_T_49 = _GEN_10; // @[Frontend.scala:259:75, :294:45] wire _taken_predictBranch_T_5 = _taken_predictBranch_T_3 | _taken_predictBranch_T_4; // @[Frontend.scala:259:{53,66,75}] wire taken_predictBranch_1 = taken_predict_taken_1 & _taken_predictBranch_T_5; // @[Frontend.scala:253:54, :259:{41,66}] wire _taken_T_31 = _taken_T_29 & _taken_T_30; // @[Frontend.scala:261:{22,43,69}] wire _taken_T_32 = _taken_T_31 & taken_valid_1; // @[Frontend.scala:235:44, :261:{43,79}] wire _taken_T_33 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91] wire _taken_T_34 = _taken_T_32 & _taken_T_33; // @[Frontend.scala:261:{79,88,91}] assign _taken_T_35 = ~_taken_T_28; // @[Frontend.scala:270:13, :313:51] assign taken_idx = _taken_T_35; // @[Frontend.scala:223:25, :270:13] assign after_idx = _taken_T_35 ? 2'h2 : 2'h1; // @[Frontend.scala:224:25, :270:{13,25}, :272:19] wire _taken_btb_io_ras_update_valid_T_10 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52] wire _taken_btb_io_ras_update_valid_T_11 = _taken_btb_io_ras_update_valid_T_9 & _taken_btb_io_ras_update_valid_T_10; // @[Decoupled.scala:51:35] wire _taken_btb_io_ras_update_valid_T_12 = taken_rviCall_1 | taken_rviReturn_1; // @[Frontend.scala:242:46, :243:42, :273:90] wire _taken_btb_io_ras_update_valid_T_13 = taken_prevRVI_1 & _taken_btb_io_ras_update_valid_T_12; // @[Frontend.scala:234:31, :273:{78,90}] wire _taken_btb_io_ras_update_valid_T_14 = taken_rvcCall_1 | taken_rvcReturn_1; // @[Frontend.scala:249:29, :251:28, :273:125] wire _taken_btb_io_ras_update_valid_T_15 = taken_valid_1 & _taken_btb_io_ras_update_valid_T_14; // @[Frontend.scala:235:44, :273:{113,125}] wire _taken_btb_io_ras_update_valid_T_16 = _taken_btb_io_ras_update_valid_T_13 | _taken_btb_io_ras_update_valid_T_15; // @[Frontend.scala:273:{78,104,113}] wire _taken_btb_io_ras_update_valid_T_17 = _taken_btb_io_ras_update_valid_T_11 & _taken_btb_io_ras_update_valid_T_16; // @[Frontend.scala:273:{51,66,104}] wire _taken_btb_io_ras_update_bits_cfiType_T_8 = taken_prevRVI_1 ? taken_rviReturn_1 : taken_rvcReturn_1; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50] wire _taken_btb_io_ras_update_bits_cfiType_T_9 = taken_prevRVI_1 ? taken_rviCall_1 : taken_rvcCall_1; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50] wire _taken_btb_io_ras_update_bits_cfiType_T_10 = taken_prevRVI_1 ? taken_rviBranch_1 : taken_rvcBranch_1; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50] wire _taken_btb_io_ras_update_bits_cfiType_T_12 = _taken_btb_io_ras_update_bits_cfiType_T_10; // @[Frontend.scala:276:{50,82}] wire _taken_btb_io_ras_update_bits_cfiType_T_13 = ~_taken_btb_io_ras_update_bits_cfiType_T_12; // @[Frontend.scala:276:{46,82}] wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_14 = _taken_btb_io_ras_update_bits_cfiType_T_9 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_13}; // @[Frontend.scala:275:{46,50}, :276:46] wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_15 = _taken_btb_io_ras_update_bits_cfiType_T_8 ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_14; // @[Frontend.scala:274:{46,50}, :275:46] assign btb_io_ras_update_bits_cfiType = _taken_T_35 ? _taken_btb_io_ras_update_bits_cfiType_T_15 : _taken_btb_io_ras_update_bits_cfiType_T_7; // @[Frontend.scala:270:{13,25}, :274:{40,46}] wire _taken_T_36 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15] wire _taken_T_38 = _taken_T_37 & taken_taken_1; // @[Decoupled.scala:51:35] wire _taken_T_39 = ~taken_predictBranch_1; // @[Frontend.scala:259:41, :280:44] wire _taken_T_40 = _taken_T_38 & _taken_T_39; // @[Frontend.scala:280:{32,41,44}] wire _taken_T_41 = ~taken_predictJump_1; // @[Frontend.scala:258:44, :280:62] wire _taken_T_42 = _taken_T_40 & _taken_T_41; // @[Frontend.scala:280:{41,59,62}] wire _taken_T_43 = ~taken_predictReturn_1; // @[Frontend.scala:257:49, :280:78] wire _taken_T_44 = _taken_T_42 & _taken_T_43; // @[Frontend.scala:280:{59,75,78}] wire _taken_T_45 = s2_valid & taken_predictReturn_1; // @[Frontend.scala:108:25, :257:49, :283:26] assign useRAS = _taken_T_35 & _taken_T_36 & _taken_T_45 | _taken_T_7 & _taken_T_16; // @[Frontend.scala:225:29, :270:{13,25}, :279:{15,30}, :283:{26,44}, :284:20] wire _taken_T_46 = taken_predictBranch_1 | taken_predictJump_1; // @[Frontend.scala:258:44, :259:41, :286:44] wire _taken_T_47 = s2_valid & _taken_T_46; // @[Frontend.scala:108:25, :286:{26,44}] wire [39:0] taken_pc_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | 2'h2}; // @[Frontend.scala:222:22, :287:33, :323:50] wire [40:0] _taken_npc_T_5 = {1'h0, taken_pc_1} - 41'h2; // @[Frontend.scala:287:33, :290:36] wire [39:0] _taken_npc_T_6 = _taken_npc_T_5[39:0]; // @[Frontend.scala:290:36] wire [39:0] _taken_npc_T_7 = taken_prevRVI_1 ? _taken_npc_T_6 : taken_pc_1; // @[Frontend.scala:234:31, :287:33, :290:{23,36}] wire [39:0] _taken_npc_T_8 = _taken_npc_T_7; // @[Frontend.scala:290:{23,59}] wire [31:0] _taken_npc_T_9 = taken_prevRVI_1 ? taken_rviImm_1 : {{11{taken_rvcImm_1[20]}}, taken_rvcImm_1}; // @[Frontend.scala:234:31, :247:23, :252:23, :290:71] wire [40:0] _taken_npc_T_10 = {_taken_npc_T_8[39], _taken_npc_T_8} + {{9{_taken_npc_T_9[31]}}, _taken_npc_T_9}; // @[Frontend.scala:290:{59,66,71}] wire [39:0] _taken_npc_T_11 = _taken_npc_T_10[39:0]; // @[Frontend.scala:290:66] wire [39:0] taken_npc_1 = _taken_npc_T_11; // @[Frontend.scala:290:66] wire [39:0] _taken_predicted_npc_T_1 = taken_npc_1; // @[Frontend.scala:290:66, :291:34] wire _taken_T_50 = _taken_T_48 | _taken_T_49; // @[Frontend.scala:294:{23,36,45}] wire _taken_btb_io_bht_advance_valid_T_4 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52] wire _taken_btb_io_bht_advance_valid_T_5 = _taken_btb_io_bht_advance_valid_T_3 & _taken_btb_io_bht_advance_valid_T_4; // @[Decoupled.scala:51:35] wire _taken_T_51 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15] wire _taken_T_53 = taken_predictBranch_1 & _taken_T_52; // @[Frontend.scala:259:41, :298:52] wire _taken_T_54 = _taken_T_53 | taken_predictJump_1; // @[Frontend.scala:258:44, :298:{52,91}] wire _taken_T_55 = _taken_T_54 | taken_predictReturn_1; // @[Frontend.scala:257:49, :298:{91,106}] wire _taken_T_56 = _taken_T_51 & _taken_T_55; // @[Frontend.scala:298:{15,34,106}] assign updateBTB = _taken_T_35 & _taken_T_56 | _taken_T_27; // @[Frontend.scala:226:32, :270:{13,25}, :298:{34,125}, :299:21] wire _taken_T_58 = ~_taken_T_28; // @[Frontend.scala:270:13, :306:26, :313:51] wire _taken_T_59 = taken_valid_1 & _taken_T_58; // @[Frontend.scala:235:44, :306:{23,26}] wire _taken_T_60 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91, :306:40] wire _taken_T_61 = _taken_T_59 & _taken_T_60; // @[Frontend.scala:306:{23,37,40}] wire [15:0] _taken_s2_partial_insn_T = {taken_bits_1[15:2], 2'h3}; // @[Frontend.scala:236:37, :308:37] wire taken = _taken_T_28 | taken_taken_1; // @[Frontend.scala:255:71, :311:19, :313:51] assign predicted_npc = useRAS ? {1'h0, _btb_io_ras_head_bits} : _taken_T_35 & _taken_T_36 & _taken_T_47 ? _taken_predicted_npc_T_1 : _taken_T_7 & _taken_T_18 ? _taken_predicted_npc_T : predicted_taken ? _predicted_npc_T_1 : ntpc; // @[package.scala:132:15] wire _GEN_11 = ~s2_btb_taken & taken; // @[Frontend.scala:120:40, :191:22, :311:19, :336:{11,26}, :337:20, :338:34] assign s2_redirect = ~s2_btb_taken & taken & _T_37 | io_cpu_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }
module TLMasterToNoC_6( // @[Tilelink.scala:37:7] input clock, // @[Tilelink.scala:37:7] input reset, // @[Tilelink.scala:37:7] output io_tilelink_a_ready, // @[Tilelink.scala:44:14] input io_tilelink_a_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_b_ready, // @[Tilelink.scala:44:14] output io_tilelink_b_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:44:14] output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:44:14] output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_c_ready, // @[Tilelink.scala:44:14] input io_tilelink_c_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_d_ready, // @[Tilelink.scala:44:14] output io_tilelink_d_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14] output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_e_ready, // @[Tilelink.scala:44:14] input io_tilelink_e_valid, // @[Tilelink.scala:44:14] input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:44:14] input io_flits_a_ready, // @[Tilelink.scala:44:14] output io_flits_a_valid, // @[Tilelink.scala:44:14] output io_flits_a_bits_head, // @[Tilelink.scala:44:14] output io_flits_a_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14] output [5:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_b_ready, // @[Tilelink.scala:44:14] input io_flits_b_valid, // @[Tilelink.scala:44:14] input io_flits_b_bits_head, // @[Tilelink.scala:44:14] input io_flits_b_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:44:14] input io_flits_c_ready, // @[Tilelink.scala:44:14] output io_flits_c_valid, // @[Tilelink.scala:44:14] output io_flits_c_bits_head, // @[Tilelink.scala:44:14] output io_flits_c_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:44:14] output [5:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_d_ready, // @[Tilelink.scala:44:14] input io_flits_d_valid, // @[Tilelink.scala:44:14] input io_flits_d_bits_head, // @[Tilelink.scala:44:14] input io_flits_d_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:44:14] input io_flits_e_ready, // @[Tilelink.scala:44:14] output io_flits_e_valid, // @[Tilelink.scala:44:14] output io_flits_e_bits_head, // @[Tilelink.scala:44:14] output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:44:14] output [5:0] io_flits_e_bits_egress_id // @[Tilelink.scala:44:14] ); wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:58:17] wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:56:17] TLAToNoC_6 a ( // @[Tilelink.scala:54:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:54:17] TLBFromNoC_5 b ( // @[Tilelink.scala:55:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_opcode (io_tilelink_b_bits_opcode), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_size (io_tilelink_b_bits_size), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_protocol_bits_mask (io_tilelink_b_bits_mask), .io_protocol_bits_data (io_tilelink_b_bits_data), .io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload) ); // @[Tilelink.scala:55:17] TLCToNoC_6 c ( // @[Tilelink.scala:56:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:56:17] TLDFromNoC_5 d ( // @[Tilelink.scala:57:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14] ); // @[Tilelink.scala:57:17] TLEToNoC_4 e ( // @[Tilelink.scala:58:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_e_ready), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:58:17] assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :56:17, :67:14] assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :58:17, :69:14] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }
module IssueSlot_17( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } }
module NoCMonitor_79( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_9( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_35( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [514:0] _c_sizes_set_T_1 = 515'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [131:0] c_opcodes_set = 132'h0; // @[Monitor.scala:740:34] wire [131:0] c_sizes_set = 132'h0; // @[Monitor.scala:741:34] wire [32:0] c_set = 33'h0; // @[Monitor.scala:738:34] wire [32:0] c_set_wo_ready = 33'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_29 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_30 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_31 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_37 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_43 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_49 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_32 = _source_ok_T_31 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire _source_ok_T_55 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire _source_ok_T_56 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_59 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire _T_1003 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1003; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1003; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1076 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1076; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1076; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1076; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [32:0] inflight; // @[Monitor.scala:614:27] reg [131:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [131:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [32:0] a_set; // @[Monitor.scala:626:34] wire [32:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [131:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [131:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [131:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [131:0] _a_opcode_lookup_T_6 = {128'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [131:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[131:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [131:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [131:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [131:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[131:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_2 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[32:0] : 33'h0; // @[OneHot.scala:58:35] wire _T_929 = _T_1003 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_929 ? _a_set_T[32:0] : 33'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_929 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_929 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_929 ? _a_opcodes_set_T_1[131:0] : 132'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_929 ? _a_sizes_set_T_1[131:0] : 132'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [32:0] d_clr; // @[Monitor.scala:664:34] wire [32:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [131:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [131:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_975 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_975 & ~d_release_ack ? _d_clr_wo_ready_T[32:0] : 33'h0; // @[OneHot.scala:58:35] wire _T_944 = _T_1076 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_944 ? _d_clr_T[32:0] : 33'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_944 ? _d_opcodes_clr_T_5[131:0] : 132'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_944 ? _d_sizes_clr_T_5[131:0] : 132'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [32:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [32:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [32:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [131:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [131:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [131:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [131:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [131:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [131:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [32:0] inflight_1; // @[Monitor.scala:726:35] wire [32:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [131:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [131:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [131:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [131:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [131:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [131:0] _c_opcode_lookup_T_6 = {128'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [131:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[131:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [131:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [131:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [131:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[131:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [32:0] d_clr_1; // @[Monitor.scala:774:34] wire [32:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [131:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [131:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1047 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1047 & d_release_ack_1 ? _d_clr_wo_ready_T_1[32:0] : 33'h0; // @[OneHot.scala:58:35] wire _T_1029 = _T_1076 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1029 ? _d_clr_T_1[32:0] : 33'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1029 ? _d_opcodes_clr_T_11[131:0] : 132'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1029 ? _d_sizes_clr_T_11[131:0] : 132'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [32:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [32:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [131:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [131:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [131:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [131:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_278( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_92( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_180 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLFragmenter_ScratchpadBank( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [27:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [27:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [28:0] _find_T_2 = 29'h0; // @[Parameters.scala:137:46] wire [28:0] _find_T_3 = 29'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [27:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [27:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [7:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [27:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[11:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [27:0] _find_T; // @[Parameters.scala:137:31] wire [28:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[27:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [8:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }
module PriorityQueueStage_202( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_12( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_1467 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1467; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1467; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1540 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1540; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1540; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1540; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1393 = _T_1467 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1393 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1393 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1393 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1393 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1393 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1439 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1439 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1408 = _T_1540 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1408 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1408 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1408 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1511 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1511 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1493 = _T_1540 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1493 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1493 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1493 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_25( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [62:0] inflight; // @[Monitor.scala:614:27] reg [251:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [503:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [62:0] inflight_1; // @[Monitor.scala:726:35] reg [503:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_91( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module Router_24( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_1_to_12_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_12_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_12_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_12_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_12_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_12_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_12_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_12_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_12_io_channel_status_3_occupied; // @[Router.scala:122:13] wire [3:0] _ingress_unit_1_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_1_from_12_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_0_from_10_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_10_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_10_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_10_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_10_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_10_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_10_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_10_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_12_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_96( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131073:0] _c_sizes_set_T_1 = 131074'h0; // @[Monitor.scala:768:52] wire [16:0] _c_opcodes_set_T = 17'h0; // @[Monitor.scala:767:79] wire [16:0] _c_sizes_set_T = 17'h0; // @[Monitor.scala:768:77] wire [131074:0] _c_opcodes_set_T_1 = 131075'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [16383:0] _c_set_wo_ready_T = 16384'h1; // @[OneHot.scala:58:35] wire [16383:0] _c_set_T = 16384'h1; // @[OneHot.scala:58:35] wire [32831:0] c_opcodes_set = 32832'h0; // @[Monitor.scala:740:34] wire [32831:0] c_sizes_set = 32832'h0; // @[Monitor.scala:741:34] wire [8207:0] c_set = 8208'h0; // @[Monitor.scala:738:34] wire [8207:0] c_set_wo_ready = 8208'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [13:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [13:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [13:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [8207:0] a_set; // @[Monitor.scala:626:34] wire [8207:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [32831:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [32831:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [16:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [16:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [16:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [16:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [16:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [16:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [16:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [16:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [16:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [32831:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [32831:0] _a_opcode_lookup_T_6 = {32828'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [32831:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [32831:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [32831:0] _a_size_lookup_T_6 = {32828'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [32831:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[32831:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [16383:0] _GEN_2 = 16384'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [16383:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [16:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [16:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [16:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [131074:0] _a_opcodes_set_T_1 = {131071'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [131073:0] _a_sizes_set_T_1 = {131071'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8207:0] d_clr; // @[Monitor.scala:664:34] wire [8207:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [32831:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [32831:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [16383:0] _GEN_5 = 16384'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_5 = 131087'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [131086:0] _d_sizes_clr_T_5 = 131087'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8207:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8207:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8207:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [32831:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [32831:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [32831:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [32831:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [32831:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [32831:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] wire [8207:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [32831:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [32831:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [32831:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [32831:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [32831:0] _c_opcode_lookup_T_6 = {32828'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [32831:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [32831:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [32831:0] _c_size_lookup_T_6 = {32828'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [32831:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[32831:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [8207:0] d_clr_1; // @[Monitor.scala:774:34] wire [8207:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [32831:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [32831:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_11 = 131087'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [131086:0] _d_sizes_clr_T_11 = 131087'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 14'h0; // @[Monitor.scala:36:7, :795:113] wire [8207:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8207:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [32831:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [32831:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [32831:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [32831:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SingleVCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} // Allocates 1 VC per cycle abstract class SingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends VCAllocator(vP)(p) { // get single input val mask = RegInit(0.U(allInParams.size.W)) val in_arb_reqs = Wire(Vec(allInParams.size, MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))) val in_arb_vals = Wire(Vec(allInParams.size, Bool())) val in_arb_filter = PriorityEncoderOH(Cat(in_arb_vals.asUInt, in_arb_vals.asUInt & ~mask)) val in_arb_sel = (in_arb_filter(allInParams.size-1,0) | (in_arb_filter >> allInParams.size)) when (in_arb_vals.orR) { mask := Mux1H(in_arb_sel, (0 until allInParams.size).map { w => ~(0.U((w+1).W)) }) } for (i <- 0 until allInParams.size) { (0 until allOutParams.size).map { m => (0 until allOutParams(m).nVirtualChannels).map { n => in_arb_reqs(i)(m)(n) := io.req(i).bits.vc_sel(m)(n) && !io.channel_status(m)(n).occupied } } in_arb_vals(i) := io.req(i).valid && in_arb_reqs(i).map(_.orR).toSeq.orR } // Input arbitration io.req.foreach(_.ready := false.B) val in_alloc = Wire(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val in_flow = Mux1H(in_arb_sel, io.req.map(_.bits.flow).toSeq) val in_vc = Mux1H(in_arb_sel, io.req.map(_.bits.in_vc).toSeq) val in_vc_sel = Mux1H(in_arb_sel, in_arb_reqs) in_alloc := Mux(in_arb_vals.orR, inputAllocPolicy(in_flow, in_vc_sel, OHToUInt(in_arb_sel), in_vc, io.req.map(_.fire).toSeq.orR), 0.U.asTypeOf(in_alloc)) // send allocation to inputunits for (i <- 0 until allInParams.size) { io.req(i).ready := in_arb_sel(i) for (m <- 0 until allOutParams.size) { (0 until allOutParams(m).nVirtualChannels).map { n => io.resp(i).vc_sel(m)(n) := in_alloc(m)(n) } } assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U) } // send allocation to output units for (i <- 0 until allOutParams.size) { (0 until allOutParams(i).nVirtualChannels).map { j => io.out_allocs(i)(j).alloc := in_alloc(i)(j) io.out_allocs(i)(j).flow := in_flow } } } File VCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.{DecodeLogic} import constellation.channel._ import constellation.noc.{HasNoCParams} import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo, ChannelRoutingInfo} class VCAllocReq( val inParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams with HasNoCParams { val flow = new FlowRoutingBundle val in_vc = UInt(log2Ceil(inParam.nVirtualChannels).W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class VCAllocResp(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } case class VCAllocatorParams( routerParams: RouterParams, inParams: Seq[ChannelParams], outParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], egressParams: Seq[EgressChannelParams]) abstract class VCAllocator(val vP: VCAllocatorParams)(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val routerParams = vP.routerParams val inParams = vP.inParams val outParams = vP.outParams val ingressParams = vP.ingressParams val egressParams = vP.egressParams val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new VCAllocReq(u, outParams, egressParams))) }) val resp = MixedVec(allInParams.map { u => Output(new VCAllocResp(outParams, egressParams)) }) val channel_status = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Input(new OutputChannelStatus)) }) val out_allocs = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputChannelAlloc)) }) }) val nOutChannels = allOutParams.map(_.nVirtualChannels).sum def inputAllocPolicy( flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool): MixedVec[Vec[Bool]] def outputAllocPolicy( out: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool): Vec[Bool] } File ISLIP.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} trait ISLIP { this: VCAllocator => def islip(in: UInt, fire: Bool): UInt = { val w = in.getWidth if (w > 1) { val mask = RegInit(0.U(w.W)) val full = Cat(in, in & ~mask) val oh = PriorityEncoderOH(full) val sel = (oh(w-1,0) | (oh >> w)) when (fire) { mask := MuxCase(0.U, (0 until w).map { i => sel(i) -> ~(0.U((i+1).W)) }) } sel } else { in } } def inputAllocPolicy(flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool) = { islip(vc_sel.asUInt, fire).asTypeOf(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool())})) } def outputAllocPolicy(channel: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool) = { islip(VecInit(reqs).asUInt, fire).asTypeOf(Vec(allInParams.size, Bool())) } } class ISLIPMultiVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends MultiVCAllocator(vP)(p) with ISLIP class RotatingSingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends SingleVCAllocator(vP)(p) with ISLIP
module RotatingSingleVCAllocator_3( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_3_ready, // @[VCAllocator.scala:49:14] input io_req_3_valid, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_2_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [3:0] mask; // @[SingleVCAllocator.scala:16:21] wire [3:0] _in_arb_filter_T_3 = {in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [7:0] in_arb_filter = _in_arb_filter_T_3[0] ? 8'h1 : _in_arb_filter_T_3[1] ? 8'h2 : _in_arb_filter_T_3[2] ? 8'h4 : _in_arb_filter_T_3[3] ? 8'h8 : in_arb_vals_0 ? 8'h10 : in_arb_vals_1 ? 8'h20 : in_arb_vals_2 ? 8'h40 : {in_arb_vals_3, 7'h0}; // @[OneHot.scala:85:71] wire [3:0] in_arb_sel = in_arb_filter[3:0] | in_arb_filter[7:4]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2 | in_arb_vals_3; // @[package.scala:81:59] wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_2 = io_req_0_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_1 = io_req_0_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_2 = io_req_0_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (io_req_0_bits_vc_sel_0_0 | in_arb_reqs_0_0_1 | in_arb_reqs_0_0_2 | in_arb_reqs_0_1_0 | in_arb_reqs_0_1_1 | in_arb_reqs_0_1_2 | in_arb_reqs_0_2_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_1 = io_req_1_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_2 = io_req_1_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (io_req_1_bits_vc_sel_0_0 | in_arb_reqs_1_0_1 | in_arb_reqs_1_0_2 | in_arb_reqs_1_1_0 | in_arb_reqs_1_1_1 | in_arb_reqs_1_1_2 | in_arb_reqs_1_2_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_2 = io_req_2_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_1 = io_req_2_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_2 = io_req_2_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (io_req_2_bits_vc_sel_0_0 | in_arb_reqs_2_0_1 | in_arb_reqs_2_0_2 | in_arb_reqs_2_1_0 | in_arb_reqs_2_1_1 | in_arb_reqs_2_1_2 | in_arb_reqs_2_2_0); // @[package.scala:81:59] wire in_arb_reqs_3_0_1 = io_req_3_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_2 = io_req_3_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_1 = io_req_3_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_2 = io_req_3_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_3 = io_req_3_valid & (io_req_3_bits_vc_sel_0_0 | in_arb_reqs_3_0_1 | in_arb_reqs_3_0_2 | in_arb_reqs_3_1_0 | in_arb_reqs_3_1_1 | in_arb_reqs_3_1_2 | in_arb_reqs_3_2_0); // @[package.scala:81:59] wire _in_vc_sel_T_10 = in_arb_sel[0] & io_req_0_bits_vc_sel_0_0 | in_arb_sel[1] & io_req_1_bits_vc_sel_0_0 | in_arb_sel[2] & io_req_2_bits_vc_sel_0_0 | in_arb_sel[3] & io_req_3_bits_vc_sel_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_17 = in_arb_sel[0] & in_arb_reqs_0_0_1 | in_arb_sel[1] & in_arb_reqs_1_0_1 | in_arb_sel[2] & in_arb_reqs_2_0_1 | in_arb_sel[3] & in_arb_reqs_3_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_24 = in_arb_sel[0] & in_arb_reqs_0_0_2 | in_arb_sel[1] & in_arb_reqs_1_0_2 | in_arb_sel[2] & in_arb_reqs_2_0_2 | in_arb_sel[3] & in_arb_reqs_3_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_31 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0 | in_arb_sel[2] & in_arb_reqs_2_1_0 | in_arb_sel[3] & in_arb_reqs_3_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_38 = in_arb_sel[0] & in_arb_reqs_0_1_1 | in_arb_sel[1] & in_arb_reqs_1_1_1 | in_arb_sel[2] & in_arb_reqs_2_1_1 | in_arb_sel[3] & in_arb_reqs_3_1_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_45 = in_arb_sel[0] & in_arb_reqs_0_1_2 | in_arb_sel[1] & in_arb_reqs_1_1_2 | in_arb_sel[2] & in_arb_reqs_2_1_2 | in_arb_sel[3] & in_arb_reqs_3_1_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_52 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0 | in_arb_sel[3] & in_arb_reqs_3_2_0; // @[Mux.scala:30:73, :32:36] reg [6:0] mask_1; // @[ISLIP.scala:17:25] wire [6:0] _full_T_1 = {_in_vc_sel_T_52, _in_vc_sel_T_45, _in_vc_sel_T_38, _in_vc_sel_T_31, _in_vc_sel_T_24, _in_vc_sel_T_17, _in_vc_sel_T_10} & ~mask_1; // @[Mux.scala:30:73] wire [13:0] oh = _full_T_1[0] ? 14'h1 : _full_T_1[1] ? 14'h2 : _full_T_1[2] ? 14'h4 : _full_T_1[3] ? 14'h8 : _full_T_1[4] ? 14'h10 : _full_T_1[5] ? 14'h20 : _full_T_1[6] ? 14'h40 : _in_vc_sel_T_10 ? 14'h80 : _in_vc_sel_T_17 ? 14'h100 : _in_vc_sel_T_24 ? 14'h200 : _in_vc_sel_T_31 ? 14'h400 : _in_vc_sel_T_38 ? 14'h800 : _in_vc_sel_T_45 ? 14'h1000 : {_in_vc_sel_T_52, 13'h0}; // @[OneHot.scala:85:71] wire [6:0] sel = oh[6:0] | oh[13:7]; // @[Mux.scala:50:70] wire in_alloc_2_0 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_1_1 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_1_2 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_78( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File local.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} abstract class AbstractLocalBranchPredictorBank(implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { val io = IO(new Bundle { val f0_valid = Input(Bool()) val f0_pc = Input(UInt(vaddrBitsExtended.W)) val f1_lhist = Output(UInt(localHistoryLength.W)) val f3_lhist = Output(UInt(localHistoryLength.W)) val f3_taken_br = Input(Bool()) val f3_fire = Input(Bool()) val update = Input(new Bundle { val valid = Input(Bool()) val mispredict = Input(Bool()) val repair = Input(Bool()) val pc = Input(UInt(vaddrBitsExtended.W)) val lhist = Input(UInt(localHistoryLength.W)) }) }) } class NullLocalBranchPredictorBank(implicit p: Parameters) extends AbstractLocalBranchPredictorBank { io.f1_lhist := 0.U io.f3_lhist := 0.U } class LocalBranchPredictorBank(implicit p: Parameters) extends AbstractLocalBranchPredictorBank { override val nSets = localHistoryNSets val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val entries = SyncReadMem(nSets, UInt(localHistoryLength.W)) val s0_idx = fetchIdx(io.f0_pc) val s1_rhist = entries.read(s0_idx, io.f0_valid) val s2_rhist = RegNext(s1_rhist) val s3_rhist = RegNext(s2_rhist) io.f1_lhist := s1_rhist io.f3_lhist := s3_rhist val f3_do_update = Reg(Bool()) val f3_update_idx = Reg(UInt(log2Ceil(nSets).W)) val f3_update_lhist = Reg(UInt(localHistoryLength.W)) f3_do_update := false.B f3_update_idx := DontCare f3_update_lhist := DontCare val s1_update = RegNext(io.update) val s1_update_idx = fetchIdx(s1_update.pc) when (s1_update.valid && (s1_update.mispredict || s1_update.repair)) { f3_do_update := true.B f3_update_idx := s1_update_idx f3_update_lhist := s1_update.lhist } .elsewhen (io.f3_fire) { f3_do_update := true.B f3_update_idx := RegNext(RegNext(RegNext(s0_idx))) f3_update_lhist := s3_rhist << 1 | io.f3_taken_br } when (doing_reset || f3_do_update) { entries.write(Mux(doing_reset, reset_idx, f3_update_idx), Mux(doing_reset, 0.U, f3_update_lhist)) } }
module NullLocalBranchPredictorBank_2( // @[local.scala:38:7] input clock, // @[local.scala:38:7] input reset, // @[local.scala:38:7] input io_f0_valid, // @[local.scala:17:14] input [39:0] io_f0_pc, // @[local.scala:17:14] input io_f3_taken_br, // @[local.scala:17:14] input io_f3_fire, // @[local.scala:17:14] input io_update_valid, // @[local.scala:17:14] input io_update_mispredict, // @[local.scala:17:14] input io_update_repair, // @[local.scala:17:14] input [39:0] io_update_pc, // @[local.scala:17:14] input io_update_lhist // @[local.scala:17:14] ); wire io_f0_valid_0 = io_f0_valid; // @[local.scala:38:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[local.scala:38:7] wire io_f3_taken_br_0 = io_f3_taken_br; // @[local.scala:38:7] wire io_f3_fire_0 = io_f3_fire; // @[local.scala:38:7] wire io_update_valid_0 = io_update_valid; // @[local.scala:38:7] wire io_update_mispredict_0 = io_update_mispredict; // @[local.scala:38:7] wire io_update_repair_0 = io_update_repair; // @[local.scala:38:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[local.scala:38:7] wire io_update_lhist_0 = io_update_lhist; // @[local.scala:38:7] wire io_f1_lhist = 1'h0; // @[local.scala:38:7] wire io_f3_lhist = 1'h0; // @[local.scala:38:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_333( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module mem_32x75( // @[InputUnit.scala:85:18] input [4:0] R0_addr, input R0_en, input R0_clk, output [74:0] R0_data, input [4:0] R1_addr, input R1_en, input R1_clk, output [74:0] R1_data, input [4:0] R2_addr, input R2_en, input R2_clk, output [74:0] R2_data, input [4:0] R3_addr, input R3_en, input R3_clk, output [74:0] R3_data, input [4:0] R4_addr, input R4_en, input R4_clk, output [74:0] R4_data, input [4:0] R5_addr, input R5_en, input R5_clk, output [74:0] R5_data, input [4:0] R6_addr, input R6_en, input R6_clk, output [74:0] R6_data, input [4:0] R7_addr, input R7_en, input R7_clk, output [74:0] R7_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [74:0] W0_data ); reg [74:0] Memory[0:31]; // @[InputUnit.scala:85:18] always @(posedge W0_clk) begin // @[InputUnit.scala:85:18] if (W0_en & 1'h1) // @[InputUnit.scala:85:18] Memory[W0_addr] <= W0_data; // @[InputUnit.scala:85:18] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File decode.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket.Instructions32 import freechips.rocketchip.rocket.CustomInstructions._ import freechips.rocketchip.rocket.RVCExpander import freechips.rocketchip.rocket.{CSR,Causes} import freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf} import FUConstants._ import boom.v3.common._ import boom.v3.util._ // scalastyle:off /** * Abstract trait giving defaults and other relevant values to different Decode constants/ */ abstract trait DecodeConstants extends freechips.rocketchip.rocket.constants.ScalarOpConstants with freechips.rocketchip.rocket.constants.MemoryOpConstants { val xpr64 = Y // TODO inform this from xLen val DC2 = BitPat.dontCare(2) // Makes the listing below more readable def decode_default: List[BitPat] = // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd // | | | | | | | | | | | | | | | | | | | | | | | | List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X) val table: Array[(BitPat, List[BitPat])] } // scalastyle:on /** * Decoded control signals */ class CtrlSigs extends Bundle { val legal = Bool() val fp_val = Bool() val fp_single = Bool() val uopc = UInt(UOPC_SZ.W) val iq_type = UInt(IQT_SZ.W) val fu_code = UInt(FUC_SZ.W) val dst_type = UInt(2.W) val rs1_type = UInt(2.W) val rs2_type = UInt(2.W) val frs3_en = Bool() val imm_sel = UInt(IS_X.getWidth.W) val uses_ldq = Bool() val uses_stq = Bool() val is_amo = Bool() val is_fence = Bool() val is_fencei = Bool() val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W) val wakeup_delay = UInt(2.W) val bypassable = Bool() val is_br = Bool() val is_sys_pc2epc = Bool() val inst_unique = Bool() val flush_on_commit = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val rocc = Bool() def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table) val sigs = Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type, rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo, is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable, is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd) sigs zip decoder map {case(s,d) => s := d} rocc := false.B this } } // scalastyle:off /** * Decode constants for RV32 */ object X32Decode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | Instructions32.SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), Instructions32.SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), Instructions32.SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N) ) } /** * Decode constants for RV64 */ object X64Decode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N) ) } /** * Overall Decode constants */ object XDecode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), // I-type, the immediate12 holds the CSR register. CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W), CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S), CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C), CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W), CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S), CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C), SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N), ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I), EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I), SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N), FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance // currently serializes pipeline // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd // A-type | | | | | | | | | | | | | | | | | | | | | | | | AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N), AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N), AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N), AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N), AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N), AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N), AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N), AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N), AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N), AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N), AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N), AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N), AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N), AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N), AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N), AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N), LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N), LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N), SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N), SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N) ) } /** * FP Decode constants */ object FDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( // frs3_en wakeup_delay // | imm sel | bypassable (aka, known/fixed latency) // | | uses_ldq | | is_br // is val inst? rs1 regtype | | | uses_stq | | | // | is fp inst? | rs2 type| | | | is_amo | | | // | | is dst single-prec? | | | | | | | is_fence | | | // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall // | | | | iq_type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N), FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N), FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // FP to FP FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // Int to FP FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // FP to Int FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // "fp_single" is used for wb_data formatting (and debugging) FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } /** * FP Divide SquareRoot Constants */ object FDivSqrtDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( // frs3_en wakeup_delay // | imm sel | bypassable (aka, known/fixed latency) // | | uses_ldq | | is_br // is val inst? rs1 regtype | | | uses_stq | | | // | is fp inst? | rs2 type| | | | is_amo | | | // | | is dst single-prec? | | | | | | | is_fence | | | // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall // | | | | iq-type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } //scalastyle:on /** * RoCC initial decode */ object RoCCDecode extends DecodeConstants { // Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec rs1 regtype | | | uses_stq | | | // | | | | rs2 type| | | | is_amo | | | // | | | micro-code func unit | | | | | | | is_fence | | | // | | | | iq-type | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd // | | | | | | | | | | | | | | | | | | | | | | | | val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | | CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } /** * IO bundle for the Decode unit */ class DecodeUnitIo(implicit p: Parameters) extends BoomBundle { val enq = new Bundle { val uop = Input(new MicroOp()) } val deq = new Bundle { val uop = Output(new MicroOp()) } // from CSRFile val status = Input(new freechips.rocketchip.rocket.MStatus()) val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO) val interrupt = Input(Bool()) val interrupt_cause = Input(UInt(xLen.W)) } /** * Decode unit that takes in a single instruction and generates a MicroOp. */ class DecodeUnit(implicit p: Parameters) extends BoomModule with freechips.rocketchip.rocket.constants.MemoryOpConstants { val io = IO(new DecodeUnitIo) val uop = Wire(new MicroOp()) uop := io.enq.uop var decode_table = XDecode.table if (usingFPU) decode_table ++= FDecode.table if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table if (usingRoCC) decode_table ++= RoCCDecode.table decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table) val inst = uop.inst val cs = Wire(new CtrlSigs()).decode(inst, decode_table) // Exception Handling io.csr_decode.inst := inst val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W) val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U val system_insn = cs.csr_cmd === CSR.I val sfence = cs.uopc === uopSFENCE val cs_legal = cs.legal // dontTouch(cs_legal) val id_illegal_insn = !cs_legal || cs.fp_val && io.csr_decode.fp_illegal || // TODO check for illegal rm mode: (io.fpu.illegal_rm) cs.rocc && io.csr_decode.rocc_illegal || cs.is_amo && !io.status.isa('a'-'a') || (cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') || csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal) || ((sfence || system_insn) && io.csr_decode.system_illegal) // cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) val (xcpt_valid, xcpt_cause) = checkExceptions(List( (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB (uop.bp_debug_if, (CSR.debugTriggerCause).U), (uop.bp_xcpt_if, (Causes.breakpoint).U), (uop.xcpt_pf_if, (Causes.fetch_page_fault).U), (uop.xcpt_ae_if, (Causes.fetch_access).U), (id_illegal_insn, (Causes.illegal_instruction).U))) uop.exception := xcpt_valid uop.exc_cause := xcpt_cause //------------------------------------------------------------- uop.uopc := cs.uopc uop.iq_type := cs.iq_type uop.fu_code := cs.fu_code // x-registers placed in 0-31, f-registers placed in 32-63. // This allows us to straight-up compare register specifiers and not need to // verify the rtypes (e.g., bypassing in rename). uop.ldst := inst(RD_MSB,RD_LSB) uop.lrs1 := inst(RS1_MSB,RS1_LSB) uop.lrs2 := inst(RS2_MSB,RS2_LSB) uop.lrs3 := inst(RS3_MSB,RS3_LSB) uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX) uop.dst_rtype := cs.dst_type uop.lrs1_rtype := cs.rs1_type uop.lrs2_rtype := cs.rs2_type uop.frs3_en := cs.frs3_en uop.ldst_is_rs1 := uop.is_sfb_shadow // SFB optimization when (uop.is_sfb_shadow && cs.rs2_type === RT_X) { uop.lrs2_rtype := RT_FIX uop.lrs2 := inst(RD_MSB,RD_LSB) uop.ldst_is_rs1 := false.B } .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) { uop.uopc := uopMOV uop.lrs1 := inst(RD_MSB, RD_LSB) uop.ldst_is_rs1 := true.B } when (uop.is_sfb_br) { uop.fu_code := FU_JMP } uop.fp_val := cs.fp_val uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal? uop.mem_cmd := cs.mem_cmd uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12)) uop.mem_signed := !inst(14) uop.uses_ldq := cs.uses_ldq uop.uses_stq := cs.uses_stq uop.is_amo := cs.is_amo uop.is_fence := cs.is_fence uop.is_fencei := cs.is_fencei uop.is_sys_pc2epc := cs.is_sys_pc2epc uop.is_unique := cs.inst_unique uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush) uop.bypassable := cs.bypassable //------------------------------------------------------------- // immediates // repackage the immediate, and then pass the fewest number of bits around val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20)) uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12)) //------------------------------------------------------------- uop.is_br := cs.is_br uop.is_jal := (uop.uopc === uopJAL) uop.is_jalr := (uop.uopc === uopJALR) // uop.is_jump := cs.is_jal || (uop.uopc === uopJALR) // uop.is_ret := (uop.uopc === uopJALR) && // (uop.ldst === X0) && // (uop.lrs1 === RA) // uop.is_call := (uop.uopc === uopJALR || uop.uopc === uopJAL) && // (uop.ldst === RA) //------------------------------------------------------------- io.deq.uop := uop } /** * Smaller Decode unit for the Frontend to decode different * branches. * Accepts EXPANDED RVC instructions */ class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle { val is_ret = Bool() val is_call = Bool() val target = UInt(vaddrBitsExtended.W) val cfi_type = UInt(CFI_SZ.W) // Is this branch a short forwards jump? val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W)) // Is this instruction allowed to be inside a sfb? val shadowable = Bool() } class BranchDecode(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val inst = Input(UInt(32.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val out = Output(new BranchDecodeSignals) }) val bpd_csignals = freechips.rocketchip.rocket.DecodeLogic(io.inst, List[BitPat](N, N, N, N, X), //// is br? //// | is jal? //// | | is jalr? //// | | | //// | | | shadowable //// | | | | has_rs2 //// | | | | | Array[(BitPat, List[BitPat])]( JAL -> List(N, Y, N, N, X), JALR -> List(N, N, Y, N, X), BEQ -> List(Y, N, N, N, X), BNE -> List(Y, N, N, N, X), BGE -> List(Y, N, N, N, X), BGEU -> List(Y, N, N, N, X), BLT -> List(Y, N, N, N, X), BLTU -> List(Y, N, N, N, X), SLLI -> List(N, N, N, Y, N), SRLI -> List(N, N, N, Y, N), SRAI -> List(N, N, N, Y, N), ADDIW -> List(N, N, N, Y, N), SLLIW -> List(N, N, N, Y, N), SRAIW -> List(N, N, N, Y, N), SRLIW -> List(N, N, N, Y, N), ADDW -> List(N, N, N, Y, Y), SUBW -> List(N, N, N, Y, Y), SLLW -> List(N, N, N, Y, Y), SRAW -> List(N, N, N, Y, Y), SRLW -> List(N, N, N, Y, Y), LUI -> List(N, N, N, Y, N), ADDI -> List(N, N, N, Y, N), ANDI -> List(N, N, N, Y, N), ORI -> List(N, N, N, Y, N), XORI -> List(N, N, N, Y, N), SLTI -> List(N, N, N, Y, N), SLTIU -> List(N, N, N, Y, N), SLL -> List(N, N, N, Y, Y), ADD -> List(N, N, N, Y, Y), SUB -> List(N, N, N, Y, Y), SLT -> List(N, N, N, Y, Y), SLTU -> List(N, N, N, Y, Y), AND -> List(N, N, N, Y, Y), OR -> List(N, N, N, Y, Y), XOR -> List(N, N, N, Y, Y), SRA -> List(N, N, N, Y, Y), SRL -> List(N, N, N, Y, Y) )) val cs_is_br = bpd_csignals(0)(0) val cs_is_jal = bpd_csignals(1)(0) val cs_is_jalr = bpd_csignals(2)(0) val cs_is_shadowable = bpd_csignals(3)(0) val cs_has_rs2 = bpd_csignals(4)(0) io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0 io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen), ComputeJALTarget(io.pc, io.inst, xLen)) io.out.cfi_type := Mux(cs_is_jalr, CFI_JALR, Mux(cs_is_jal, CFI_JAL, Mux(cs_is_br, CFI_BR, CFI_X))) val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W)) // Is a sfb if it points forwards (offset is positive) io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U io.out.sfb_offset.bits := br_offset io.out.shadowable := cs_is_shadowable && ( !cs_has_rs2 || (GetRs1(io.inst) === GetRd(io.inst)) || (io.inst === ADD && GetRs1(io.inst) === X0) ) } /** * Track the current "branch mask", and give out the branch mask to each micro-op in Decode * (each micro-op in the machine has a branch mask which says which branches it * is being speculated under). * * @param pl_width pipeline width for the processor */ class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { // guess if the uop is a branch (we'll catch this later) val is_branch = Input(Vec(pl_width, Bool())) // lock in that it's actually a branch and will fire, so we update // the branch_masks. val will_fire = Input(Vec(pl_width, Bool())) // give out tag immediately (needed in rename) // mask can come later in the cycle val br_tag = Output(Vec(pl_width, UInt(brTagSz.W))) val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W))) // tell decoders the branch mask has filled up, but on the granularity // of an individual micro-op (so some micro-ops can go through) val is_full = Output(Vec(pl_width, Bool())) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val debug_branch_mask = Output(UInt(maxBrCount.W)) }) val branch_mask = RegInit(0.U(maxBrCount.W)) //------------------------------------------------------------- // Give out the branch tag to each branch micro-op var allocate_mask = branch_mask val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W))) for (w <- 0 until pl_width) { // TODO this is a loss of performance as we're blocking branches based on potentially fake branches io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w) // find br_tag and compute next br_mask val new_br_tag = Wire(UInt(brTagSz.W)) new_br_tag := 0.U tag_masks(w) := 0.U for (i <- maxBrCount-1 to 0 by -1) { when (~allocate_mask(i)) { new_br_tag := i.U tag_masks(w) := (1.U << i.U) } } io.br_tag(w) := new_br_tag allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask) } //------------------------------------------------------------- // Give out the branch mask to each micro-op // (kill off the bits that corresponded to branches that aren't going to fire) var curr_mask = branch_mask for (w <- 0 until pl_width) { io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask) curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask) } //------------------------------------------------------------- // Update the current branch_mask when (io.flush_pipeline) { branch_mask := 0.U } .otherwise { val mask = Mux(io.brupdate.b2.mispredict, io.brupdate.b2.uop.br_mask, ~(0.U(maxBrCount.W))) branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask } io.debug_branch_mask := branch_mask } File micro-op.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // MicroOp //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.exu.FUConstants /** * Extension to BoomBundle to add a MicroOp */ abstract trait HasBoomUOP extends BoomBundle { val uop = new MicroOp() } /** * MicroOp passing through the pipeline */ class MicroOp(implicit p: Parameters) extends BoomBundle with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val uopc = UInt(UOPC_SZ.W) // micro-op code val inst = UInt(32.W) val debug_inst = UInt(32.W) val is_rvc = Bool() val debug_pc = UInt(coreMaxAddrBits.W) val iq_type = UInt(IQT_SZ.W) // which issue unit do we use? val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use? val ctrl = new CtrlSignals // What is the next state of this uop in the issue window? useful // for the compacting queue. val iw_state = UInt(2.W) // Has operand 1 or 2 been waken speculatively by a load? // Only integer operands are speculaively woken up, // so we can ignore p3. val iw_p1_poisoned = Bool() val iw_p2_poisoned = Bool() val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst? val is_jalr = Bool() // is this a jump? (jal or jalr) val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit val is_sfb = Bool() // is this a sfb or in the shadow of a sfb val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under? val br_tag = UInt(brTagSz.W) // Index into FTQ to figure out our fetch PC. val ftq_idx = UInt(log2Ceil(ftqSz).W) // This inst straddles two fetch packets val edge_inst = Bool() // Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC. // Aligned to a cache-line size, as that is the greater fetch granularity. // TODO: Shouldn't this be aligned to fetch-width size? val pc_lob = UInt(log2Ceil(icBlockBytes).W) // Was this a branch that was predicted taken? val taken = Bool() val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode... // then translate and sign-extend in execute val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe val rob_idx = UInt(robAddrSz.W) val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) val pdst = UInt(maxPregSz.W) val prs1 = UInt(maxPregSz.W) val prs2 = UInt(maxPregSz.W) val prs3 = UInt(maxPregSz.W) val ppred = UInt(log2Ceil(ftqSz).W) val prs1_busy = Bool() val prs2_busy = Bool() val prs3_busy = Bool() val ppred_busy = Bool() val stale_pdst = UInt(maxPregSz.W) val exception = Bool() val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...) val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes val mem_size = UInt(2.W) val mem_signed = Bool() val is_fence = Bool() val is_fencei = Bool() val is_amo = Bool() val uses_ldq = Bool() val uses_stq = Bool() val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC. val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to // drain, clear fetcha fter it (tell ROB to un-ready until empty) val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them // Preditation def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst, // else copy rs2 to dst // logical specifiers (only used in Decode->Rename), except rollback (ldst) val ldst = UInt(lregSz.W) val lrs1 = UInt(lregSz.W) val lrs2 = UInt(lregSz.W) val lrs3 = UInt(lregSz.W) val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc. val dst_rtype = UInt(2.W) val lrs1_rtype = UInt(2.W) val lrs2_rtype = UInt(2.W) val frs3_en = Bool() // floating point information val fp_val = Bool() // is a floating-point instruction (F- or D-extension)? // If it's non-ld/st it will write back exception bits to the fcsr. val fp_single = Bool() // single-precision floating point instruction (F-extension) // frontend exception information val xcpt_pf_if = Bool() // I-TLB page fault. val xcpt_ae_if = Bool() // I$ access exception. val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr). val bp_debug_if = Bool() // Breakpoint val bp_xcpt_if = Bool() // Breakpoint // What prediction structure provides the prediction FROM this op val debug_fsrc = UInt(BSRC_SZ.W) // What prediction structure provides the prediction TO this op val debug_tsrc = UInt(BSRC_SZ.W) // Do we allocate a branch tag for this? // SFB branches don't get a mask, they get a predicate bit def allocate_brtag = (is_br && !is_sfb) || is_jalr // Does this register write-back def rf_wen = dst_rtype =/= RT_X // Is it possible for this uop to misspeculate, preventing the commit of subsequent uops? def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U } /** * Control signals within a MicroOp * * TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution */ class CtrlSignals extends Bundle() { val br_type = UInt(BR_N.getWidth.W) val op1_sel = UInt(OP1_X.getWidth.W) val op2_sel = UInt(OP2_X.getWidth.W) val imm_sel = UInt(IS_X.getWidth.W) val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W) val fcn_dw = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val is_load = Bool() // will invoke TLB address lookup val is_sta = Bool() // will invoke TLB address lookup val is_std = Bool() }
module DecodeUnit_2( // @[decode.scala:474:7] input clock, // @[decode.scala:474:7] input reset, // @[decode.scala:474:7] input [31:0] io_enq_uop_inst, // @[decode.scala:477:14] input [31:0] io_enq_uop_debug_inst, // @[decode.scala:477:14] input io_enq_uop_is_rvc, // @[decode.scala:477:14] input [39:0] io_enq_uop_debug_pc, // @[decode.scala:477:14] input io_enq_uop_is_sfb, // @[decode.scala:477:14] input [4:0] io_enq_uop_ftq_idx, // @[decode.scala:477:14] input io_enq_uop_edge_inst, // @[decode.scala:477:14] input [5:0] io_enq_uop_pc_lob, // @[decode.scala:477:14] input io_enq_uop_taken, // @[decode.scala:477:14] input io_enq_uop_xcpt_pf_if, // @[decode.scala:477:14] input io_enq_uop_xcpt_ae_if, // @[decode.scala:477:14] input io_enq_uop_bp_debug_if, // @[decode.scala:477:14] input io_enq_uop_bp_xcpt_if, // @[decode.scala:477:14] input [1:0] io_enq_uop_debug_fsrc, // @[decode.scala:477:14] output [6:0] io_deq_uop_uopc, // @[decode.scala:477:14] output [31:0] io_deq_uop_inst, // @[decode.scala:477:14] output [31:0] io_deq_uop_debug_inst, // @[decode.scala:477:14] output io_deq_uop_is_rvc, // @[decode.scala:477:14] output [39:0] io_deq_uop_debug_pc, // @[decode.scala:477:14] output [2:0] io_deq_uop_iq_type, // @[decode.scala:477:14] output [9:0] io_deq_uop_fu_code, // @[decode.scala:477:14] output io_deq_uop_is_br, // @[decode.scala:477:14] output io_deq_uop_is_jalr, // @[decode.scala:477:14] output io_deq_uop_is_jal, // @[decode.scala:477:14] output io_deq_uop_is_sfb, // @[decode.scala:477:14] output [4:0] io_deq_uop_ftq_idx, // @[decode.scala:477:14] output io_deq_uop_edge_inst, // @[decode.scala:477:14] output [5:0] io_deq_uop_pc_lob, // @[decode.scala:477:14] output io_deq_uop_taken, // @[decode.scala:477:14] output [19:0] io_deq_uop_imm_packed, // @[decode.scala:477:14] output io_deq_uop_exception, // @[decode.scala:477:14] output [63:0] io_deq_uop_exc_cause, // @[decode.scala:477:14] output io_deq_uop_bypassable, // @[decode.scala:477:14] output [4:0] io_deq_uop_mem_cmd, // @[decode.scala:477:14] output [1:0] io_deq_uop_mem_size, // @[decode.scala:477:14] output io_deq_uop_mem_signed, // @[decode.scala:477:14] output io_deq_uop_is_fence, // @[decode.scala:477:14] output io_deq_uop_is_fencei, // @[decode.scala:477:14] output io_deq_uop_is_amo, // @[decode.scala:477:14] output io_deq_uop_uses_ldq, // @[decode.scala:477:14] output io_deq_uop_uses_stq, // @[decode.scala:477:14] output io_deq_uop_is_sys_pc2epc, // @[decode.scala:477:14] output io_deq_uop_is_unique, // @[decode.scala:477:14] output io_deq_uop_flush_on_commit, // @[decode.scala:477:14] output [5:0] io_deq_uop_ldst, // @[decode.scala:477:14] output [5:0] io_deq_uop_lrs1, // @[decode.scala:477:14] output [5:0] io_deq_uop_lrs2, // @[decode.scala:477:14] output [5:0] io_deq_uop_lrs3, // @[decode.scala:477:14] output io_deq_uop_ldst_val, // @[decode.scala:477:14] output [1:0] io_deq_uop_dst_rtype, // @[decode.scala:477:14] output [1:0] io_deq_uop_lrs1_rtype, // @[decode.scala:477:14] output [1:0] io_deq_uop_lrs2_rtype, // @[decode.scala:477:14] output io_deq_uop_frs3_en, // @[decode.scala:477:14] output io_deq_uop_fp_val, // @[decode.scala:477:14] output io_deq_uop_fp_single, // @[decode.scala:477:14] output io_deq_uop_xcpt_pf_if, // @[decode.scala:477:14] output io_deq_uop_xcpt_ae_if, // @[decode.scala:477:14] output io_deq_uop_bp_debug_if, // @[decode.scala:477:14] output io_deq_uop_bp_xcpt_if, // @[decode.scala:477:14] output [1:0] io_deq_uop_debug_fsrc, // @[decode.scala:477:14] input io_status_debug, // @[decode.scala:477:14] input io_status_cease, // @[decode.scala:477:14] input io_status_wfi, // @[decode.scala:477:14] input [1:0] io_status_dprv, // @[decode.scala:477:14] input io_status_dv, // @[decode.scala:477:14] input [1:0] io_status_prv, // @[decode.scala:477:14] input io_status_v, // @[decode.scala:477:14] input io_status_sd, // @[decode.scala:477:14] input io_status_mpv, // @[decode.scala:477:14] input io_status_gva, // @[decode.scala:477:14] input io_status_tsr, // @[decode.scala:477:14] input io_status_tw, // @[decode.scala:477:14] input io_status_tvm, // @[decode.scala:477:14] input io_status_mxr, // @[decode.scala:477:14] input io_status_sum, // @[decode.scala:477:14] input io_status_mprv, // @[decode.scala:477:14] input [1:0] io_status_fs, // @[decode.scala:477:14] input [1:0] io_status_mpp, // @[decode.scala:477:14] input io_status_spp, // @[decode.scala:477:14] input io_status_mpie, // @[decode.scala:477:14] input io_status_spie, // @[decode.scala:477:14] input io_status_mie, // @[decode.scala:477:14] input io_status_sie, // @[decode.scala:477:14] output [31:0] io_csr_decode_inst, // @[decode.scala:477:14] input io_csr_decode_fp_illegal, // @[decode.scala:477:14] input io_csr_decode_fp_csr, // @[decode.scala:477:14] input io_csr_decode_read_illegal, // @[decode.scala:477:14] input io_csr_decode_write_illegal, // @[decode.scala:477:14] input io_csr_decode_write_flush, // @[decode.scala:477:14] input io_csr_decode_system_illegal, // @[decode.scala:477:14] input io_csr_decode_virtual_access_illegal, // @[decode.scala:477:14] input io_csr_decode_virtual_system_illegal, // @[decode.scala:477:14] input io_interrupt, // @[decode.scala:477:14] input [63:0] io_interrupt_cause // @[decode.scala:477:14] ); wire [31:0] io_enq_uop_inst_0 = io_enq_uop_inst; // @[decode.scala:474:7] wire [31:0] io_enq_uop_debug_inst_0 = io_enq_uop_debug_inst; // @[decode.scala:474:7] wire io_enq_uop_is_rvc_0 = io_enq_uop_is_rvc; // @[decode.scala:474:7] wire [39:0] io_enq_uop_debug_pc_0 = io_enq_uop_debug_pc; // @[decode.scala:474:7] wire io_enq_uop_is_sfb_0 = io_enq_uop_is_sfb; // @[decode.scala:474:7] wire [4:0] io_enq_uop_ftq_idx_0 = io_enq_uop_ftq_idx; // @[decode.scala:474:7] wire io_enq_uop_edge_inst_0 = io_enq_uop_edge_inst; // @[decode.scala:474:7] wire [5:0] io_enq_uop_pc_lob_0 = io_enq_uop_pc_lob; // @[decode.scala:474:7] wire io_enq_uop_taken_0 = io_enq_uop_taken; // @[decode.scala:474:7] wire io_enq_uop_xcpt_pf_if_0 = io_enq_uop_xcpt_pf_if; // @[decode.scala:474:7] wire io_enq_uop_xcpt_ae_if_0 = io_enq_uop_xcpt_ae_if; // @[decode.scala:474:7] wire io_enq_uop_bp_debug_if_0 = io_enq_uop_bp_debug_if; // @[decode.scala:474:7] wire io_enq_uop_bp_xcpt_if_0 = io_enq_uop_bp_xcpt_if; // @[decode.scala:474:7] wire [1:0] io_enq_uop_debug_fsrc_0 = io_enq_uop_debug_fsrc; // @[decode.scala:474:7] wire io_status_debug_0 = io_status_debug; // @[decode.scala:474:7] wire io_status_cease_0 = io_status_cease; // @[decode.scala:474:7] wire io_status_wfi_0 = io_status_wfi; // @[decode.scala:474:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[decode.scala:474:7] wire io_status_dv_0 = io_status_dv; // @[decode.scala:474:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[decode.scala:474:7] wire io_status_v_0 = io_status_v; // @[decode.scala:474:7] wire io_status_sd_0 = io_status_sd; // @[decode.scala:474:7] wire io_status_mpv_0 = io_status_mpv; // @[decode.scala:474:7] wire io_status_gva_0 = io_status_gva; // @[decode.scala:474:7] wire io_status_tsr_0 = io_status_tsr; // @[decode.scala:474:7] wire io_status_tw_0 = io_status_tw; // @[decode.scala:474:7] wire io_status_tvm_0 = io_status_tvm; // @[decode.scala:474:7] wire io_status_mxr_0 = io_status_mxr; // @[decode.scala:474:7] wire io_status_sum_0 = io_status_sum; // @[decode.scala:474:7] wire io_status_mprv_0 = io_status_mprv; // @[decode.scala:474:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[decode.scala:474:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[decode.scala:474:7] wire io_status_spp_0 = io_status_spp; // @[decode.scala:474:7] wire io_status_mpie_0 = io_status_mpie; // @[decode.scala:474:7] wire io_status_spie_0 = io_status_spie; // @[decode.scala:474:7] wire io_status_mie_0 = io_status_mie; // @[decode.scala:474:7] wire io_status_sie_0 = io_status_sie; // @[decode.scala:474:7] wire io_csr_decode_fp_illegal_0 = io_csr_decode_fp_illegal; // @[decode.scala:474:7] wire io_csr_decode_fp_csr_0 = io_csr_decode_fp_csr; // @[decode.scala:474:7] wire io_csr_decode_read_illegal_0 = io_csr_decode_read_illegal; // @[decode.scala:474:7] wire io_csr_decode_write_illegal_0 = io_csr_decode_write_illegal; // @[decode.scala:474:7] wire io_csr_decode_write_flush_0 = io_csr_decode_write_flush; // @[decode.scala:474:7] wire io_csr_decode_system_illegal_0 = io_csr_decode_system_illegal; // @[decode.scala:474:7] wire io_csr_decode_virtual_access_illegal_0 = io_csr_decode_virtual_access_illegal; // @[decode.scala:474:7] wire io_csr_decode_virtual_system_illegal_0 = io_csr_decode_virtual_system_illegal; // @[decode.scala:474:7] wire io_interrupt_0 = io_interrupt; // @[decode.scala:474:7] wire [63:0] io_interrupt_cause_0 = io_interrupt_cause; // @[decode.scala:474:7] wire [1:0] io_status_sxl = 2'h2; // @[decode.scala:474:7] wire [1:0] io_status_uxl = 2'h2; // @[decode.scala:474:7] wire io_csr_decode_vector_illegal = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51] wire io_csr_decode_rocc_illegal = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51] wire _id_illegal_insn_T_5 = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51] wire _id_illegal_insn_T_11 = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51] wire [7:0] io_status_zero1 = 8'h0; // @[decode.scala:474:7, :477:14] wire [22:0] io_status_zero2 = 23'h0; // @[decode.scala:474:7, :477:14] wire [31:0] io_status_isa = 32'h14112D; // @[decode.scala:474:7, :477:14] wire [5:0] io_enq_uop_ldst = 6'h0; // @[decode.scala:474:7, :477:14] wire [5:0] io_enq_uop_lrs1 = 6'h0; // @[decode.scala:474:7, :477:14] wire [5:0] io_enq_uop_lrs2 = 6'h0; // @[decode.scala:474:7, :477:14] wire [5:0] io_enq_uop_lrs3 = 6'h0; // @[decode.scala:474:7, :477:14] wire [63:0] io_enq_uop_exc_cause = 64'h0; // @[decode.scala:474:7, :477:14] wire [11:0] io_enq_uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [11:0] io_deq_uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [11:0] uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [19:0] io_enq_uop_imm_packed = 20'h0; // @[decode.scala:474:7, :477:14] wire [15:0] io_enq_uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [15:0] io_deq_uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [15:0] uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17] wire io_enq_uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ctrl_is_load = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ctrl_is_sta = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ctrl_is_std = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_iw_p1_poisoned = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_iw_p2_poisoned = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_br = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_jalr = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_jal = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_prs1_busy = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_prs2_busy = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_prs3_busy = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ppred_busy = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_exception = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_bypassable = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_mem_signed = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_fence = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_fencei = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_amo = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_uses_ldq = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_uses_stq = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_sys_pc2epc = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_unique = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_flush_on_commit = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ldst_val = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_frs3_en = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_fp_val = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_fp_single = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ctrl_is_load = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ctrl_is_sta = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ctrl_is_std = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_iw_p1_poisoned = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_iw_p2_poisoned = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_prs1_busy = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_prs2_busy = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_prs3_busy = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ppred_busy = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:474:7] wire io_status_mbe = 1'h0; // @[decode.scala:474:7] wire io_status_sbe = 1'h0; // @[decode.scala:474:7] wire io_status_sd_rv32 = 1'h0; // @[decode.scala:474:7] wire io_status_ube = 1'h0; // @[decode.scala:474:7] wire io_status_upie = 1'h0; // @[decode.scala:474:7] wire io_status_hie = 1'h0; // @[decode.scala:474:7] wire io_status_uie = 1'h0; // @[decode.scala:474:7] wire io_csr_decode_vector_csr = 1'h0; // @[decode.scala:474:7] wire uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:479:17] wire uop_ctrl_is_load = 1'h0; // @[decode.scala:479:17] wire uop_ctrl_is_sta = 1'h0; // @[decode.scala:479:17] wire uop_ctrl_is_std = 1'h0; // @[decode.scala:479:17] wire uop_iw_p1_poisoned = 1'h0; // @[decode.scala:479:17] wire uop_iw_p2_poisoned = 1'h0; // @[decode.scala:479:17] wire uop_prs1_busy = 1'h0; // @[decode.scala:479:17] wire uop_prs2_busy = 1'h0; // @[decode.scala:479:17] wire uop_prs3_busy = 1'h0; // @[decode.scala:479:17] wire uop_ppred_busy = 1'h0; // @[decode.scala:479:17] wire uop_ldst_is_rs1 = 1'h0; // @[decode.scala:479:17] wire uop_xcpt_ma_if = 1'h0; // @[decode.scala:479:17] wire cs_rocc = 1'h0; // @[decode.scala:490:16] wire _id_illegal_insn_T_3 = 1'h0; // @[decode.scala:504:13] wire _id_illegal_insn_T_6 = 1'h0; // @[decode.scala:505:18] wire _id_illegal_insn_T_7 = 1'h0; // @[decode.scala:505:15] wire _id_illegal_insn_T_12 = 1'h0; // @[decode.scala:506:37] wire _id_illegal_insn_T_13 = 1'h0; // @[decode.scala:506:34] wire _uop_ldst_is_rs1_T_2 = 1'h0; // @[micro-op.scala:110:43] wire [4:0] io_enq_uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_enq_uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_enq_uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_enq_uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_enq_uop_mem_cmd = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_deq_uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_deq_uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_deq_uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_deq_uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_mem_size = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_dst_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_lrs1_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_lrs2_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_deq_uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_deq_uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_deq_uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_deq_uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_status_xs = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_status_vs = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] io_enq_uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] io_enq_uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] io_deq_uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] io_deq_uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [9:0] io_enq_uop_fu_code = 10'h0; // @[decode.scala:474:7, :477:14] wire [2:0] io_enq_uop_iq_type = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_enq_uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_enq_uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_enq_uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_deq_uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_deq_uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_deq_uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_uopc = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [31:0] uop_inst = io_enq_uop_inst_0; // @[decode.scala:474:7, :479:17] wire [31:0] uop_debug_inst = io_enq_uop_debug_inst_0; // @[decode.scala:474:7, :479:17] wire uop_is_rvc = io_enq_uop_is_rvc_0; // @[decode.scala:474:7, :479:17] wire [39:0] uop_debug_pc = io_enq_uop_debug_pc_0; // @[decode.scala:474:7, :479:17] wire uop_is_sfb = io_enq_uop_is_sfb_0; // @[decode.scala:474:7, :479:17] wire [4:0] uop_ftq_idx = io_enq_uop_ftq_idx_0; // @[decode.scala:474:7, :479:17] wire uop_edge_inst = io_enq_uop_edge_inst_0; // @[decode.scala:474:7, :479:17] wire [5:0] uop_pc_lob = io_enq_uop_pc_lob_0; // @[decode.scala:474:7, :479:17] wire uop_taken = io_enq_uop_taken_0; // @[decode.scala:474:7, :479:17] wire uop_xcpt_pf_if = io_enq_uop_xcpt_pf_if_0; // @[decode.scala:474:7, :479:17] wire uop_xcpt_ae_if = io_enq_uop_xcpt_ae_if_0; // @[decode.scala:474:7, :479:17] wire uop_bp_debug_if = io_enq_uop_bp_debug_if_0; // @[decode.scala:474:7, :479:17] wire uop_bp_xcpt_if = io_enq_uop_bp_xcpt_if_0; // @[decode.scala:474:7, :479:17] wire [1:0] uop_debug_fsrc = io_enq_uop_debug_fsrc_0; // @[decode.scala:474:7, :479:17] wire [6:0] uop_uopc; // @[decode.scala:479:17] wire [2:0] uop_iq_type; // @[decode.scala:479:17] wire [9:0] uop_fu_code; // @[decode.scala:479:17] wire uop_is_br; // @[decode.scala:479:17] wire uop_is_jalr; // @[decode.scala:479:17] wire uop_is_jal; // @[decode.scala:479:17] wire [19:0] uop_imm_packed; // @[decode.scala:479:17] wire uop_exception; // @[decode.scala:479:17] wire [63:0] uop_exc_cause; // @[decode.scala:479:17] wire uop_bypassable; // @[decode.scala:479:17] wire [4:0] uop_mem_cmd; // @[decode.scala:479:17] wire [1:0] uop_mem_size; // @[decode.scala:479:17] wire uop_mem_signed; // @[decode.scala:479:17] wire uop_is_fence; // @[decode.scala:479:17] wire uop_is_fencei; // @[decode.scala:479:17] wire uop_is_amo; // @[decode.scala:479:17] wire uop_uses_ldq; // @[decode.scala:479:17] wire uop_uses_stq; // @[decode.scala:479:17] wire uop_is_sys_pc2epc; // @[decode.scala:479:17] wire uop_is_unique; // @[decode.scala:479:17] wire uop_flush_on_commit; // @[decode.scala:479:17] wire [5:0] uop_ldst; // @[decode.scala:479:17] wire [5:0] uop_lrs1; // @[decode.scala:479:17] wire [5:0] uop_lrs2; // @[decode.scala:479:17] wire [5:0] uop_lrs3; // @[decode.scala:479:17] wire uop_ldst_val; // @[decode.scala:479:17] wire [1:0] uop_dst_rtype; // @[decode.scala:479:17] wire [1:0] uop_lrs1_rtype; // @[decode.scala:479:17] wire [1:0] uop_lrs2_rtype; // @[decode.scala:479:17] wire uop_frs3_en; // @[decode.scala:479:17] wire uop_fp_val; // @[decode.scala:479:17] wire uop_fp_single; // @[decode.scala:479:17] wire [6:0] io_deq_uop_uopc_0; // @[decode.scala:474:7] wire [31:0] io_deq_uop_inst_0; // @[decode.scala:474:7] wire [31:0] io_deq_uop_debug_inst_0; // @[decode.scala:474:7] wire io_deq_uop_is_rvc_0; // @[decode.scala:474:7] wire [39:0] io_deq_uop_debug_pc_0; // @[decode.scala:474:7] wire [2:0] io_deq_uop_iq_type_0; // @[decode.scala:474:7] wire [9:0] io_deq_uop_fu_code_0; // @[decode.scala:474:7] wire io_deq_uop_is_br_0; // @[decode.scala:474:7] wire io_deq_uop_is_jalr_0; // @[decode.scala:474:7] wire io_deq_uop_is_jal_0; // @[decode.scala:474:7] wire io_deq_uop_is_sfb_0; // @[decode.scala:474:7] wire [4:0] io_deq_uop_ftq_idx_0; // @[decode.scala:474:7] wire io_deq_uop_edge_inst_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_pc_lob_0; // @[decode.scala:474:7] wire io_deq_uop_taken_0; // @[decode.scala:474:7] wire [19:0] io_deq_uop_imm_packed_0; // @[decode.scala:474:7] wire io_deq_uop_exception_0; // @[decode.scala:474:7] wire [63:0] io_deq_uop_exc_cause_0; // @[decode.scala:474:7] wire io_deq_uop_bypassable_0; // @[decode.scala:474:7] wire [4:0] io_deq_uop_mem_cmd_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_mem_size_0; // @[decode.scala:474:7] wire io_deq_uop_mem_signed_0; // @[decode.scala:474:7] wire io_deq_uop_is_fence_0; // @[decode.scala:474:7] wire io_deq_uop_is_fencei_0; // @[decode.scala:474:7] wire io_deq_uop_is_amo_0; // @[decode.scala:474:7] wire io_deq_uop_uses_ldq_0; // @[decode.scala:474:7] wire io_deq_uop_uses_stq_0; // @[decode.scala:474:7] wire io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:474:7] wire io_deq_uop_is_unique_0; // @[decode.scala:474:7] wire io_deq_uop_flush_on_commit_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_ldst_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_lrs1_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_lrs2_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_lrs3_0; // @[decode.scala:474:7] wire io_deq_uop_ldst_val_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_dst_rtype_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_lrs1_rtype_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_lrs2_rtype_0; // @[decode.scala:474:7] wire io_deq_uop_frs3_en_0; // @[decode.scala:474:7] wire io_deq_uop_fp_val_0; // @[decode.scala:474:7] wire io_deq_uop_fp_single_0; // @[decode.scala:474:7] wire io_deq_uop_xcpt_pf_if_0; // @[decode.scala:474:7] wire io_deq_uop_xcpt_ae_if_0; // @[decode.scala:474:7] wire io_deq_uop_bp_debug_if_0; // @[decode.scala:474:7] wire io_deq_uop_bp_xcpt_if_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_debug_fsrc_0; // @[decode.scala:474:7] wire [31:0] io_csr_decode_inst_0; // @[decode.scala:474:7] wire [6:0] cs_uopc; // @[decode.scala:490:16] assign io_deq_uop_uopc_0 = uop_uopc; // @[decode.scala:474:7, :479:17] assign io_deq_uop_inst_0 = uop_inst; // @[decode.scala:474:7, :479:17] assign io_csr_decode_inst_0 = uop_inst; // @[decode.scala:474:7, :479:17] wire [31:0] cs_decoder_decoded_plaInput = uop_inst; // @[pla.scala:77:22] assign io_deq_uop_debug_inst_0 = uop_debug_inst; // @[decode.scala:474:7, :479:17] assign io_deq_uop_is_rvc_0 = uop_is_rvc; // @[decode.scala:474:7, :479:17] assign io_deq_uop_debug_pc_0 = uop_debug_pc; // @[decode.scala:474:7, :479:17] wire [2:0] cs_iq_type; // @[decode.scala:490:16] assign io_deq_uop_iq_type_0 = uop_iq_type; // @[decode.scala:474:7, :479:17] wire [9:0] cs_fu_code; // @[decode.scala:490:16] assign io_deq_uop_fu_code_0 = uop_fu_code; // @[decode.scala:474:7, :479:17] wire cs_is_br; // @[decode.scala:490:16] assign io_deq_uop_is_br_0 = uop_is_br; // @[decode.scala:474:7, :479:17] wire _uop_is_jalr_T; // @[decode.scala:590:35] assign io_deq_uop_is_jalr_0 = uop_is_jalr; // @[decode.scala:474:7, :479:17] wire _uop_is_jal_T; // @[decode.scala:589:35] assign io_deq_uop_is_jal_0 = uop_is_jal; // @[decode.scala:474:7, :479:17] assign io_deq_uop_is_sfb_0 = uop_is_sfb; // @[decode.scala:474:7, :479:17] assign io_deq_uop_ftq_idx_0 = uop_ftq_idx; // @[decode.scala:474:7, :479:17] assign io_deq_uop_edge_inst_0 = uop_edge_inst; // @[decode.scala:474:7, :479:17] assign io_deq_uop_pc_lob_0 = uop_pc_lob; // @[decode.scala:474:7, :479:17] assign io_deq_uop_taken_0 = uop_taken; // @[decode.scala:474:7, :479:17] wire [19:0] _uop_imm_packed_T_2; // @[decode.scala:584:24] assign io_deq_uop_imm_packed_0 = uop_imm_packed; // @[decode.scala:474:7, :479:17] wire xcpt_valid; // @[decode.scala:513:26] assign io_deq_uop_exception_0 = uop_exception; // @[decode.scala:474:7, :479:17] wire [63:0] xcpt_cause; // @[Mux.scala:50:70] assign io_deq_uop_exc_cause_0 = uop_exc_cause; // @[decode.scala:474:7, :479:17] wire cs_bypassable; // @[decode.scala:490:16] assign io_deq_uop_bypassable_0 = uop_bypassable; // @[decode.scala:474:7, :479:17] wire [4:0] cs_mem_cmd; // @[decode.scala:490:16] assign io_deq_uop_mem_cmd_0 = uop_mem_cmd; // @[decode.scala:474:7, :479:17] wire [1:0] _uop_mem_size_T_7; // @[decode.scala:566:24] assign io_deq_uop_mem_size_0 = uop_mem_size; // @[decode.scala:474:7, :479:17] wire _uop_mem_signed_T_1; // @[decode.scala:567:21] assign io_deq_uop_mem_signed_0 = uop_mem_signed; // @[decode.scala:474:7, :479:17] wire cs_is_fence; // @[decode.scala:490:16] assign io_deq_uop_is_fence_0 = uop_is_fence; // @[decode.scala:474:7, :479:17] wire cs_is_fencei; // @[decode.scala:490:16] assign io_deq_uop_is_fencei_0 = uop_is_fencei; // @[decode.scala:474:7, :479:17] wire cs_is_amo; // @[decode.scala:490:16] assign io_deq_uop_is_amo_0 = uop_is_amo; // @[decode.scala:474:7, :479:17] wire cs_uses_ldq; // @[decode.scala:490:16] assign io_deq_uop_uses_ldq_0 = uop_uses_ldq; // @[decode.scala:474:7, :479:17] wire cs_uses_stq; // @[decode.scala:490:16] assign io_deq_uop_uses_stq_0 = uop_uses_stq; // @[decode.scala:474:7, :479:17] wire cs_is_sys_pc2epc; // @[decode.scala:490:16] assign io_deq_uop_is_sys_pc2epc_0 = uop_is_sys_pc2epc; // @[decode.scala:474:7, :479:17] wire cs_inst_unique; // @[decode.scala:490:16] assign io_deq_uop_is_unique_0 = uop_is_unique; // @[decode.scala:474:7, :479:17] wire _uop_flush_on_commit_T_3; // @[decode.scala:575:45] assign io_deq_uop_flush_on_commit_0 = uop_flush_on_commit; // @[decode.scala:474:7, :479:17] assign io_deq_uop_ldst_0 = uop_ldst; // @[decode.scala:474:7, :479:17] assign io_deq_uop_lrs1_0 = uop_lrs1; // @[decode.scala:474:7, :479:17] assign io_deq_uop_lrs2_0 = uop_lrs2; // @[decode.scala:474:7, :479:17] assign io_deq_uop_lrs3_0 = uop_lrs3; // @[decode.scala:474:7, :479:17] wire _uop_ldst_val_T_5; // @[decode.scala:540:42] assign io_deq_uop_ldst_val_0 = uop_ldst_val; // @[decode.scala:474:7, :479:17] wire [1:0] cs_dst_type; // @[decode.scala:490:16] assign io_deq_uop_dst_rtype_0 = uop_dst_rtype; // @[decode.scala:474:7, :479:17] wire [1:0] cs_rs1_type; // @[decode.scala:490:16] assign io_deq_uop_lrs1_rtype_0 = uop_lrs1_rtype; // @[decode.scala:474:7, :479:17] wire [1:0] cs_rs2_type; // @[decode.scala:490:16] assign io_deq_uop_lrs2_rtype_0 = uop_lrs2_rtype; // @[decode.scala:474:7, :479:17] wire cs_frs3_en; // @[decode.scala:490:16] assign io_deq_uop_frs3_en_0 = uop_frs3_en; // @[decode.scala:474:7, :479:17] wire cs_fp_val; // @[decode.scala:490:16] assign io_deq_uop_fp_val_0 = uop_fp_val; // @[decode.scala:474:7, :479:17] wire cs_fp_single; // @[decode.scala:490:16] assign io_deq_uop_fp_single_0 = uop_fp_single; // @[decode.scala:474:7, :479:17] assign io_deq_uop_xcpt_pf_if_0 = uop_xcpt_pf_if; // @[decode.scala:474:7, :479:17] assign io_deq_uop_xcpt_ae_if_0 = uop_xcpt_ae_if; // @[decode.scala:474:7, :479:17] assign io_deq_uop_bp_debug_if_0 = uop_bp_debug_if; // @[decode.scala:474:7, :479:17] assign io_deq_uop_bp_xcpt_if_0 = uop_bp_xcpt_if; // @[decode.scala:474:7, :479:17] assign io_deq_uop_debug_fsrc_0 = uop_debug_fsrc; // @[decode.scala:474:7, :479:17] wire cs_decoder_0; // @[Decode.scala:50:77] wire cs_decoder_1; // @[Decode.scala:50:77] assign uop_fp_val = cs_fp_val; // @[decode.scala:479:17, :490:16] wire cs_decoder_2; // @[Decode.scala:50:77] assign uop_fp_single = cs_fp_single; // @[decode.scala:479:17, :490:16] wire [6:0] cs_decoder_3; // @[Decode.scala:50:77] assign uop_uopc = cs_uopc; // @[decode.scala:479:17, :490:16] wire [2:0] cs_decoder_4; // @[Decode.scala:50:77] assign uop_iq_type = cs_iq_type; // @[decode.scala:479:17, :490:16] wire [9:0] cs_decoder_5; // @[Decode.scala:50:77] assign uop_fu_code = cs_fu_code; // @[decode.scala:479:17, :490:16] wire [1:0] cs_decoder_6; // @[Decode.scala:50:77] assign uop_dst_rtype = cs_dst_type; // @[decode.scala:479:17, :490:16] wire [1:0] cs_decoder_7; // @[Decode.scala:50:77] assign uop_lrs1_rtype = cs_rs1_type; // @[decode.scala:479:17, :490:16] wire [1:0] cs_decoder_8; // @[Decode.scala:50:77] assign uop_lrs2_rtype = cs_rs2_type; // @[decode.scala:479:17, :490:16] wire cs_decoder_9; // @[Decode.scala:50:77] assign uop_frs3_en = cs_frs3_en; // @[decode.scala:479:17, :490:16] wire [2:0] cs_decoder_10; // @[Decode.scala:50:77] wire cs_decoder_11; // @[Decode.scala:50:77] assign uop_uses_ldq = cs_uses_ldq; // @[decode.scala:479:17, :490:16] wire cs_decoder_12; // @[Decode.scala:50:77] assign uop_uses_stq = cs_uses_stq; // @[decode.scala:479:17, :490:16] wire cs_decoder_13; // @[Decode.scala:50:77] assign uop_is_amo = cs_is_amo; // @[decode.scala:479:17, :490:16] wire cs_decoder_14; // @[Decode.scala:50:77] assign uop_is_fence = cs_is_fence; // @[decode.scala:479:17, :490:16] wire cs_decoder_15; // @[Decode.scala:50:77] assign uop_is_fencei = cs_is_fencei; // @[decode.scala:479:17, :490:16] wire [4:0] cs_decoder_16; // @[Decode.scala:50:77] assign uop_mem_cmd = cs_mem_cmd; // @[decode.scala:479:17, :490:16] wire [1:0] cs_decoder_17; // @[Decode.scala:50:77] wire cs_decoder_18; // @[Decode.scala:50:77] assign uop_bypassable = cs_bypassable; // @[decode.scala:479:17, :490:16] wire cs_decoder_19; // @[Decode.scala:50:77] assign uop_is_br = cs_is_br; // @[decode.scala:479:17, :490:16] wire cs_decoder_20; // @[Decode.scala:50:77] assign uop_is_sys_pc2epc = cs_is_sys_pc2epc; // @[decode.scala:479:17, :490:16] wire cs_decoder_21; // @[Decode.scala:50:77] assign uop_is_unique = cs_inst_unique; // @[decode.scala:479:17, :490:16] wire cs_decoder_22; // @[Decode.scala:50:77] wire [2:0] cs_decoder_23; // @[Decode.scala:50:77] wire cs_legal; // @[decode.scala:490:16] wire [2:0] cs_imm_sel; // @[decode.scala:490:16] wire [1:0] cs_wakeup_delay; // @[decode.scala:490:16] wire cs_flush_on_commit; // @[decode.scala:490:16] wire [2:0] cs_csr_cmd; // @[decode.scala:490:16] wire [31:0] cs_decoder_decoded_invInputs = ~cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [52:0] cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [52:0] cs_decoder_decoded; // @[pla.scala:81:23] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo = {cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi = {cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T = {cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_77_2 = &_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_1 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_1 = {cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_84_2 = &_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_2 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_2 = {cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_8_2 = &_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_3 = {cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_29_2 = &_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_4 = {cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_124_2 = &_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_5 = {cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_102_2 = &_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_6 = {cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_85_2 = &_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_26 = cs_decoder_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_7 = {cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_56_2 = &_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_8 = {cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_71_2 = &_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_130_2 = &_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_10 = {cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_34_2 = &_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_11 = {cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_163_2 = &_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_12 = {cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_48_2 = &_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_13 = {cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_110_2 = &_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_14 = {cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_170_2 = &_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_15 = {cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_5_2 = &_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_16 = {cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_75_2 = &_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_17 = {cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_12_2 = &_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_18 = {cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_35_2 = &_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_19 = {cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_30_2 = &_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_20 = {cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_24_2 = &_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_21 = {cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_144_2 = &_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_22 = {cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_28_2 = &_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_23 = {cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_126_2 = &_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] _cs_decoder_decoded_andMatrixOutputs_T_24 = {cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_162_2 = &_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_38 = cs_decoder_decoded_andMatrixOutputs_162_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_25 = {cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_1_2 = &_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_26 = {cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_17_2 = &_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_27 = {cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_98_2 = &_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_28 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_28 = {cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_27_2 = &_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_29 = {cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_105_2 = &_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_30 = {cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_122_2 = &_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_31 = {cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_38_2 = &_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_32 = {cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_165_2 = &_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_33 = {cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_19_2 = &_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_34 = {cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_118_2 = &_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_153_2 = &_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_36 = {cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_141_2 = &_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_37 = {cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_168_2 = &_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_38 = {cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_73_2 = &_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_39 = {cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_25_2 = &_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_40 = {cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_79_2 = &_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_41 = {cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_114_2 = &_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_42 = {cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_174_2 = &_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_43 = {cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_139_2 = &_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_37 = cs_decoder_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_44 = {cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_43_2 = &_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_45 = {cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_67_2 = &_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_8 = cs_decoder_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_46 = {cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_18_2 = &_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_25 = cs_decoder_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_47 = {cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_108_2 = &_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_48 = {cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_46_2 = &_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_49 = {cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_10_2 = &_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_50 = {cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_82_2 = &_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_51 = {cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_26_2 = &_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_52 = {cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_42_2 = &_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_53 = {cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_41_2 = &_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_54 = {cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_93_2 = &_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_55 = {cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_70_2 = &_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_56 = {cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_11_2 = &_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_76_2 = &_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_58 = {cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_167_2 = &_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T = cs_decoder_decoded_andMatrixOutputs_167_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_59 = {cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_152_2 = &_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_60 = {cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_96_2 = &_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_61 = {cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_125_2 = &_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_62 = {cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_40_2 = &_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_63 = {cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_169_2 = &_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_64 = {cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_69_2 = &_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_65 = {cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_3_2 = &_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_66 = {cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_16_2 = &_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_67 = {cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_112_2 = &_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_68 = {cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_160_2 = &_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_69 = {cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_101_2 = &_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_70 = {cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_15_2 = &_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_23 = cs_decoder_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_71 = {cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_23_2 = &_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_72 = {cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_173_2 = &_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_73 = {cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_137_2 = &_cs_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_1 = cs_decoder_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_74 = {cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_20_2 = &_cs_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_75 = {cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_54_2 = &_cs_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_76 = {cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_97_2 = &_cs_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_77 = {cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_157_2 = &_cs_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_78 = {cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_145_2 = &_cs_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_79 = {cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_134_2 = &_cs_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_80 = {cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_128_2 = &_cs_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_81 = {cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_142_2 = &_cs_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_117_2 = &_cs_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_83 = {cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_53_2 = &_cs_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_84 = {cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_166_2 = &_cs_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_85 = {cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_21_2 = &_cs_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_86 = {cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_65_2 = &_cs_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_87 = {cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_52_2 = &_cs_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_88 = {cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_57_2 = &_cs_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_74_2 = &_cs_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_90 = {cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_91_2 = &_cs_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_91 = {cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_104_2 = &_cs_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_92 = {cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_68_2 = &_cs_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_93 = {cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_94_2 = &_cs_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_94 = {cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_151_2 = &_cs_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_95 = {cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_2_2 = &_cs_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_96 = {cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_156_2 = &_cs_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_97 = {cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_154_2 = &_cs_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_98 = {cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_148_2 = &_cs_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_99 = {cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_89_2 = &_cs_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_100 = {cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_55_2 = &_cs_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_101 = {cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_116_2 = &_cs_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_102 = {cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_131_2 = &_cs_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_103 = {cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_172_2 = &_cs_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_104 = {cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_72_2 = &_cs_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_105 = {cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_81_2 = &_cs_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_106 = {cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_6_2 = &_cs_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_59 = cs_decoder_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_107 = {cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_143_2 = &_cs_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_108 = {cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_66_2 = &_cs_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_109 = {cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_63_2 = &_cs_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_110 = {cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_161_2 = &_cs_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_111 = {cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_132_2 = &_cs_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_112 = {cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_133_2 = &_cs_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_113 = {cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_147_2 = &_cs_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_114 = {cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_129_2 = &_cs_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_115 = {cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_100_2 = &_cs_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_116 = {cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_119_2 = &_cs_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_117 = {cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_150_2 = &_cs_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_118 = {cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_121_2 = &_cs_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_119 = {cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_158_2 = &_cs_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_120 = {cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_49_2 = &_cs_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_121 = {cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_50_2 = &_cs_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_122 = {cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_45_2 = &_cs_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_123 = {cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_135_2 = &_cs_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_124 = {cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_140_2 = &_cs_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_125 = {cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_95_2 = &_cs_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_126 = {cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_115_2 = &_cs_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_127 = {cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_60_2 = &_cs_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_24 = cs_decoder_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_128 = {cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_7_2 = &_cs_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_129 = {cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_14_2 = &_cs_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_130 = {cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_92_2 = &_cs_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_131 = {cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_78_2 = &_cs_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_132 = {cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_47_2 = &_cs_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_133 = {cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_4_2 = &_cs_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_134 = {cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_123_2 = &_cs_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_135 = {cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_107_2 = &_cs_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_136 = {cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_33_2 = &_cs_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_137 = {cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_88_2 = &_cs_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_138 = {cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_87_2 = &_cs_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_139 = {cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_37_2 = &_cs_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_140 = {cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_22_2 = &_cs_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_141 = {cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_58_2 = &_cs_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_142 = {cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_62_2 = &_cs_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_143 = {cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_9_2 = &_cs_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_144 = {cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_64_2 = &_cs_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_145 = {cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_146_2 = &_cs_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_146 = {cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_113_2 = &_cs_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_147 = {cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_80_2 = &_cs_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_148 = {cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_44_2 = &_cs_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_149 = {cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_159_2 = &_cs_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_150 = {cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_0_2 = &_cs_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_151 = {cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_99_2 = &_cs_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_152 = {cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_13_2 = &_cs_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_153 = {cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_120_2 = &_cs_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_154 = {cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_171_2 = &_cs_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_155 = {cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_109_2 = &_cs_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_156 = {cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_59_2 = &_cs_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_157 = {cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_106_2 = &_cs_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_158 = {cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_155_2 = &_cs_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_159 = {cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_149_2 = &_cs_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_160 = {cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_136_2 = &_cs_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_161 = {cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_31_2 = &_cs_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_162 = {cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_90_2 = &_cs_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_163 = {cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_39_2 = &_cs_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_164 = {cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_83_2 = &_cs_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_165 = {cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_103_2 = &_cs_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_166 = {cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_138_2 = &_cs_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_167 = {cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_86_2 = &_cs_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_168 = {cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_111_2 = &_cs_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_169 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_166 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_169 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_169 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_169, cs_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_169 = {cs_decoder_decoded_andMatrixOutputs_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_32_2 = &_cs_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_169 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_170 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_167 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_170 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_170 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_170, cs_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_170 = {cs_decoder_decoded_andMatrixOutputs_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_127_2 = &_cs_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_170 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_171 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_168 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_171 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_171 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_171, cs_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_171 = {cs_decoder_decoded_andMatrixOutputs_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_164_2 = &_cs_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_171 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_172 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_169 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_172 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_172 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_172, cs_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_172 = {cs_decoder_decoded_andMatrixOutputs_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_61_2 = &_cs_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_172 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_173 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_170 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_173 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_173 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_173, cs_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_173 = {cs_decoder_decoded_andMatrixOutputs_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_36_2 = &_cs_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_173 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_174 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_171 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_174 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_174 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_174, cs_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_174 = {cs_decoder_decoded_andMatrixOutputs_hi_174, cs_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_51_2 = &_cs_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] _GEN = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_13; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo = {cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_0 = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = _GEN_0; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_2 = {cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_3 = |_cs_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_1 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = _GEN_1; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_2 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_2; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_4 = {cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_5 = |_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_6 = {cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_7 = |_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_10 = |_cs_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_3 = {cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = _GEN_3; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = _GEN_4; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_5 = {cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_5; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = _GEN_5; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_11 = {cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_12 = |_cs_decoder_decoded_orMatrixOutputs_T_11; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_6 = {cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = _GEN_6; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_7 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = _GEN_7; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = _GEN_7; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_8 = {cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [14:0] _cs_decoder_decoded_orMatrixOutputs_T_13 = {cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_14 = |_cs_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_5 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = _GEN_9; // @[pla.scala:114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_15 = {cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_16 = |_cs_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_17 = {cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_18 = |_cs_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_19 = {cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_20 = |_cs_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_21 = {cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_22 = |_cs_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_10 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_27 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_7 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_12; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_16; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = _GEN_10; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_28 = |_cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_29 = {cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_30 = |_cs_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_31 = {cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_32 = |_cs_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_33 = {cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_34 = |_cs_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_35 = {cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_36 = |_cs_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_11 = {cs_decoder_decoded_andMatrixOutputs_4_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_6; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = _GEN_12; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_39 = {cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_40 = |_cs_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = _GEN_13; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_14 = {cs_decoder_decoded_andMatrixOutputs_137_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = _GEN_14; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = _GEN_14; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] _GEN_15 = {cs_decoder_decoded_andMatrixOutputs_167_2, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = _GEN_15; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = _GEN_15; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = _GEN_16; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_16; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [24:0] _cs_decoder_decoded_orMatrixOutputs_T_41 = {cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_42 = |_cs_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_17 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = _GEN_17; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_43 = {cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_44 = |_cs_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_45 = {cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_46 = |_cs_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_18 = {cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = _GEN_18; // @[pla.scala:114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_66 = _GEN_18; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_19 = {cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_19; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_47 = {cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_48 = |_cs_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_20 = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_20; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_20; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_16_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = _GEN_21; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = _GEN_21; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = _GEN_22; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_5_2, cs_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_49 = {cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_50 = |_cs_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_144_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [12:0] _cs_decoder_decoded_orMatrixOutputs_T_51 = {cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_52 = |_cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_53 = {cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_54 = |_cs_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_55 = {cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_56 = |_cs_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_148_2, cs_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_58 = |_cs_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_60 = {cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_61 = |_cs_decoder_decoded_orMatrixOutputs_T_60; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_62 = {cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_63 = |_cs_decoder_decoded_orMatrixOutputs_T_62; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_23 = {cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_64 = _GEN_23; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = _GEN_23; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_65 = |_cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:{19,36}] wire _cs_decoder_decoded_orMatrixOutputs_T_67 = |_cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_24 = {cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_19; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_19 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_13; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_101_2, cs_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_68 = {cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_69 = |_cs_decoder_decoded_orMatrixOutputs_T_68; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [17:0] _cs_decoder_decoded_orMatrixOutputs_T_70 = {cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_71 = |_cs_decoder_decoded_orMatrixOutputs_T_70; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [7:0] _cs_decoder_decoded_orMatrixOutputs_T_72 = {cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_73 = |_cs_decoder_decoded_orMatrixOutputs_T_72; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_74 = {cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_75 = |_cs_decoder_decoded_orMatrixOutputs_T_74; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_61_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = _GEN_26; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_150_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_151_2, cs_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [17:0] cs_decoder_decoded_orMatrixOutputs_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] cs_decoder_decoded_orMatrixOutputs_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [36:0] _cs_decoder_decoded_orMatrixOutputs_T_76 = {cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_77 = |_cs_decoder_decoded_orMatrixOutputs_T_76; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_72_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_20_2, cs_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_41_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_10_2, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_27 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = _GEN_27; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [33:0] _cs_decoder_decoded_orMatrixOutputs_T_78 = {cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_79 = |_cs_decoder_decoded_orMatrixOutputs_T_78; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_148_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_42_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {cs_decoder_decoded_andMatrixOutputs_27_2, cs_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_28; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_30_2, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [27:0] _cs_decoder_decoded_orMatrixOutputs_T_80 = {cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_81 = |_cs_decoder_decoded_orMatrixOutputs_T_80; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_129_2, cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_66_2, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] _GEN_29 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_82 = {cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_83 = |_cs_decoder_decoded_orMatrixOutputs_T_82; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_113_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_154_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] cs_decoder_decoded_orMatrixOutputs_hi_32 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _cs_decoder_decoded_orMatrixOutputs_T_84 = {cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_27}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_85 = |_cs_decoder_decoded_orMatrixOutputs_T_84; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_hi_33 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [23:0] _cs_decoder_decoded_orMatrixOutputs_T_86 = {cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_orMatrixOutputs_lo_28}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_87 = |_cs_decoder_decoded_orMatrixOutputs_T_86; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_31_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_29 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_34 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:114:19] wire [17:0] _cs_decoder_decoded_orMatrixOutputs_T_88 = {cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_29}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_89 = |_cs_decoder_decoded_orMatrixOutputs_T_88; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_111_2, cs_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_171_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_30 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_lo_21}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_35 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_90 = {cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_30}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_91 = |_cs_decoder_decoded_orMatrixOutputs_T_90; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_90_2, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_31 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_22}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_36 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_orMatrixOutputs_hi_lo_23}; // @[pla.scala:114:19] wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_92 = {cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_31}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_93 = |_cs_decoder_decoded_orMatrixOutputs_T_92; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [19:0] cs_decoder_decoded_orMatrixOutputs_lo_32 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_23}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_70_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_114_2, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [10:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [20:0] cs_decoder_decoded_orMatrixOutputs_hi_37 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_24}; // @[pla.scala:114:19] wire [40:0] _cs_decoder_decoded_orMatrixOutputs_T_94 = {cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_32}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_95 = |_cs_decoder_decoded_orMatrixOutputs_T_94; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_8, _cs_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_14, _cs_decoder_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_10}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_18, _cs_decoder_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_22, _cs_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [12:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_25, _cs_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_23}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_30, _cs_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_38, _cs_decoder_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {_cs_decoder_decoded_orMatrixOutputs_T_42, _cs_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [12:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:102:36] wire [25:0] cs_decoder_decoded_orMatrixOutputs_lo_33 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_24}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_48, _cs_decoder_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_54, _cs_decoder_decoded_orMatrixOutputs_T_52}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_59, _cs_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_63, _cs_decoder_decoded_orMatrixOutputs_T_61}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_67, _cs_decoder_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_73, _cs_decoder_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_69}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_77, _cs_decoder_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_81, _cs_decoder_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_87, _cs_decoder_decoded_orMatrixOutputs_T_85}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_83}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_91, _cs_decoder_decoded_orMatrixOutputs_T_89}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {_cs_decoder_decoded_orMatrixOutputs_T_95, _cs_decoder_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:102:36] wire [26:0] cs_decoder_decoded_orMatrixOutputs_hi_38 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_25}; // @[pla.scala:102:36] wire [52:0] cs_decoder_decoded_orMatrixOutputs = {cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_33}; // @[pla.scala:102:36] wire _cs_decoder_decoded_invMatrixOutputs_T = cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_1 = cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_2 = cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_3 = cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_4 = cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_5 = cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_6 = cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_7 = cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_8 = cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_9 = cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_10 = cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_11 = cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_12 = cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_13 = cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_14 = cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_15 = cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_16 = cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_17 = cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_18 = cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_19 = cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_20 = cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_21 = cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_22 = cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_23 = cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_24 = cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_25 = cs_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_26 = cs_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_27 = cs_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_28 = cs_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_29 = cs_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_30 = ~_cs_decoder_decoded_invMatrixOutputs_T_29; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_31 = cs_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_32 = cs_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_33 = cs_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_34 = cs_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_35 = cs_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_36 = cs_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_37 = cs_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_38 = cs_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_39 = cs_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_40 = cs_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_41 = cs_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_42 = ~_cs_decoder_decoded_invMatrixOutputs_T_41; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_43 = cs_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_44 = cs_decoder_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_45 = cs_decoder_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_46 = cs_decoder_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_47 = cs_decoder_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_48 = cs_decoder_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_49 = cs_decoder_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_50 = cs_decoder_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_51 = cs_decoder_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_52 = cs_decoder_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_53 = cs_decoder_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_54 = cs_decoder_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_5, _cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_8, _cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_10, _cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_12, _cs_decoder_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [12:0] cs_decoder_decoded_invMatrixOutputs_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_15, _cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [5:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_21, _cs_decoder_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] cs_decoder_decoded_invMatrixOutputs_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [25:0] cs_decoder_decoded_invMatrixOutputs_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_28, _cs_decoder_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :123:40] wire [5:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_35, _cs_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_37, _cs_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_38}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [12:0] cs_decoder_decoded_invMatrixOutputs_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_45, _cs_decoder_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_50, _cs_decoder_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_52, _cs_decoder_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_54, _cs_decoder_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [26:0] cs_decoder_decoded_invMatrixOutputs_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded_invMatrixOutputs = {cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded = cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign cs_decoder_0 = cs_decoder_decoded[52]; // @[pla.scala:81:23] assign cs_legal = cs_decoder_0; // @[Decode.scala:50:77] assign cs_decoder_1 = cs_decoder_decoded[51]; // @[pla.scala:81:23] assign cs_fp_val = cs_decoder_1; // @[Decode.scala:50:77] assign cs_decoder_2 = cs_decoder_decoded[50]; // @[pla.scala:81:23] assign cs_fp_single = cs_decoder_2; // @[Decode.scala:50:77] assign cs_decoder_3 = cs_decoder_decoded[49:43]; // @[pla.scala:81:23] assign cs_uopc = cs_decoder_3; // @[Decode.scala:50:77] assign cs_decoder_4 = cs_decoder_decoded[42:40]; // @[pla.scala:81:23] assign cs_iq_type = cs_decoder_4; // @[Decode.scala:50:77] assign cs_decoder_5 = cs_decoder_decoded[39:30]; // @[pla.scala:81:23] assign cs_fu_code = cs_decoder_5; // @[Decode.scala:50:77] assign cs_decoder_6 = cs_decoder_decoded[29:28]; // @[pla.scala:81:23] assign cs_dst_type = cs_decoder_6; // @[Decode.scala:50:77] assign cs_decoder_7 = cs_decoder_decoded[27:26]; // @[pla.scala:81:23] assign cs_rs1_type = cs_decoder_7; // @[Decode.scala:50:77] assign cs_decoder_8 = cs_decoder_decoded[25:24]; // @[pla.scala:81:23] assign cs_rs2_type = cs_decoder_8; // @[Decode.scala:50:77] assign cs_decoder_9 = cs_decoder_decoded[23]; // @[pla.scala:81:23] assign cs_frs3_en = cs_decoder_9; // @[Decode.scala:50:77] assign cs_decoder_10 = cs_decoder_decoded[22:20]; // @[pla.scala:81:23] assign cs_imm_sel = cs_decoder_10; // @[Decode.scala:50:77] assign cs_decoder_11 = cs_decoder_decoded[19]; // @[pla.scala:81:23] assign cs_uses_ldq = cs_decoder_11; // @[Decode.scala:50:77] assign cs_decoder_12 = cs_decoder_decoded[18]; // @[pla.scala:81:23] assign cs_uses_stq = cs_decoder_12; // @[Decode.scala:50:77] assign cs_decoder_13 = cs_decoder_decoded[17]; // @[pla.scala:81:23] assign cs_is_amo = cs_decoder_13; // @[Decode.scala:50:77] assign cs_decoder_14 = cs_decoder_decoded[16]; // @[pla.scala:81:23] assign cs_is_fence = cs_decoder_14; // @[Decode.scala:50:77] assign cs_decoder_15 = cs_decoder_decoded[15]; // @[pla.scala:81:23] assign cs_is_fencei = cs_decoder_15; // @[Decode.scala:50:77] assign cs_decoder_16 = cs_decoder_decoded[14:10]; // @[pla.scala:81:23] assign cs_mem_cmd = cs_decoder_16; // @[Decode.scala:50:77] assign cs_decoder_17 = cs_decoder_decoded[9:8]; // @[pla.scala:81:23] assign cs_wakeup_delay = cs_decoder_17; // @[Decode.scala:50:77] assign cs_decoder_18 = cs_decoder_decoded[7]; // @[pla.scala:81:23] assign cs_bypassable = cs_decoder_18; // @[Decode.scala:50:77] assign cs_decoder_19 = cs_decoder_decoded[6]; // @[pla.scala:81:23] assign cs_is_br = cs_decoder_19; // @[Decode.scala:50:77] assign cs_decoder_20 = cs_decoder_decoded[5]; // @[pla.scala:81:23] assign cs_is_sys_pc2epc = cs_decoder_20; // @[Decode.scala:50:77] assign cs_decoder_21 = cs_decoder_decoded[4]; // @[pla.scala:81:23] assign cs_inst_unique = cs_decoder_21; // @[Decode.scala:50:77] assign cs_decoder_22 = cs_decoder_decoded[3]; // @[pla.scala:81:23] assign cs_flush_on_commit = cs_decoder_22; // @[Decode.scala:50:77] assign cs_decoder_23 = cs_decoder_decoded[2:0]; // @[pla.scala:81:23] assign cs_csr_cmd = cs_decoder_23; // @[Decode.scala:50:77] wire _GEN_30 = cs_csr_cmd == 3'h6; // @[package.scala:16:47] wire _csr_en_T; // @[package.scala:16:47] assign _csr_en_T = _GEN_30; // @[package.scala:16:47] wire _csr_ren_T; // @[package.scala:16:47] assign _csr_ren_T = _GEN_30; // @[package.scala:16:47] wire _csr_en_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_en_T_2 = cs_csr_cmd == 3'h5; // @[package.scala:16:47] wire _csr_en_T_3 = _csr_en_T | _csr_en_T_1; // @[package.scala:16:47, :81:59] wire csr_en = _csr_en_T_3 | _csr_en_T_2; // @[package.scala:16:47, :81:59] wire _csr_ren_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _csr_ren_T_3 = ~(|uop_lrs1); // @[decode.scala:479:17, :495:62] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[package.scala:81:59] wire system_insn = cs_csr_cmd == 3'h4; // @[decode.scala:490:16, :496:32] wire sfence = cs_uopc == 7'h6B; // @[decode.scala:490:16, :497:24] wire _id_illegal_insn_T = ~cs_legal; // @[decode.scala:490:16, :502:25] wire _id_illegal_insn_T_1 = cs_fp_val & io_csr_decode_fp_illegal_0; // @[decode.scala:474:7, :490:16, :503:15] wire _id_illegal_insn_T_2 = _id_illegal_insn_T | _id_illegal_insn_T_1; // @[decode.scala:502:{25,35}, :503:15] wire _id_illegal_insn_T_4 = _id_illegal_insn_T_2; // @[decode.scala:502:35, :503:43] wire _id_illegal_insn_T_8 = _id_illegal_insn_T_4; // @[decode.scala:503:43, :504:43] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_8; // @[decode.scala:504:43, :505:43] wire _id_illegal_insn_T_9 = ~cs_fp_single; // @[decode.scala:490:16, :506:19] wire _id_illegal_insn_T_10 = cs_fp_val & _id_illegal_insn_T_9; // @[decode.scala:490:16, :506:{16,19}] wire _id_illegal_insn_T_15 = ~csr_ren; // @[decode.scala:495:50, :507:46] wire _id_illegal_insn_T_16 = _id_illegal_insn_T_15 & io_csr_decode_write_illegal_0; // @[decode.scala:474:7, :507:{46,55}] wire _id_illegal_insn_T_17 = io_csr_decode_read_illegal_0 | _id_illegal_insn_T_16; // @[decode.scala:474:7, :507:{43,55}] wire _id_illegal_insn_T_18 = csr_en & _id_illegal_insn_T_17; // @[package.scala:81:59] wire _id_illegal_insn_T_19 = _id_illegal_insn_T_14 | _id_illegal_insn_T_18; // @[decode.scala:505:43, :506:61, :507:12] wire _id_illegal_insn_T_20 = sfence | system_insn; // @[decode.scala:496:32, :497:24, :508:14] wire _id_illegal_insn_T_21 = _id_illegal_insn_T_20 & io_csr_decode_system_illegal_0; // @[decode.scala:474:7, :508:{14,30}] wire id_illegal_insn = _id_illegal_insn_T_19 | _id_illegal_insn_T_21; // @[decode.scala:506:61, :507:87, :508:30] wire _T_1 = io_interrupt_0 & ~io_enq_uop_is_sfb_0; // @[decode.scala:474:7, :516:{19,22}] assign xcpt_valid = _T_1 | uop_bp_debug_if | uop_bp_xcpt_if | uop_xcpt_pf_if | uop_xcpt_ae_if | id_illegal_insn; // @[decode.scala:479:17, :507:87, :513:26, :516:19] assign uop_exception = xcpt_valid; // @[decode.scala:479:17, :513:26] assign xcpt_cause = _T_1 ? io_interrupt_cause_0 : {60'h0, uop_bp_debug_if ? 4'hE : uop_bp_xcpt_if ? 4'h3 : uop_xcpt_pf_if ? 4'hC : {2'h0, uop_xcpt_ae_if ? 2'h1 : 2'h2}}; // @[Mux.scala:50:70] assign uop_exc_cause = xcpt_cause; // @[Mux.scala:50:70] wire [4:0] _uop_ldst_T = uop_inst[11:7]; // @[decode.scala:479:17, :535:25] wire [4:0] _uop_lrs2_T_1 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :550:28] wire [4:0] _uop_lrs1_T_1 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :554:28] wire [4:0] _di24_20_T_3 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :583:69] assign uop_ldst = {1'h0, _uop_ldst_T}; // @[decode.scala:479:17, :535:{18,25}] wire [4:0] _uop_lrs1_T = uop_inst[19:15]; // @[decode.scala:479:17, :536:25] assign uop_lrs1 = {1'h0, _uop_lrs1_T}; // @[decode.scala:479:17, :536:{18,25}] wire [4:0] _uop_lrs2_T = uop_inst[24:20]; // @[decode.scala:479:17, :537:25] wire [4:0] _di24_20_T_4 = uop_inst[24:20]; // @[decode.scala:479:17, :537:25, :583:81] assign uop_lrs2 = {1'h0, _uop_lrs2_T}; // @[decode.scala:479:17, :537:{18,25}] wire [4:0] _uop_lrs3_T = uop_inst[31:27]; // @[decode.scala:479:17, :538:25] assign uop_lrs3 = {1'h0, _uop_lrs3_T}; // @[decode.scala:479:17, :538:{18,25}] wire _uop_ldst_val_T = cs_dst_type != 2'h2; // @[decode.scala:490:16, :540:33] wire _uop_ldst_val_T_1 = uop_ldst == 6'h0; // @[decode.scala:474:7, :477:14, :479:17, :540:56] wire _uop_ldst_val_T_2 = uop_dst_rtype == 2'h0; // @[decode.scala:474:7, :477:14, :479:17, :540:81] wire _uop_ldst_val_T_3 = _uop_ldst_val_T_1 & _uop_ldst_val_T_2; // @[decode.scala:540:{56,64,81}] wire _uop_ldst_val_T_4 = ~_uop_ldst_val_T_3; // @[decode.scala:540:{45,64}] assign _uop_ldst_val_T_5 = _uop_ldst_val_T & _uop_ldst_val_T_4; // @[decode.scala:540:{33,42,45}] assign uop_ldst_val = _uop_ldst_val_T_5; // @[decode.scala:479:17, :540:42] wire _uop_ldst_is_rs1_T = ~uop_is_br; // @[decode.scala:479:17] wire _uop_ldst_is_rs1_T_1 = _uop_ldst_is_rs1_T & uop_is_sfb; // @[decode.scala:479:17] wire _uop_mem_size_T = cs_mem_cmd == 5'h14; // @[package.scala:16:47] wire _uop_mem_size_T_1 = cs_mem_cmd == 5'h5; // @[package.scala:16:47] wire _uop_mem_size_T_2 = _uop_mem_size_T | _uop_mem_size_T_1; // @[package.scala:16:47, :81:59] wire _uop_mem_size_T_3 = |uop_lrs2; // @[decode.scala:479:17, :566:81] wire _uop_mem_size_T_4 = |uop_lrs1; // @[decode.scala:479:17, :495:62, :566:99] wire [1:0] _uop_mem_size_T_5 = {_uop_mem_size_T_3, _uop_mem_size_T_4}; // @[decode.scala:566:{71,81,99}] wire [1:0] _uop_mem_size_T_6 = uop_inst[13:12]; // @[decode.scala:479:17, :566:113] assign _uop_mem_size_T_7 = _uop_mem_size_T_2 ? _uop_mem_size_T_5 : _uop_mem_size_T_6; // @[package.scala:81:59] assign uop_mem_size = _uop_mem_size_T_7; // @[decode.scala:479:17, :566:24] wire _uop_mem_signed_T = uop_inst[14]; // @[decode.scala:479:17, :567:26] assign _uop_mem_signed_T_1 = ~_uop_mem_signed_T; // @[decode.scala:567:{21,26}] assign uop_mem_signed = _uop_mem_signed_T_1; // @[decode.scala:479:17, :567:21] wire _uop_flush_on_commit_T = ~csr_ren; // @[decode.scala:495:50, :507:46, :575:59] wire _uop_flush_on_commit_T_1 = csr_en & _uop_flush_on_commit_T; // @[package.scala:81:59] wire _uop_flush_on_commit_T_2 = _uop_flush_on_commit_T_1 & io_csr_decode_write_flush_0; // @[decode.scala:474:7, :575:{56,68}] assign _uop_flush_on_commit_T_3 = cs_flush_on_commit | _uop_flush_on_commit_T_2; // @[decode.scala:490:16, :575:{45,68}] assign uop_flush_on_commit = _uop_flush_on_commit_T_3; // @[decode.scala:479:17, :575:45] wire _di24_20_T = cs_imm_sel == 3'h2; // @[decode.scala:490:16, :583:32] wire _di24_20_T_1 = cs_imm_sel == 3'h1; // @[decode.scala:490:16, :583:55] wire _di24_20_T_2 = _di24_20_T | _di24_20_T_1; // @[decode.scala:583:{32,41,55}] wire [4:0] di24_20 = _di24_20_T_2 ? _di24_20_T_3 : _di24_20_T_4; // @[decode.scala:583:{20,41,69,81}] wire [6:0] _uop_imm_packed_T = uop_inst[31:25]; // @[decode.scala:479:17, :584:29] wire [7:0] _uop_imm_packed_T_1 = uop_inst[19:12]; // @[decode.scala:479:17, :584:51] wire [11:0] uop_imm_packed_hi = {_uop_imm_packed_T, di24_20}; // @[decode.scala:583:20, :584:{24,29}] assign _uop_imm_packed_T_2 = {uop_imm_packed_hi, _uop_imm_packed_T_1}; // @[decode.scala:584:{24,51}] assign uop_imm_packed = _uop_imm_packed_T_2; // @[decode.scala:479:17, :584:24] assign _uop_is_jal_T = uop_uopc == 7'h25; // @[decode.scala:479:17, :589:35] assign uop_is_jal = _uop_is_jal_T; // @[decode.scala:479:17, :589:35] assign _uop_is_jalr_T = uop_uopc == 7'h26; // @[decode.scala:479:17, :590:35] assign uop_is_jalr = _uop_is_jalr_T; // @[decode.scala:479:17, :590:35] assign io_deq_uop_uopc = io_deq_uop_uopc_0; // @[decode.scala:474:7] assign io_deq_uop_inst = io_deq_uop_inst_0; // @[decode.scala:474:7] assign io_deq_uop_debug_inst = io_deq_uop_debug_inst_0; // @[decode.scala:474:7] assign io_deq_uop_is_rvc = io_deq_uop_is_rvc_0; // @[decode.scala:474:7] assign io_deq_uop_debug_pc = io_deq_uop_debug_pc_0; // @[decode.scala:474:7] assign io_deq_uop_iq_type = io_deq_uop_iq_type_0; // @[decode.scala:474:7] assign io_deq_uop_fu_code = io_deq_uop_fu_code_0; // @[decode.scala:474:7] assign io_deq_uop_is_br = io_deq_uop_is_br_0; // @[decode.scala:474:7] assign io_deq_uop_is_jalr = io_deq_uop_is_jalr_0; // @[decode.scala:474:7] assign io_deq_uop_is_jal = io_deq_uop_is_jal_0; // @[decode.scala:474:7] assign io_deq_uop_is_sfb = io_deq_uop_is_sfb_0; // @[decode.scala:474:7] assign io_deq_uop_ftq_idx = io_deq_uop_ftq_idx_0; // @[decode.scala:474:7] assign io_deq_uop_edge_inst = io_deq_uop_edge_inst_0; // @[decode.scala:474:7] assign io_deq_uop_pc_lob = io_deq_uop_pc_lob_0; // @[decode.scala:474:7] assign io_deq_uop_taken = io_deq_uop_taken_0; // @[decode.scala:474:7] assign io_deq_uop_imm_packed = io_deq_uop_imm_packed_0; // @[decode.scala:474:7] assign io_deq_uop_exception = io_deq_uop_exception_0; // @[decode.scala:474:7] assign io_deq_uop_exc_cause = io_deq_uop_exc_cause_0; // @[decode.scala:474:7] assign io_deq_uop_bypassable = io_deq_uop_bypassable_0; // @[decode.scala:474:7] assign io_deq_uop_mem_cmd = io_deq_uop_mem_cmd_0; // @[decode.scala:474:7] assign io_deq_uop_mem_size = io_deq_uop_mem_size_0; // @[decode.scala:474:7] assign io_deq_uop_mem_signed = io_deq_uop_mem_signed_0; // @[decode.scala:474:7] assign io_deq_uop_is_fence = io_deq_uop_is_fence_0; // @[decode.scala:474:7] assign io_deq_uop_is_fencei = io_deq_uop_is_fencei_0; // @[decode.scala:474:7] assign io_deq_uop_is_amo = io_deq_uop_is_amo_0; // @[decode.scala:474:7] assign io_deq_uop_uses_ldq = io_deq_uop_uses_ldq_0; // @[decode.scala:474:7] assign io_deq_uop_uses_stq = io_deq_uop_uses_stq_0; // @[decode.scala:474:7] assign io_deq_uop_is_sys_pc2epc = io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:474:7] assign io_deq_uop_is_unique = io_deq_uop_is_unique_0; // @[decode.scala:474:7] assign io_deq_uop_flush_on_commit = io_deq_uop_flush_on_commit_0; // @[decode.scala:474:7] assign io_deq_uop_ldst = io_deq_uop_ldst_0; // @[decode.scala:474:7] assign io_deq_uop_lrs1 = io_deq_uop_lrs1_0; // @[decode.scala:474:7] assign io_deq_uop_lrs2 = io_deq_uop_lrs2_0; // @[decode.scala:474:7] assign io_deq_uop_lrs3 = io_deq_uop_lrs3_0; // @[decode.scala:474:7] assign io_deq_uop_ldst_val = io_deq_uop_ldst_val_0; // @[decode.scala:474:7] assign io_deq_uop_dst_rtype = io_deq_uop_dst_rtype_0; // @[decode.scala:474:7] assign io_deq_uop_lrs1_rtype = io_deq_uop_lrs1_rtype_0; // @[decode.scala:474:7] assign io_deq_uop_lrs2_rtype = io_deq_uop_lrs2_rtype_0; // @[decode.scala:474:7] assign io_deq_uop_frs3_en = io_deq_uop_frs3_en_0; // @[decode.scala:474:7] assign io_deq_uop_fp_val = io_deq_uop_fp_val_0; // @[decode.scala:474:7] assign io_deq_uop_fp_single = io_deq_uop_fp_single_0; // @[decode.scala:474:7] assign io_deq_uop_xcpt_pf_if = io_deq_uop_xcpt_pf_if_0; // @[decode.scala:474:7] assign io_deq_uop_xcpt_ae_if = io_deq_uop_xcpt_ae_if_0; // @[decode.scala:474:7] assign io_deq_uop_bp_debug_if = io_deq_uop_bp_debug_if_0; // @[decode.scala:474:7] assign io_deq_uop_bp_xcpt_if = io_deq_uop_bp_xcpt_if_0; // @[decode.scala:474:7] assign io_deq_uop_debug_fsrc = io_deq_uop_debug_fsrc_0; // @[decode.scala:474:7] assign io_csr_decode_inst = io_csr_decode_inst_0; // @[decode.scala:474:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module cc_banks_1( // @[DescribedSRAM.scala:17:26] input [14:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); cc_banks_0_ext cc_banks_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_297( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_41 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_110( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_5( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File TLChannelCompactor.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLBeat(val beatWidth: Int) extends Bundle { val payload = UInt(beatWidth.W) val head = Bool() val tail = Bool() } abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper { override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_") val beatWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val beat = Decoupled(new TLBeat(beatWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) q.io.enq <> io.protocol val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.beat.valid := protocol.valid protocol.ready := io.beat.ready && (is_body || !has_body) io.beat.bits.head := head && !is_body io.beat.bits.tail := tail && (is_body || !has_body) io.beat.bits.payload := Mux(is_body, body, const) when (io.beat.fire && io.beat.bits.head) { is_body := true.B } when (io.beat.fire && io.beat.bits.tail) { is_body := false.B } } abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper { override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_") val beatWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val beat = Flipped(Decoupled(new TLBeat(beatWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) io.protocol <> protocol val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg) io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.beat.bits.payload, body_fields) when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload } when (io.beat.fire && io.beat.bits.tail) { is_const := true.B } } class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) } class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) { when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) } class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) { when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) } class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p) class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) { has_body := edgeOut.hasData(protocol.bits) } class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p) class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) } class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p) File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLEToBeat_SerialRAM_a64d64s8k8z8c( // @[TLChannelCompactor.scala:136:7] input clock, // @[TLChannelCompactor.scala:136:7] input reset, // @[TLChannelCompactor.scala:136:7] input io_beat_ready, // @[TLChannelCompactor.scala:40:14] output io_beat_bits_head // @[TLChannelCompactor.scala:40:14] ); wire io_beat_ready_0 = io_beat_ready; // @[TLChannelCompactor.scala:136:7] wire [8:0] head_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] tail_count = 9'h0; // @[Edges.scala:234:25] wire [7:0] io_protocol_bits_sink = 8'h0; // @[TLChannelCompactor.scala:136:7] wire [7:0] io_beat_bits_payload = 8'h0; // @[TLChannelCompactor.scala:136:7] wire [7:0] _io_beat_bits_payload_T = 8'h0; // @[TLChannelCompactor.scala:66:33] wire io_protocol_valid = 1'h0; // @[TLChannelCompactor.scala:136:7] wire io_beat_valid = 1'h0; // @[TLChannelCompactor.scala:136:7] wire has_body = 1'h0; // @[TLChannelCompactor.scala:51:22] wire _head_T = 1'h0; // @[Decoupled.scala:51:35] wire head_done = 1'h0; // @[Edges.scala:233:22] wire _tail_T = 1'h0; // @[Decoupled.scala:51:35] wire tail_done = 1'h0; // @[Edges.scala:233:22] wire io_protocol_ready = 1'h1; // @[TLChannelCompactor.scala:136:7] wire io_beat_bits_tail = 1'h1; // @[TLChannelCompactor.scala:136:7] wire _head_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire head_last = 1'h1; // @[Edges.scala:232:33] wire _tail_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire tail = 1'h1; // @[Edges.scala:232:33] wire _q_io_deq_ready_T = 1'h1; // @[TLChannelCompactor.scala:62:50] wire _q_io_deq_ready_T_1 = 1'h1; // @[TLChannelCompactor.scala:62:47] wire _io_beat_bits_tail_T = 1'h1; // @[TLChannelCompactor.scala:65:50] wire _io_beat_bits_tail_T_1 = 1'h1; // @[TLChannelCompactor.scala:65:47] wire _io_beat_bits_tail_T_2 = 1'h1; // @[TLChannelCompactor.scala:65:35] wire _q_io_deq_ready_T_2 = io_beat_ready_0; // @[TLChannelCompactor.scala:62:35, :136:7] wire _io_beat_bits_head_T_1; // @[TLChannelCompactor.scala:64:35] wire io_beat_bits_head_0; // @[TLChannelCompactor.scala:136:7] reg [8:0] head_counter; // @[Edges.scala:229:27] wire [9:0] _head_counter1_T = {1'h0, head_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] head_counter1 = _head_counter1_T[8:0]; // @[Edges.scala:230:28] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _head_last_T = head_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _head_count_T = ~head_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _head_counter_T = head ? 9'h0 : head_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [8:0] tail_counter; // @[Edges.scala:229:27] wire [9:0] _tail_counter1_T = {1'h0, tail_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] tail_counter1 = _tail_counter1_T[8:0]; // @[Edges.scala:230:28] wire tail_first = tail_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _tail_last_T = tail_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _tail_count_T = ~tail_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _tail_counter_T = tail_first ? 9'h0 : tail_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg is_body; // @[TLChannelCompactor.scala:60:24] wire _io_beat_bits_head_T = ~is_body; // @[TLChannelCompactor.scala:60:24, :64:38] assign _io_beat_bits_head_T_1 = head & _io_beat_bits_head_T; // @[TLChannelCompactor.scala:64:{35,38}] assign io_beat_bits_head_0 = _io_beat_bits_head_T_1; // @[TLChannelCompactor.scala:64:35, :136:7] always @(posedge clock) begin // @[TLChannelCompactor.scala:136:7] if (reset) begin // @[TLChannelCompactor.scala:136:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TLChannelCompactor.scala:60:24] end always @(posedge) Queue1_TLBundleE_a64d64s8k8z8c q ( // @[TLChannelCompactor.scala:47:17] .clock (clock), .reset (reset), .io_deq_ready (_q_io_deq_ready_T_2) // @[TLChannelCompactor.scala:62:35] ); // @[TLChannelCompactor.scala:47:17] assign io_beat_bits_head = io_beat_bits_head_0; // @[TLChannelCompactor.scala:136:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }
module MulAddRecFNToRaw_postMul_e8_s24_47( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49] wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SRAM.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} import freechips.rocketchip.resources.{Device, DeviceRegName, DiplomaticSRAM, HasJustOneSeqMem} import freechips.rocketchip.util.{CanHaveErrors, ECCParams, property, SECDEDCode} import freechips.rocketchip.util.DataToAugmentedData import freechips.rocketchip.util.BooleanToAugmentedBoolean class TLRAMErrors(val params: ECCParams, val addrBits: Int) extends Bundle with CanHaveErrors { val correctable = (params.code.canCorrect && params.notifyErrors).option(Valid(UInt(addrBits.W))) val uncorrectable = (params.code.canDetect && params.notifyErrors).option(Valid(UInt(addrBits.W))) } class TLRAM( address: AddressSet, cacheable: Boolean = true, executable: Boolean = true, atomics: Boolean = false, beatBytes: Int = 4, ecc: ECCParams = ECCParams(), sramReg: Boolean = false, // drive SRAM data output directly into a register => 1 cycle longer response val devName: Option[String] = None, val dtsCompat: Option[Seq[String]] = None, val devOverride: Option[Device with DeviceRegName] = None )(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName, dtsCompat, devOverride) { val eccBytes = ecc.bytes val code = ecc.code require (eccBytes >= 1 && isPow2(eccBytes)) require (beatBytes >= 1 && isPow2(beatBytes)) require (eccBytes <= beatBytes, s"TLRAM eccBytes (${eccBytes}) > beatBytes (${beatBytes}). Use a WidthWidget=>Fragmenter=>SRAM if you need high density and narrow ECC; it will do bursts efficiently") val node = TLManagerNode(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = List(address), resources = resources, regionType = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT, executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), supportsArithmetic = if (atomics) TransferSizes(1, beatBytes) else TransferSizes.none, supportsLogical = if (atomics) TransferSizes(1, beatBytes) else TransferSizes.none, fifoId = Some(0)).v2copy(name=devName)), // requests are handled in order beatBytes = beatBytes, minLatency = 1))) // no bypass needed for this device val notifyNode = ecc.notifyErrors.option(BundleBridgeSource(() => new TLRAMErrors(ecc, log2Ceil(address.max)).cloneType)) private val outer = this lazy val module = new Impl class Impl extends LazyModuleImp(this) with HasJustOneSeqMem { val (in, edge) = node.in(0) val indexBits = (outer.address.mask & ~(beatBytes-1)).bitCount val width = code.width(eccBytes*8) val lanes = beatBytes/eccBytes val mem = makeSinglePortedByteWriteSeqMem( size = BigInt(1) << indexBits, lanes = lanes, bits = width) val eccCode = Some(ecc.code) val address = outer.address val laneDataBits = eccBytes * 8 /* This block has a three-stage pipeline * Stage A is the combinational request from TileLink A channel * Stage R corresponds to an accepted request * Stage D registers the result of an SRAM read (if any) * * The TileLink D channel response comes from * - stage D for corected reads or AMOs * - stage R for everything else * - However, to increase maximum operating frequency, the * stage R responses can be configured to come from stage D * * For sub-ECC granule writes and atomic operations: * - stage A sets up the read for the old data value * - stage R is used to gather the result from SRAM to registers * - stage D corrects ECC, applies the ALU, and sets up SRAM write * * For super-ECC granule writes: * - stage A sets up the write * * For reads: * - stage A sets up the read * - stage R drives the uncorrected data with valid based on ECC validity * - stage D sets up the correction, if any * * When stage D needs to perform a write (AMO, sub-ECC write, or ECC correction): * - there is a WaW or WaR hazard vs. the operation in stage R * - for sub-ECC writes and atomics, we ensure stage R has a bubble * - for ECC correction, we cause stage R to be replayed (and reject stage A twice) * - there is a structural hazard competing with stage A for SRAM access * - stage D always wins (stage A is rejected) * - on ECC correction, there is a structural hazard competing with stage R for the response channel * - stage D always wins (stage R is replayed) */ // D stage registers from R val d_full = RegInit(false.B) val d_respond = Reg(Bool()) val d_opcode = Reg(UInt(3.W)) val d_param = Reg(UInt(3.W)) val d_size = Reg(UInt(edge.bundle.sizeBits.W)) val d_source = Reg(UInt(edge.bundle.sourceBits.W)) val d_read = Reg(Bool()) val d_atomic = Reg(Bool()) val d_sublane = Reg(Bool()) val d_address = Reg(UInt(edge.bundle.addressBits.W)) val d_mask = Reg(UInt(beatBytes.W)) val d_rmw_data = Reg(UInt((8*beatBytes).W)) val d_poison = Reg(Bool()) val d_raw_data = Reg(Vec(lanes, Bits(width.W))) // R stage registers from A val r_full = RegInit(false.B) val r_opcode = Reg(UInt(3.W)) val r_param = Reg(UInt(3.W)) val r_size = Reg(UInt(edge.bundle.sizeBits.W)) val r_source = Reg(UInt(edge.bundle.sourceBits.W)) val r_read = Reg(Bool()) val r_atomic = Reg(Bool()) val r_sublane = Reg(Bool()) val r_address = Reg(UInt(edge.bundle.addressBits.W)) val r_mask = Reg(UInt(beatBytes.W)) val r_rmw_data = Reg(UInt((8*beatBytes).W)) val r_poison = Reg(Bool()) val r_raw_data = Wire(Vec(lanes, Bits(width.W))) // Decode raw SRAM output val d_decoded = d_raw_data.map(lane => code.decode(lane)) val d_corrected = Cat(d_decoded.map(_.corrected).reverse) val d_uncorrected = Cat(d_decoded.map(_.uncorrected).reverse) val d_correctable = d_decoded.map(_.correctable) val d_uncorrectable = d_decoded.map(_.uncorrectable) val d_need_fix = d_correctable.reduce(_ || _) val d_lanes = Cat(Seq.tabulate(lanes) { i => d_mask(eccBytes*(i+1)-1, eccBytes*i).orR }.reverse) val d_lane_error = Cat(d_uncorrectable.reverse) & d_lanes val d_error = d_lane_error.orR val r_decoded = r_raw_data.map(lane => code.decode(lane)) val r_corrected = Cat(r_decoded.map(_.corrected).reverse) val r_uncorrected = Cat(r_decoded.map(_.uncorrected).reverse) val r_correctable = r_decoded.map(_.correctable) val r_uncorrectable = r_decoded.map(_.uncorrectable) val r_need_fix = r_correctable.reduce(_ || _) val r_lanes = Cat(Seq.tabulate(lanes) { i => r_mask(eccBytes*(i+1)-1, eccBytes*i).orR }.reverse) val r_lane_error = Cat(r_uncorrectable.reverse) & r_lanes val r_error = r_lane_error.orR // Out-of-band notification of any faults notifyNode.foreach { nnode => nnode.bundle.correctable.foreach { c => c.valid := d_need_fix && d_full && (d_atomic || d_read || d_sublane) c.bits := d_address } nnode.bundle.uncorrectable.foreach { u => u.valid := d_error && d_full && (d_atomic || d_read || d_sublane) u.bits := d_address } } // What does D-stage want to write-back? // Make an ALU if we need one val d_updated = if (atomics) { val alu = Module(new Atomics(edge.bundle)) alu.io.write := false.B alu.io.a.opcode := d_opcode alu.io.a.param := d_param alu.io.a.size := d_size alu.io.a.source := 0.U alu.io.a.address := 0.U alu.io.a.data := d_rmw_data alu.io.a.mask := d_mask alu.io.a.corrupt := false.B alu.io.data_in := d_corrected alu.io.data_out } else { Cat(Seq.tabulate(beatBytes) { i => val upd = d_mask(i) && !d_read val rmw = d_rmw_data (8*(i+1)-1, 8*i) val fix = d_corrected(8*(i+1)-1, 8*i) // safe to use, because D-stage write-back always wins arbitration Mux(upd, rmw, fix) }.reverse) } // Stage D always wins control of the response channel val d_win = d_full && d_respond val d_mux = if (sramReg) true.B else d_win val out_aad = Mux(d_mux, d_read || d_atomic, r_read || r_atomic) in.d.bits.opcode := Mux(out_aad, TLMessages.AccessAckData, TLMessages.AccessAck) in.d.bits.param := 0.U in.d.bits.size := Mux(d_mux, d_size, r_size) in.d.bits.source := Mux(d_mux, d_source, r_source) in.d.bits.sink := 0.U in.d.bits.denied := false.B in.d.bits.data := Mux(d_mux, d_corrected, r_uncorrected) in.d.bits.corrupt := Mux(d_mux, d_error, r_error) && out_aad val mem_active_valid = Seq(property.CoverBoolean(in.d.valid, Seq("mem_active"))) val data_error = Seq( property.CoverBoolean(!d_need_fix && !d_error , Seq("no_data_error")), property.CoverBoolean(d_need_fix && !in.d.bits.corrupt, Seq("data_correctable_error_not_reported")), property.CoverBoolean(d_error && in.d.bits.corrupt, Seq("data_uncorrectable_error_reported"))) val error_cross_covers = new property.CrossProperty(Seq(mem_active_valid, data_error), Seq(), "Ecc Covers") property.cover(error_cross_covers) // Does the D stage want to perform a write? // It's important this reduce to false.B when eccBytes=1 && atomics=false && canCorrect=false val d_wb = d_full && (d_sublane || d_atomic || (d_read && d_need_fix)) // Formulate an R response unless there is a data output fix to perform // It's important this reduce to false.B for sramReg and true.B for !code.canCorrect val r_respond = !sramReg.B && (!r_need_fix || !(r_read || r_atomic)) // Resolve WaW and WaR hazard when D performs an update (only happens on ECC correction) // It's important this reduce to false.B unless code.canDetect val r_replay = RegNext(r_full && d_full && d_read && d_need_fix) // r_full && d_wb => read ecc fault (we insert a buble for atomic/sublane) assert (!(r_full && d_wb) || (d_full && d_read && d_need_fix)) // Pipeline control in.d.valid := (d_full && d_respond) || (r_full && r_respond && !d_wb && !r_replay) val d_ready = !d_respond || in.d.ready val r_ready = !d_wb && !r_replay && (!d_full || d_ready) && (!r_respond || (!d_win && in.d.ready)) in.a.ready := !(d_full && d_wb) && (!r_full || r_ready) && (!r_full || !(r_atomic || r_sublane)) // ignore sublane if it is a read or mask is all set val a_read = in.a.bits.opcode === TLMessages.Get val a_sublane = if (eccBytes == 1) false.B else ~a_read && (((in.a.bits.opcode === TLMessages.PutPartialData) && (~in.a.bits.mask.andR)) || in.a.bits.size < log2Ceil(eccBytes).U) val a_atomic = if (!atomics) false.B else in.a.bits.opcode === TLMessages.ArithmeticData || in.a.bits.opcode === TLMessages.LogicalData // Forward pipeline stage from R to D when (d_ready) { d_full := false.B } when (r_full && r_ready) { d_full := true.B d_respond := !r_respond d_opcode := r_opcode d_param := r_param d_size := r_size d_source := r_source d_read := r_read d_atomic := r_atomic d_sublane := r_sublane d_address := r_address d_mask := r_mask d_rmw_data := r_rmw_data d_poison := r_poison d_raw_data := r_raw_data } // Forward pipeline stage from A to R when (r_ready) { r_full := false.B } when (in.a.fire) { r_full := true.B r_sublane := a_sublane r_opcode := in.a.bits.opcode r_param := in.a.bits.param r_size := in.a.bits.size r_source := in.a.bits.source r_read := a_read r_atomic := a_atomic r_sublane := a_sublane r_address := in.a.bits.address r_poison := in.a.bits.corrupt r_mask := in.a.bits.mask when (!a_read) { r_rmw_data := in.a.bits.data } } // Split data into eccBytes-sized chunks: val a_data = VecInit(Seq.tabulate(lanes) { i => in.a.bits.data(eccBytes*8*(i+1)-1, eccBytes*8*i) }) val r_data = VecInit(Seq.tabulate(lanes) { i => r_rmw_data(eccBytes*8*(i+1)-1, eccBytes*8*i) }) val d_data = VecInit(Seq.tabulate(lanes) { i => d_updated(8*eccBytes*(i+1)-1, 8*eccBytes*i) }) // Which data chunks get poisoned val a_poisonv = VecInit(Seq.fill(lanes) { in.a.bits.corrupt }) val r_poisonv = VecInit(Seq.fill(lanes) { r_poison }) val d_poisonv = VecInit(Seq.tabulate(lanes) { i => val upd = d_mask(eccBytes*(i+1)-1, eccBytes*i) (!upd.andR && d_uncorrectable(i)) || d_poison // sub-lane writes should not correct uncorrectable }) val a_lanes = Cat(Seq.tabulate(lanes) { i => in.a.bits.mask(eccBytes*(i+1)-1, eccBytes*i).orR }.reverse) // SRAM arbitration val a_fire = in.a.fire val a_ren = a_read || a_atomic || a_sublane val r_ren = r_read || r_atomic || r_sublane val wen = d_wb || Mux(r_replay, !r_ren, a_fire && !a_ren) val ren = !wen && (a_fire || r_replay) // help Chisel infer a RW-port val addr = Mux(d_wb, d_address, Mux(r_replay, r_address, in.a.bits.address)) val sel = Mux(d_wb, d_lanes, Mux(r_replay, r_lanes, a_lanes)) val dat = Mux(d_wb, d_data, Mux(r_replay, r_data, a_data)) val poison = Mux(d_wb, d_poisonv, Mux(r_replay, r_poisonv, a_poisonv)) val coded = VecInit((dat zip poison) map { case (d, p) => if (code.canDetect) code.encode(d, p) else code.encode(d) }) val index = Cat(mask.zip((addr >> log2Ceil(beatBytes)).asBools).filter(_._1).map(_._2).reverse) r_raw_data := mem.read(index, ren) holdUnless RegNext(ren) when (wen) { mem.write(index, coded, sel.asBools) } // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B } } object TLRAM { def apply( address: AddressSet, cacheable: Boolean = true, executable: Boolean = true, atomics: Boolean = false, beatBytes: Int = 4, ecc: ECCParams = ECCParams(), sramReg: Boolean = false, devName: Option[String] = None, )(implicit p: Parameters): TLInwardNode = { val ram = LazyModule(new TLRAM(address, cacheable, executable, atomics, beatBytes, ecc, sramReg, devName)) ram.node } } // Synthesizable unit testing import freechips.rocketchip.unittest._ class TLRAMSimple(ramBeatBytes: Int, sramReg: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("SRAMSimple")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes, sramReg = sramReg)) ram.node := TLDelayer(0.25) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMSimpleTest(ramBeatBytes: Int, sramReg: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMSimple(ramBeatBytes, sramReg, txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLRAMECC(ramBeatBytes: Int, eccBytes: Int, sramReg: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("SRAMSimple")) val ram = LazyModule(new TLRAM( AddressSet(0x0, 0x3ff), atomics = true, beatBytes = ramBeatBytes, ecc = ECCParams(bytes = eccBytes, code = new SECDEDCode), sramReg = sramReg)) ram.node := TLDelayer(0.25) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMECCTest(ramBeatBytes: Int, eccBytes: Int, sramReg: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMECC(ramBeatBytes, eccBytes, sramReg, txns)).module) dut.io.start := io.start io.finished := dut.io.finished } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module TLRAM_ScratchpadBank( // @[SRAM.scala:63:9] input clock, // @[SRAM.scala:63:9] input reset, // @[SRAM.scala:63:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire [7:0] r_raw_data_7; // @[package.scala:88:63] wire [7:0] r_raw_data_6; // @[package.scala:88:63] wire [7:0] r_raw_data_5; // @[package.scala:88:63] wire [7:0] r_raw_data_4; // @[package.scala:88:63] wire [7:0] r_raw_data_3; // @[package.scala:88:63] wire [7:0] r_raw_data_2; // @[package.scala:88:63] wire [7:0] r_raw_data_1; // @[package.scala:88:63] wire [7:0] r_raw_data_0; // @[package.scala:88:63] wire ren; // @[SRAM.scala:306:20] wire mem_MPORT_1_en; // @[SRAM.scala:305:52] wire [63:0] _mem_RW0_rdata; // @[DescribedSRAM.scala:17:26] reg r_full; // @[SRAM.scala:128:30] reg [1:0] r_size; // @[SRAM.scala:131:26] reg [7:0] r_source; // @[SRAM.scala:132:26] reg r_read; // @[SRAM.scala:133:26] wire [2:0] nodeIn_d_bits_opcode = {2'h0, r_read}; // @[SRAM.scala:133:26, :203:23] wire nodeIn_a_ready = ~r_full | auto_in_d_ready; // @[SRAM.scala:128:30, :237:{41,49}] wire a_fire = nodeIn_a_ready & auto_in_a_valid; // @[Decoupled.scala:51:35] assign mem_MPORT_1_en = a_fire & auto_in_a_bits_opcode != 3'h4; // @[Decoupled.scala:51:35] assign ren = ~mem_MPORT_1_en & a_fire; // @[Decoupled.scala:51:35] reg REG; // @[SRAM.scala:317:58] reg [7:0] r_0; // @[package.scala:88:63] reg [7:0] r_1; // @[package.scala:88:63] reg [7:0] r_2; // @[package.scala:88:63] reg [7:0] r_3; // @[package.scala:88:63] reg [7:0] r_4; // @[package.scala:88:63] reg [7:0] r_5; // @[package.scala:88:63] reg [7:0] r_6; // @[package.scala:88:63] reg [7:0] r_7; // @[package.scala:88:63] assign r_raw_data_0 = REG ? _mem_RW0_rdata[7:0] : r_0; // @[package.scala:88:63] assign r_raw_data_1 = REG ? _mem_RW0_rdata[15:8] : r_1; // @[package.scala:88:63] assign r_raw_data_2 = REG ? _mem_RW0_rdata[23:16] : r_2; // @[package.scala:88:63] assign r_raw_data_3 = REG ? _mem_RW0_rdata[31:24] : r_3; // @[package.scala:88:63] assign r_raw_data_4 = REG ? _mem_RW0_rdata[39:32] : r_4; // @[package.scala:88:63] assign r_raw_data_5 = REG ? _mem_RW0_rdata[47:40] : r_5; // @[package.scala:88:63] assign r_raw_data_6 = REG ? _mem_RW0_rdata[55:48] : r_6; // @[package.scala:88:63] assign r_raw_data_7 = REG ? _mem_RW0_rdata[63:56] : r_7; // @[package.scala:88:63] always @(posedge clock) begin // @[SRAM.scala:63:9] if (reset) // @[SRAM.scala:63:9] r_full <= 1'h0; // @[SRAM.scala:128:30] else // @[SRAM.scala:63:9] r_full <= a_fire | ~auto_in_d_ready & r_full; // @[Decoupled.scala:51:35] if (a_fire) begin // @[Decoupled.scala:51:35] r_size <= auto_in_a_bits_size; // @[SRAM.scala:131:26] r_source <= auto_in_a_bits_source; // @[SRAM.scala:132:26] r_read <= auto_in_a_bits_opcode == 3'h4; // @[SRAM.scala:133:26, :240:35] end REG <= ren; // @[SRAM.scala:306:20, :317:58] if (REG) begin // @[SRAM.scala:317:58] r_0 <= _mem_RW0_rdata[7:0]; // @[package.scala:88:63] r_1 <= _mem_RW0_rdata[15:8]; // @[package.scala:88:63] r_2 <= _mem_RW0_rdata[23:16]; // @[package.scala:88:63] r_3 <= _mem_RW0_rdata[31:24]; // @[package.scala:88:63] r_4 <= _mem_RW0_rdata[39:32]; // @[package.scala:88:63] r_5 <= _mem_RW0_rdata[47:40]; // @[package.scala:88:63] r_6 <= _mem_RW0_rdata[55:48]; // @[package.scala:88:63] r_7 <= _mem_RW0_rdata[63:56]; // @[package.scala:88:63] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLWidthWidget8( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [31:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [31:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [31:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [7:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [31:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:32]; // @[Repeater.scala:36:26] wire [31:0] _cated_bits_data_T_1 = anonIn_a_bits_data[31:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [17:0] _repeat_limit_T = 18'h7 << cated_bits_size; // @[package.scala:243:71] wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire repeat_limit = _repeat_limit_T_2[2]; // @[package.scala:243:46] reg repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24] wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24] wire repeat_sel = cated_bits_address[2]; // @[WidthWidget.scala:116:39, :161:25] wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [31:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[31:0]; // @[WidthWidget.scala:128:55, :161:25] wire [31:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [31:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[63:32]; // @[WidthWidget.scala:128:55, :161:25] wire [31:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_data = repeat_index ? repeat_anonOut_a_bits_data_mux_1 : repeat_anonOut_a_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30] wire [3:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[3:0]; // @[WidthWidget.scala:128:55, :161:25] wire [3:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [3:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[7:4]; // @[WidthWidget.scala:128:55, :161:25] wire [3:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_mask = repeat_index ? repeat_anonOut_a_bits_mask_mux_1 : repeat_anonOut_a_bits_mask_mux_0; // @[WidthWidget.scala:126:24, :128:43, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [17:0] _limit_T = 18'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire limit = _limit_T_2[2]; // @[package.scala:243:46] reg count; // @[WidthWidget.scala:40:27] wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = ~count; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56] wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24] wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [31:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] wire [31:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [31:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 1'h0; // @[WidthWidget.scala:105:26] count <= 1'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] always @(posedge) TLMonitor_3 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a32d64s5k3z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_334( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_78 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_10( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File FSECompressorDicBuilder.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import ZstdConsts._ class FSECompTransformationTable extends Bundle { val nbbit = UInt(32.W) val findstate = UInt(32.W) val from_last_symbol = Bool() } class FSECompressorDicBuilderIO(val interleave_cnt: Int)(implicit p: Parameters) extends Bundle { val nb_seq = Flipped(Decoupled(UInt(64.W))) val ll_stream = Flipped(new MemLoaderConsumerBundle) val ll_table_log = Decoupled(UInt(4.W)) val symbol_info = Vec(interleave_cnt, Flipped(Decoupled(new FSESymbolInfo))) val symbolTT_info = Vec(interleave_cnt, Decoupled(new FSECompTransformationTable)) val state_table_idx = Vec(interleave_cnt, Input(UInt(16.W))) val new_state = Vec(interleave_cnt, Valid(UInt(16.W))) val header_writes = Decoupled(new WriterBundle) val predefined_mode = Decoupled(Bool()) val lookup_done = Flipped(Decoupled(Bool())) } // NOTE : about 4 * 2^tableLog Bytes of on-chip regs class FSECompressorDicBuilder( val printInfo: String, val interleave_cnt: Int, val as_zstd_submodule: Boolean, val max_symbol_value: Int, val max_table_log: Int, val predefined_table_log: Int, val mark_end_of_header: Boolean = false) (implicit p: Parameters) extends Module { val io = IO(new FSECompressorDicBuilderIO(interleave_cnt)) def BIT_highbit32(x: UInt): UInt = { // add assertion about x width? val highBit = 31.U - PriorityEncoder(Reverse(x)) highBit } val rtbTable_initialized = RegInit(false.B) val rtbTable = RegInit(VecInit(Seq.fill(8)(0.U(32.W)))) when (!rtbTable_initialized) { rtbTable(0) := 0.U rtbTable(1) := 473195.U rtbTable(2) := 504333.U rtbTable(3) := 520860.U rtbTable(4) := 550000.U rtbTable(5) := 700000.U rtbTable(6) := 750000.U rtbTable(7) := 830000.U rtbTable_initialized := true.B } val LL_symbolTTDeltaNbBitsDefaultValues = List( 327552, 327584, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393152, 393152, 393152, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 393088, 327584, 393088, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152 ) val LL_symbolTTDeltaFindStateDefaultValues = List( -4, 1, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 28, 29, 30, 30, 32, 34, 36, 38, 40, 42, 44, 46, 47, 51, 54, 55, 56, 57, 58, 59, 60, 61, 62 ) val LL_DefaultTableU16 = List( 64, 65, 86, 107, 66, 87, 108, 88, 109, 67, 110, 68, 89, 90, 111, 69, 112, 70, 91, 92, 113, 71, 114, 72, 93, 94, 115, 73, 116, 95, 74, 117, 75, 96, 97, 118, 76, 119, 77, 98, 99, 120, 78, 121, 79, 100, 101, 122, 80, 123, 81, 102, 103, 82, 104, 83, 105, 84, 106, 85, 127, 126, 125, 124 ) val OF_symbolTTDeltaNbBitsDefaultValues = List( 327648, 327648, 327648, 327648, 327648, 327648, 327616, 327616, 327616, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648, 327648 ) val OF_symbolTTDeltaFindStateDefaultValues = List( -1, 0, 1, 2, 3, 4, 4, 6, 8, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 ) val OF_DefaultTableU16 = List( 32, 55, 46, 37, 51, 42, 33, 56, 38, 47, 43, 52, 34, 57, 48, 39, 53, 44, 35, 58, 49, 40, 54, 45, 36, 50, 41, 63, 62, 61, 60, 59 ) val ML_symbolTTDeltaNbBitsDefaultValues = List( 393152, 327552, 327584, 393088, 393088, 393088, 393088, 393088, 393088, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152, 393152 ) val ML_symbolTTDeltaFindStateDefaultValues = List( -1, -3, 2, 6, 8, 10, 12, 14, 16, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62 ) val ML_DefaultTableU16 = List( 64, 65, 86, 107, 108, 66, 87, 109, 67, 88, 89, 110, 68, 111, 69, 90, 91, 112, 70, 113, 92, 71, 114, 93, 72, 115, 94, 73, 116, 95, 74, 117, 96, 75, 118, 97, 76, 119, 98, 77, 120, 99, 78, 100, 79, 101, 80, 102, 81, 103, 82, 104, 83, 105, 84, 106, 85, 127, 126, 125, 124, 123, 122, 121 ) // Tie up wires io.ll_stream.output_ready := false.B io.ll_stream.user_consumed_bytes := 0.U io.nb_seq.ready := false.B val predefined_mode_q = Module(new Queue(Bool(), 4)) predefined_mode_q.io.enq.valid := false.B predefined_mode_q.io.enq.bits := false.B io.predefined_mode <> predefined_mode_q.io.deq val sIdle = 0.U val sCount = 1.U val sNormalizeCount = 2.U val sBuildCTableSymbolStartPositions = 3.U val sBuildCTableSpreadSymbols = 4.U val sBuildCTableBuildTable = 5.U val sBuildCTableSymbolTT = 6.U val sWriteCTable = 7.U val sLookup = 8.U val dicBuilderState = RegInit(0.U(4.W)) val COLLECT_STAT_PROCESS_BYTES = p(FSECompressDicBuilderProcessedStatBytesPerCycle) val COLLECT_STAT_PROCESS_BYTES_LOG2 = log2Ceil(COLLECT_STAT_PROCESS_BYTES + 1) val tableLogLL = max_table_log // Always use maximum possible tableLog since dictionary lookups are basically free??????? val maxSymbolLL = max_symbol_value val maxSymbolLLPlus1 = max_symbol_value + 1 /////////////////////////////////////////////////////////////////////////// // sCount /////////////////////////////////////////////////////////////////////////// val ll_count = RegInit(VecInit(Seq.fill(maxSymbolLLPlus1)(0.U(32.W)))) val ll_max_symbol_value = RegInit(0.U(32.W)) val ll_nbseq_1 = RegInit(0.U(64.W)) val input_ll_symbols = WireInit(VecInit(Seq.fill(COLLECT_STAT_PROCESS_BYTES)(0.U(8.W)))) for (i <- 0 until COLLECT_STAT_PROCESS_BYTES) { input_ll_symbols(i) := io.ll_stream.output_data >> (i*8).U } dontTouch(input_ll_symbols) val avail_bytes = io.ll_stream.available_output_bytes val table = Seq.fill(maxSymbolLLPlus1)(WireInit(VecInit(Seq.fill(COLLECT_STAT_PROCESS_BYTES)(0.U(1.W))))) for (i <- 0 until maxSymbolLLPlus1) { for (j <- 0 until COLLECT_STAT_PROCESS_BYTES) { table(i)(j) := Mux(j.U < avail_bytes && (input_ll_symbols(j) === i.U), 1.U, 0.U) } } val stat_sum = WireInit(VecInit(Seq.fill(maxSymbolLLPlus1)(0.U(COLLECT_STAT_PROCESS_BYTES_LOG2.W)))) for (i <- 0 until maxSymbolLLPlus1) { stat_sum(i) := table(i).reduce(_ +& _) } val has_value = WireInit(VecInit(Seq.fill(maxSymbolLLPlus1)(0.U(1.W)))) for (i <- 0 until maxSymbolLLPlus1) { has_value(i) := Mux(stat_sum(i) > 0.U, 1.U, 0.U) } val has_value_cat = Cat(has_value) val cur_max_value = (maxSymbolLLPlus1 - 1).U - PriorityEncoder(has_value_cat) when (dicBuilderState === sCount) { when (io.ll_stream.output_valid) { for (i <- 0 until maxSymbolLLPlus1) { ll_count(i) := ll_count(i) + stat_sum(i) } ll_max_symbol_value := Mux(ll_max_symbol_value > cur_max_value, ll_max_symbol_value, cur_max_value) } } /////////////////////////////////////////////////////////////////////////// // sNormalizeCount (FSE_normalizeCount) /////////////////////////////////////////////////////////////////////////// /* * { static U32 const rtbTable[] = { 0, 473195, 504333, 520860, 550000, 700000, 750000, 830000 }; * short const lowProbCount = useLowProbCount ? -1 : 1; * U64 const scale = 62 - tableLog; * U64 const step = ZSTD_div64((U64)1<<62, (U32)total); * U64 const vStep = 1ULL<<(scale-20); * int stillToDistribute = 1<<tableLog; * unsigned s; * unsigned largest=0; * short largestP=0; * U32 lowThreshold = (U32)(total >> tableLog); * for (s=0; s<=maxSymbolValue; s++) { * if (count[s] == total) return 0; // rle special case * if (count[s] == 0) { normalizedCounter[s]=0; continue; } * if (count[s] <= lowThreshold) { * normalizedCounter[s] = lowProbCount; * stillToDistribute--; * } else { * short proba = (short)((count[s]*step) >> scale); * if (proba<8) { * U64 restToBeat = vStep * rtbTable[proba]; * proba += (count[s]*step) - ((U64)proba<<scale) > restToBeat; * } * if (proba > largestP) { largestP=proba; largest=s; } * normalizedCounter[s] = proba; * stillToDistribute -= proba; * } } * if (-stillToDistribute >= (normalizedCounter[largest] >> 1)) { * // corner case, need another normalization method * size_t const errorCode = FSE_normalizeM2(normalizedCounter, tableLog, count, total, maxSymbolValue, lowProbCount); * if (FSE_isError(errorCode)) return errorCode; * } * else normalizedCounter[largest] += (short)stillToDistribute; */ val neg_one_uint16 = (1 << 16) - 1 // val ll_useLowProbCount = ll_nbseq_1 >= 2048.U // don't use lowProb stuff for now, (small comp ratio gains for thousands of cycle tradeoff) val ll_useLowProbCount = ll_nbseq_1 >= BigInt("FFFFFFFF", 16).U val ll_lowProbCount = Wire(UInt(16.W)) ll_lowProbCount := Mux(ll_useLowProbCount, neg_one_uint16.U, 1.U) val ll_scale = Wire(UInt(7.W)) ll_scale := 62.U - tableLogLL.U val ll_step = Wire(UInt(64.W)) ll_step := BigInt("4000000000000000", 16).U / ll_nbseq_1 val ll_scale_20 = Wire(UInt(7.W)) ll_scale_20 := ll_scale - 20.U val ll_vStep = Wire(UInt(64.W)) ll_vStep := 1.U << ll_scale_20 val ll_still_to_distribute = (1 << tableLogLL).U val ll_lowThreshold = Wire(UInt(32.W)) ll_lowThreshold := ll_nbseq_1 >> tableLogLL.U val ll_proba_base = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_proba = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_count_times_step = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(64.W)))) for (i <- 0 until maxSymbolLL + 1) { ll_count_times_step(i) := ll_count(i) * ll_step ll_proba_base(i) := ll_count_times_step(i) >> ll_scale val restToBeat = ll_vStep * rtbTable(ll_proba_base(i)) val ll_add_to_proba_base = Mux(ll_count(i) * ll_step - (ll_proba_base(i) << ll_scale) > restToBeat, 1.U, 0.U) ll_proba(i) := Mux(ll_proba_base(i) < 8.U, ll_proba_base(i) + ll_add_to_proba_base, ll_proba_base(i)) } val ll_normalizedCounter = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_normalizedCounterMaxAdjusted = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_count_has_nbseq_1_as_value = ll_count.map{ case count => count === ll_nbseq_1 }.reduce(_ || _) val ll_rle = ll_count_has_nbseq_1_as_value for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounter(i) := Mux(ll_count(i) === 0.U, 0.U, Mux(ll_count(i) <= ll_lowThreshold, ll_lowProbCount, ll_proba(i))) } val ll_smallOrEqToLowThresholdCount = ll_count.map{ case count => ((count <= ll_lowThreshold) && (count > 0.U)).asUInt }.reduce(_ +& _) val ll_largerThanLowThresholdProbaSum = ll_count.zipWithIndex.map{ case (count, idx) => Mux((count === ll_nbseq_1) || (count === 0.U) || (count <= ll_lowThreshold), 0.U, ll_proba(idx)) }.reduce(_ +& _) val ll_normalizedCounterMax = ll_normalizedCounter.reduceTree((a, b) => Mux(a > b, a, b)) val ll_normalizedCounterIdx = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounterIdx(i) := i.U } val ll_normalizedCounterMaxIdx = ll_normalizedCounter.zip(ll_normalizedCounterIdx).reduce{ (x, y) => (Mux(x._1 < y._1, y._1, x._1), Mux(x._1 < y._1, y._2, x._2)) }._2 val ll_nxtStillToDistribute = (ll_still_to_distribute - ll_largerThanLowThresholdProbaSum - ll_smallOrEqToLowThresholdCount).asSInt val ll_negNxtStillToDistribute = (-1).S * ll_nxtStillToDistribute val fse_normalize_corner_case = ll_negNxtStillToDistribute >= (ll_normalizedCounterMax >> 1.U).asSInt val fse_normalize_corner_case_reg = RegInit(false.B) when (dicBuilderState === sNormalizeCount && predefined_mode_q.io.enq.ready) { predefined_mode_q.io.enq.valid := true.B for (i <- 0 until maxSymbolLL + 1) { val ll_ncountSumStill2Dist = (ll_normalizedCounter(i).asSInt + ll_nxtStillToDistribute).asUInt ll_normalizedCounterMaxAdjusted(i) := Mux(i.U === ll_normalizedCounterMaxIdx, ll_ncountSumStill2Dist, ll_normalizedCounter(i)) } // Force predefined mode when we encounter normalization corner case fse_normalize_corner_case_reg := fse_normalize_corner_case predefined_mode_q.io.enq.bits := fse_normalize_corner_case when (fse_normalize_corner_case) { CompressAccelLogger.logInfo(printInfo + " DICBUILDER ForcePredefinedMode\n") } } // insert registers to avoid critical path issues val ll_normalizedCounterReg = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) when (dicBuilderState === sNormalizeCount) { for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_count(%d): %d\n", i.U, ll_count(i)) } CompressAccelLogger.logInfo(printInfo + " ll_lowProbCount: %d\n", ll_lowProbCount) CompressAccelLogger.logInfo(printInfo + " ll_scale: %d\n", ll_scale) CompressAccelLogger.logInfo(printInfo + " ll_scale_20: %d\n", ll_scale_20) CompressAccelLogger.logInfo(printInfo + " ll_step: %d\n", ll_step) CompressAccelLogger.logInfo(printInfo + " ll_vStep: %d\n", ll_vStep) CompressAccelLogger.logInfo(printInfo + " ll_still_to_distribute: %d\n", ll_still_to_distribute) CompressAccelLogger.logInfo(printInfo + " ll_lowThreshold: %d\n", ll_lowThreshold) for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_count_times_step(%d): %d\n", i.U, ll_count_times_step(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba_base(%d): %d\n", i.U, ll_proba_base(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba(%d): %d\n", i.U, ll_proba(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounter(%d): %d\n", i.U, ll_normalizedCounter(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterMaxAdjusted(%d): %d\n", i.U, ll_normalizedCounterMaxAdjusted(i)) } CompressAccelLogger.logInfo(printInfo + " ll_smallOrEqToLowThresholdCount: %d\n", ll_smallOrEqToLowThresholdCount) CompressAccelLogger.logInfo(printInfo + " ll_largerThanLowThresholdProbaSum: %d\n", ll_largerThanLowThresholdProbaSum) CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterMax: %d\n", ll_normalizedCounterMax) CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterMaxIdx: %d\n", ll_normalizedCounterMaxIdx) CompressAccelLogger.logInfo(printInfo + " ll_nxtStillToDistribute: %d\n", ll_nxtStillToDistribute) CompressAccelLogger.logInfo(printInfo + " ll_negNxtStillToDistribute: %d\n", ll_negNxtStillToDistribute) CompressAccelLogger.logInfo(printInfo + " (ll_normalizedCounterMax >> 1.U).asSInt: %d\n", (ll_normalizedCounterMax >> 1.U).asSInt) } /////////////////////////////////////////////////////////////////////////// // sBuildCTableSymbolStartPositions /////////////////////////////////////////////////////////////////////////// val LL_TABLESIZE = 1 << tableLogLL val ll_maxSV1 = ll_max_symbol_value + 1.U val ll_tableSize = LL_TABLESIZE.U val ll_tableMask = ll_tableSize - 1.U val ll_cumul = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) val ll_tableSymbol = RegInit(VecInit(Seq.fill(LL_TABLESIZE)(0.U(8.W)))) val ll_highThresholdBeforeCumul = WireInit(0.U(32.W)) ll_highThresholdBeforeCumul := ll_tableSize - 1.U val ll_normCountEqsNegOne = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(8.W)))) val ll_normCountEqsNegOneCumul = WireInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(8.W)))) val ll_normCountEqsNegOneSum = ll_normCountEqsNegOne.reduce(_ +& _) val ll_highThresholdAfterCumul = RegInit(0.U(32.W)) val ll_cumulReg = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(16.W)))) /////////////////////////////////////////////////////////////////////////// // sBuildCTableSpreadSymbols /////////////////////////////////////////////////////////////////////////// val LL_SPREAD_TABLE_SIZE = LL_TABLESIZE + 8 val ll_spread = RegInit(VecInit(Seq.fill(LL_SPREAD_TABLE_SIZE)(0.U(8.W)))) val add = BigInt("0101010101010101", 16) val ll_pos = RegInit(0.U(64.W)) val ll_s = RegInit(0.U(64.W)) val ll_sv = RegInit(0.U(64.W)) val ll_fse_tablestep = (ll_tableSize >> 1.U) + (ll_tableSize >> 3.U) + 3.U /////////////////////////////////////////////////////////////////////////// // sBuildCTableBuildTable / sBuildCTableSymbolTT /////////////////////////////////////////////////////////////////////////// val ll_tableU16 = RegInit(VecInit(Seq.fill(LL_TABLESIZE)(0.U(16.W)))) val ll_symbolTTDeltaNbBits = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.U(32.W)))) val ll_symbolTTDeltaFindState = RegInit(VecInit(Seq.fill(maxSymbolLL + 1)(0.S(32.W)))) val ll_total = RegInit(0.U(32.W)) val normCount = Wire(UInt(32.W)) normCount := ll_normalizedCounterReg(ll_s) /////////////////////////////////////////////////////////////////////////// // sLookup /////////////////////////////////////////////////////////////////////////// val symbolTT_lookup_fire_and_last_vec = WireInit(VecInit(Seq.fill(interleave_cnt)(false.B))) for (i <- 0 until interleave_cnt) { val cur_symbol = io.symbol_info(i).bits.symbol val last_symbol = io.symbol_info(i).bits.last_symbol val symbolTT_lookup_fire = DecoupledHelper( io.symbol_info(i).valid, io.symbolTT_info(i).ready, dicBuilderState === sLookup) io.symbol_info(i).ready := symbolTT_lookup_fire.fire(io.symbol_info(i).valid) io.symbolTT_info(i).valid := symbolTT_lookup_fire.fire(io.symbolTT_info(i).ready) io.symbolTT_info(i).bits.nbbit := ll_symbolTTDeltaNbBits(cur_symbol) io.symbolTT_info(i).bits.findstate := ll_symbolTTDeltaFindState(cur_symbol).asUInt io.symbolTT_info(i).bits.from_last_symbol := last_symbol io.new_state(i).valid := (dicBuilderState === sLookup) io.new_state(i).bits := ll_tableU16(io.state_table_idx(i)) symbolTT_lookup_fire_and_last_vec(i) := symbolTT_lookup_fire.fire && last_symbol } val dictionary_lookup_done = symbolTT_lookup_fire_and_last_vec.reduce(_ || _) // this is okay since we know for sure that in huffman, the fse compressor will // not be kicked-off unless there are enough symobls to compress val use_predefined_mode = (io.nb_seq.bits <= ZSTD_SEQUENCE_PREDEFINED_MODE_LIMIT.U) || fse_normalize_corner_case_reg val ll_table_log_fired = RegInit(false.B) io.ll_table_log.bits := Mux(use_predefined_mode, predefined_table_log.U, tableLogLL.U) io.ll_table_log.valid := !ll_table_log_fired && (dicBuilderState === sLookup) when (io.ll_table_log.fire) { ll_table_log_fired := true.B } val print_table = RegInit(true.B) val write_header_started = RegInit(false.B) val nbBits = RegInit(0.U(32.W)) val remaining = RegInit(0.U(32.W)) val threshold = RegInit(0.U(32.W)) val symbol = RegInit(0.U(32.W)) val alphabetSize = ll_max_symbol_value + 1.U val previousIs0 = RegInit(false.B) val bitStream = RegInit(0.U(64.W)) val bitCount = RegInit(0.U(7.W)) val writeBitStream = RegInit(false.B) // TODO : optimize to write & update bitStream at the same time val start = RegInit(0.U(32.W)) val start_initialized = RegInit(false.B) val skip_zeros_done = RegInit(false.B) val skip_24_done = RegInit(false.B) val skip_3_done = RegInit(false.B) val writeBitStreamPrev0 = RegInit(false.B) val FSE_MIN_TABLELOG = 5 io.header_writes.valid := false.B io.header_writes.bits.data := 0.U io.header_writes.bits.validbytes := 0.U io.header_writes.bits.end_of_message := false.B val shifted_thresholds = WireInit(VecInit(Seq.fill(tableLogLL+1)(0.U(32.W)))) shifted_thresholds(0) := threshold for (i <- 1 until tableLogLL + 1) { shifted_thresholds(i) := shifted_thresholds(i-1) >> 1.U } val shifted_threshold_small_or_eq_remaining = WireInit(VecInit(Seq.fill(tableLogLL+1)(0.U(32.W)))) val nxt_shifted_threshold_idx = shifted_threshold_small_or_eq_remaining.reduce(_ + _) io.lookup_done.ready := true.B when (io.lookup_done.valid) { for (i <- 0 until maxSymbolLL+1) { ll_count(i) := 0.U } ll_max_symbol_value := 0.U ll_nbseq_1 := 0.U for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounterReg(i) := 0.U } for (i <- 0 until LL_TABLESIZE) { ll_tableSymbol(i) := 0.U } ll_highThresholdAfterCumul := 0.U for (i <- 0 until maxSymbolLL + 1) { ll_cumulReg(i) := 0.U } for (i <- 0 until LL_SPREAD_TABLE_SIZE) { ll_spread(i) := 0.U } ll_pos := 0.U ll_s := 0.U ll_sv := 0.U for (i <- 0 until LL_TABLESIZE) { ll_tableU16(i) := 0.U } for (i <- 0 until maxSymbolLL+ 1) { ll_symbolTTDeltaNbBits(i) := 0.U ll_symbolTTDeltaFindState(i) := 0.S } ll_total := 0.U ll_table_log_fired := false.B fse_normalize_corner_case_reg := false.B print_table := true.B write_header_started := false.B nbBits := 0.U remaining := 0.U threshold := 0.U symbol := 0.U previousIs0 := false.B bitStream := 0.U bitCount := 0.U writeBitStream := false.B start := 0.U start_initialized := false.B skip_zeros_done := false.B skip_24_done := false.B skip_3_done := false.B writeBitStreamPrev0 := false.B } switch (dicBuilderState) { is (sIdle) { when (io.ll_stream.output_valid && io.nb_seq.valid) { dicBuilderState := sCount } } is (sCount) { io.ll_stream.output_ready := predefined_mode_q.io.enq.ready io.ll_stream.user_consumed_bytes := Mux(io.ll_stream.available_output_bytes < COLLECT_STAT_PROCESS_BYTES.U, io.ll_stream.available_output_bytes, COLLECT_STAT_PROCESS_BYTES.U) when (io.ll_stream.output_valid) { for (i <- 0 until maxSymbolLL + 1) { ll_count(i) := ll_count(i) + stat_sum(i) } ll_max_symbol_value := Mux(ll_max_symbol_value > cur_max_value, ll_max_symbol_value, cur_max_value) } when (predefined_mode_q.io.enq.ready && io.ll_stream.output_valid && io.ll_stream.output_last_chunk && (io.ll_stream.user_consumed_bytes === io.ll_stream.available_output_bytes)) { // zstd_compress_sequences.c 271 // if (count[codeTable[nbSeq-1]] > 1) { // count[codeTable[nbSeq-1]]--; // nbSeq_1--; // } if (as_zstd_submodule) { val ll_last_codetable = input_ll_symbols(io.ll_stream.user_consumed_bytes - 1.U) val ll_count_last_codetable = ll_count(ll_last_codetable) val ll_last_statcount = stat_sum(ll_last_codetable) val ll_last_count = ll_count_last_codetable + ll_last_statcount val do_subtract = ll_last_count > 1.U ll_nbseq_1 := Mux(do_subtract, io.nb_seq.bits - 1.U, io.nb_seq.bits) ll_count(ll_last_codetable) := Mux(do_subtract, ll_last_count - 1.U, ll_last_count) } else { ll_nbseq_1 := io.nb_seq.bits } when (!use_predefined_mode) { dicBuilderState := sNormalizeCount } .otherwise { // TODO : set io.ll_stream.output_ready to true & move on to sLookup without going through sCount dicBuilderState := sLookup predefined_mode_q.io.enq.valid := true.B predefined_mode_q.io.enq.bits := true.B if (printInfo == "LL") { for (i <- 0 until 36) { ll_symbolTTDeltaNbBits(i) := LL_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := LL_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := LL_DefaultTableU16(i).U } } else if (printInfo == "ML") { for (i <- 0 until 53) { ll_symbolTTDeltaNbBits(i) := ML_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := ML_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := ML_DefaultTableU16(i).U } } else if (printInfo == "OF") { for (i <- 0 until 29) { ll_symbolTTDeltaNbBits(i) := OF_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := OF_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 32) { ll_tableU16(i) := OF_DefaultTableU16(i).U } } } } } is (sNormalizeCount) { CompressAccelLogger.logInfo(printInfo + "ll_nbseq_1: %d\n", ll_nbseq_1) for (i <- 0 until maxSymbolLL + 1) { ll_normalizedCounterReg(i) := ll_normalizedCounterMaxAdjusted(i) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba_base(%d): %d\n", i.U, ll_proba_base(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba(%d): %d\n", i.U, ll_proba(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_proba(%d): %d\n", i.U, ll_proba(i)) } for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounter(%d): %d\n", i.U, ll_normalizedCounter(i)) } CompressAccelLogger.logInfo(printInfo + " ll_lowThreshold: %d\n", ll_lowThreshold) CompressAccelLogger.logInfo(printInfo + " ll_lowProbCount: %d\n", ll_lowProbCount) // Takes only one cycle when (predefined_mode_q.io.enq.ready) { when (fse_normalize_corner_case) { dicBuilderState := sLookup if (printInfo == "LL") { for (i <- 0 until 36) { ll_symbolTTDeltaNbBits(i) := LL_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := LL_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := LL_DefaultTableU16(i).U } } else if (printInfo == "ML") { for (i <- 0 until 53) { ll_symbolTTDeltaNbBits(i) := ML_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := ML_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 64) { ll_tableU16(i) := ML_DefaultTableU16(i).U } } else if (printInfo == "OF") { for (i <- 0 until 29) { ll_symbolTTDeltaNbBits(i) := OF_symbolTTDeltaNbBitsDefaultValues(i).U ll_symbolTTDeltaFindState(i) := OF_symbolTTDeltaFindStateDefaultValues(i).S } for (i <- 0 until 32) { ll_tableU16(i) := OF_DefaultTableU16(i).U } } } .otherwise { dicBuilderState := sBuildCTableSymbolStartPositions } } } is (sBuildCTableSymbolStartPositions) { ll_normCountEqsNegOneCumul(0) := ll_normCountEqsNegOne(0) for (i <- 1 until maxSymbolLL + 1) { when (ll_normalizedCounterReg(i-1) === neg_one_uint16.U) { ll_normCountEqsNegOne(i-1) := 1.U ll_cumul(i) := ll_cumul(i-1) + 1.U ll_tableSymbol(ll_highThresholdBeforeCumul - ll_normCountEqsNegOneCumul(i-1) + 1.U) := (i-1).U } .otherwise { ll_cumul(i) := ll_cumul(i-1) + ll_normalizedCounterReg(i-1) } ll_normCountEqsNegOneCumul(i) := ll_normCountEqsNegOneCumul(i-1) + ll_normCountEqsNegOne(i) } ll_cumul(ll_maxSV1) := ll_tableSize + 1.U ll_highThresholdAfterCumul := ll_highThresholdBeforeCumul - ll_normCountEqsNegOneSum for (i <- 0 until maxSymbolLL + 1) { ll_cumulReg(i) := ll_cumul(i) } // Takes only one cycle dicBuilderState := sBuildCTableSpreadSymbols } is (sBuildCTableSpreadSymbols) { when (ll_highThresholdAfterCumul === ll_tableSize - 1.U) { ll_s := ll_s + 1.U ll_sv := ll_sv + add.U val n = ll_normalizedCounterReg(ll_s) val write_spread_cnt = n >> 3.U val write_extra = (n & 7.U) =/= 0.U val write_spread_cnt_wrapped = write_spread_cnt +& write_extra.asUInt val write_spread_bytes = write_spread_cnt_wrapped << 3.U ll_pos := ll_pos + n // pos + n for (i <- 0 until LL_SPREAD_TABLE_SIZE) { when ((i.U >= ll_pos) && (i.U < ll_pos + write_spread_bytes)) { val shift_bytes = (i.U - ll_pos)(2, 0) val shift_bits = shift_bytes << 3.U ll_spread(i) := ll_sv >> shift_bits } } when (ll_s === ll_maxSV1) { for (i <- 0 until LL_TABLESIZE) { val uPosition = (i.U * ll_fse_tablestep) & ll_tableMask when ((i.U >= ll_pos) && (i.U < ll_pos + write_spread_bytes)) { val shift_bytes = (i.U - ll_pos)(2, 0) val shift_bits = shift_bytes << 3.U ll_tableSymbol(uPosition) := ll_sv >> shift_bits } .otherwise { ll_tableSymbol(uPosition) := ll_spread(i) } } dicBuilderState := sBuildCTableBuildTable ll_s := 0.U } } .otherwise { CompressAccelLogger.logInfo(printInfo + " Doesn't support low probability cases") assert(false.B, "Doesn't support low probability cases") } } is (sBuildCTableBuildTable) { // 2^tableLogLL cycles ll_s := ll_s + 1.U val s = ll_tableSymbol(ll_s) ll_cumulReg(s) := ll_cumulReg(s) + 1.U ll_tableU16(ll_cumulReg(s)) := ll_tableSize + ll_s when (ll_s === ll_tableSize - 1.U) { ll_s := 0.U dicBuilderState := sBuildCTableSymbolTT } } is (sBuildCTableSymbolTT) { ll_s := ll_s + 1.U when (normCount === 0.U) { ll_symbolTTDeltaNbBits(ll_s) := (((tableLogLL + 1) << 16) - (1 << tableLogLL)).U ll_symbolTTDeltaFindState(ll_s) := 0.S } .elsewhen (normCount === 1.U) { // ignore low-prob (normCount === -1.S) for now ll_symbolTTDeltaNbBits(ll_s) := (((tableLogLL) << 16) - (1 << tableLogLL)).U ll_symbolTTDeltaFindState(ll_s) := (ll_total - 1.U).asSInt ll_total := ll_total + 1.U } .otherwise { val maxBitsOut = tableLogLL.U - BIT_highbit32(normCount - 1.U) val minStatePlus = normCount << maxBitsOut(3, 0) ll_symbolTTDeltaNbBits(ll_s) := (maxBitsOut << 16.U) - minStatePlus ll_symbolTTDeltaFindState(ll_s) := (ll_total - normCount).asSInt ll_total := ll_total + normCount } when (ll_s === ll_max_symbol_value) { ll_s := 0.U dicBuilderState := sWriteCTable } } is (sWriteCTable) { when (!write_header_started) { write_header_started := true.B remaining := ll_tableSize + 1.U threshold := ll_tableSize nbBits := (tableLogLL + 1).U bitStream := (tableLogLL - FSE_MIN_TABLELOG).U bitCount := 4.U } .otherwise { when ((symbol < alphabetSize) && (remaining > 1.U)) { when(writeBitStream) { when (io.header_writes.ready) { writeBitStream := false.B bitStream := bitStream >> 16.U bitCount := bitCount - 16.U CompressAccelLogger.logInfo(printInfo + " bitStream(7, 0): %d\n", bitStream(7, 0)) CompressAccelLogger.logInfo(printInfo + " bitStream(15, 8): %d\n", bitStream(15, 8)) } io.header_writes.valid := true.B io.header_writes.bits.data := bitStream io.header_writes.bits.validbytes := 2.U } .elsewhen (writeBitStreamPrev0) { when (io.header_writes.ready) { writeBitStreamPrev0 := false.B bitStream := bitStream >> 16.U CompressAccelLogger.logInfo(printInfo + "writeBitStreamPrev0") } io.header_writes.valid := true.B io.header_writes.bits.data := bitStream io.header_writes.bits.validbytes := 2.U } .elsewhen (previousIs0) { when (!start_initialized) { start := symbol start_initialized := true.B CompressAccelLogger.logInfo(printInfo + " start: %d\n", symbol) } .elsewhen (!skip_zeros_done) { val cur_norm_count = ll_normalizedCounterReg(symbol) when (cur_norm_count =/= 0.U) { skip_zeros_done := true.B CompressAccelLogger.logInfo(printInfo + " symbol: %d\n", symbol) } .otherwise { symbol := symbol + 1.U when ((symbol + 1.U) === alphabetSize) { assert(false.B, printInfo + " Wrong distribution for FSE compression\n"); } } } .elsewhen (!skip_24_done) { when (symbol >= start + 24.U) { start := start + 24.U bitStream := bitStream + (BigInt("FFFF", 16).U << bitCount) writeBitStreamPrev0 := true.B } .otherwise { skip_24_done := true.B CompressAccelLogger.logInfo(printInfo + " skip_24_done\n") } CompressAccelLogger.logInfo(printInfo + " skip_24\n") } .elsewhen (!skip_3_done) { when (symbol >= start + 3.U) { start := start + 3.U bitStream := bitStream + (3.U << bitCount) bitCount := bitCount + 2.U } .otherwise { skip_3_done := true.B CompressAccelLogger.logInfo(printInfo + " skip_3_done\n") } CompressAccelLogger.logInfo(printInfo + " skip_3\n") } .otherwise { bitStream := bitStream + ((symbol - start) << bitCount) bitCount := bitCount + 2.U previousIs0 := false.B start := 0.U start_initialized := false.B skip_zeros_done := false.B skip_24_done := false.B skip_3_done := false.B when (bitCount > 16.U) { writeBitStream := true.B } CompressAccelLogger.logInfo(printInfo + " previousIs0_done\n") } } .otherwise { val count = ll_normalizedCounterReg(symbol) symbol := symbol + 1.U val max = ((threshold << 1.U) - 1.U) - remaining // fse_compress.c 327 ????? // remaining := remaining - Mux(count < 0.S, (-1.S)*count, count) val nxt_remaining = remaining - count remaining := nxt_remaining val count1 = count + 1.U val count1_max = Mux(count1 >= threshold, count1 + max, count1) val nxt_bitCount = bitCount + nbBits - Mux(count1_max < max, 1.U, 0.U) bitStream := bitStream + (count1_max << bitCount) bitCount := nxt_bitCount writeBitStream := nxt_bitCount > 16.U previousIs0 := (count1_max === 1.U) assert(remaining >= 1.U, "Not enough remaining for FSE header writes\n") CompressAccelLogger.logInfo(printInfo + " previousIs0: %d\n", (count1_max === 1.U)) CompressAccelLogger.logInfo(printInfo + " alphabetSize: %d\n", alphabetSize) CompressAccelLogger.logInfo(printInfo + " symbol: %d\n", symbol) CompressAccelLogger.logInfo(printInfo + " threshold: %d\n", threshold) CompressAccelLogger.logInfo(printInfo + " max: %d\n", max) CompressAccelLogger.logInfo(printInfo + " remaining: %d\n", remaining) CompressAccelLogger.logInfo(printInfo + " nxt_remaining: %d\n", nxt_remaining) CompressAccelLogger.logInfo(printInfo + " count: %d\n", count) CompressAccelLogger.logInfo(printInfo + " count1_max: %d\n", count1_max) CompressAccelLogger.logInfo(printInfo + " nxt_bitCount: %d\n", nxt_bitCount) CompressAccelLogger.logInfo(printInfo + " writeBitStream: %d\n", writeBitStream) CompressAccelLogger.logInfo(printInfo + " BitStream: 0x%x\n", (bitStream + (count1_max << bitCount))) for (i <- 0 until tableLogLL + 1) { shifted_threshold_small_or_eq_remaining(i) := Mux(nxt_remaining < shifted_thresholds(i), 1.U, 0.U) } threshold := shifted_thresholds(nxt_shifted_threshold_idx) nbBits := nbBits - nxt_shifted_threshold_idx } } .otherwise { io.header_writes.valid := true.B io.header_writes.bits.data := bitStream io.header_writes.bits.validbytes := ((bitCount + 7.U) >> 3.U) if (mark_end_of_header) { io.header_writes.bits.end_of_message := true.B } when (io.header_writes.ready) { dicBuilderState := sLookup bitStream := 0.U bitCount := 0.U } } } } is (sLookup) { when (print_table) { print_table := false.B // for (i <- 0 until maxSymbolLL + 1) { // CompressAccelLogger.logInfo(printInfo + " ll_count(%d): %d\n", i.U, ll_count(i)) // } CompressAccelLogger.logInfo(printInfo + " ll_max_symbol_value: %d\n", ll_max_symbol_value) for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " ll_normalizedCounterReg(%d): %d\n", i.U, ll_normalizedCounterReg(i)) } for (i <- 0 until LL_TABLESIZE) { CompressAccelLogger.logInfo(printInfo + " ll_tableSymbol(%d): %d\n", i.U, ll_tableSymbol(i)) } CompressAccelLogger.logInfo(printInfo + " ll_highThresholdAfterCumul: %d\n", ll_highThresholdAfterCumul) for (i <- 0 until LL_SPREAD_TABLE_SIZE) { CompressAccelLogger.logInfo(printInfo + " ll_spread(%d): %d\n", i.U, ll_spread(i)) } CompressAccelLogger.logInfo(printInfo + " ll_fse_tablestep: %d\n", ll_fse_tablestep) for (i <- 0 until maxSymbolLL + 1) { CompressAccelLogger.logInfo(printInfo + " symbolTTDeltaNbBits(%d): %d, ll_symbolTTDeltaFindState(%d): %d\n", i.U, ll_symbolTTDeltaNbBits(i), i.U, ll_symbolTTDeltaFindState(i).asSInt) } for (i <- 0 until (1 << tableLogLL)) { CompressAccelLogger.logInfo(printInfo + " ll_tableU16(%d): %d\n", i.U, ll_tableU16(i)) } } when (io.lookup_done.valid) { io.nb_seq.ready := true.B dicBuilderState := sIdle } } } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } def logCritical(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_*)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } } def logWaveStyle(format: String, args: Bits*)(implicit p: Parameters) { } } object CompressAccelParams { }
module FSECompressorDicBuilder( // @[FSECompressorDicBuilder.scala:39:7] input clock, // @[FSECompressorDicBuilder.scala:39:7] input reset, // @[FSECompressorDicBuilder.scala:39:7] output io_nb_seq_ready, // @[FSECompressorDicBuilder.scala:48:14] input io_nb_seq_valid, // @[FSECompressorDicBuilder.scala:48:14] input [63:0] io_nb_seq_bits, // @[FSECompressorDicBuilder.scala:48:14] output [5:0] io_ll_stream_user_consumed_bytes, // @[FSECompressorDicBuilder.scala:48:14] input [5:0] io_ll_stream_available_output_bytes, // @[FSECompressorDicBuilder.scala:48:14] input io_ll_stream_output_valid, // @[FSECompressorDicBuilder.scala:48:14] output io_ll_stream_output_ready, // @[FSECompressorDicBuilder.scala:48:14] input [255:0] io_ll_stream_output_data, // @[FSECompressorDicBuilder.scala:48:14] input io_ll_stream_output_last_chunk, // @[FSECompressorDicBuilder.scala:48:14] input io_ll_table_log_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_ll_table_log_valid, // @[FSECompressorDicBuilder.scala:48:14] output io_symbol_info_0_ready, // @[FSECompressorDicBuilder.scala:48:14] input io_symbol_info_0_valid, // @[FSECompressorDicBuilder.scala:48:14] input [7:0] io_symbol_info_0_bits_symbol, // @[FSECompressorDicBuilder.scala:48:14] input io_symbol_info_0_bits_last_symbol, // @[FSECompressorDicBuilder.scala:48:14] output io_symbol_info_1_ready, // @[FSECompressorDicBuilder.scala:48:14] input io_symbol_info_1_valid, // @[FSECompressorDicBuilder.scala:48:14] input [7:0] io_symbol_info_1_bits_symbol, // @[FSECompressorDicBuilder.scala:48:14] input io_symbol_info_1_bits_last_symbol, // @[FSECompressorDicBuilder.scala:48:14] input io_symbolTT_info_0_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_symbolTT_info_0_valid, // @[FSECompressorDicBuilder.scala:48:14] output [31:0] io_symbolTT_info_0_bits_nbbit, // @[FSECompressorDicBuilder.scala:48:14] output [31:0] io_symbolTT_info_0_bits_findstate, // @[FSECompressorDicBuilder.scala:48:14] output io_symbolTT_info_0_bits_from_last_symbol, // @[FSECompressorDicBuilder.scala:48:14] input io_symbolTT_info_1_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_symbolTT_info_1_valid, // @[FSECompressorDicBuilder.scala:48:14] output [31:0] io_symbolTT_info_1_bits_nbbit, // @[FSECompressorDicBuilder.scala:48:14] output [31:0] io_symbolTT_info_1_bits_findstate, // @[FSECompressorDicBuilder.scala:48:14] output io_symbolTT_info_1_bits_from_last_symbol, // @[FSECompressorDicBuilder.scala:48:14] input [15:0] io_state_table_idx_0, // @[FSECompressorDicBuilder.scala:48:14] input [15:0] io_state_table_idx_1, // @[FSECompressorDicBuilder.scala:48:14] output io_new_state_0_valid, // @[FSECompressorDicBuilder.scala:48:14] output [15:0] io_new_state_0_bits, // @[FSECompressorDicBuilder.scala:48:14] output io_new_state_1_valid, // @[FSECompressorDicBuilder.scala:48:14] output [15:0] io_new_state_1_bits, // @[FSECompressorDicBuilder.scala:48:14] input io_header_writes_ready, // @[FSECompressorDicBuilder.scala:48:14] output io_header_writes_valid, // @[FSECompressorDicBuilder.scala:48:14] output [255:0] io_header_writes_bits_data, // @[FSECompressorDicBuilder.scala:48:14] output [5:0] io_header_writes_bits_validbytes, // @[FSECompressorDicBuilder.scala:48:14] input io_lookup_done_valid // @[FSECompressorDicBuilder.scala:48:14] ); wire [15:0] ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_2; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] ll_normalizedCounter_0; // @[FSECompressorDicBuilder.scala:277:38] wire _predefined_mode_q_io_enq_ready; // @[FSECompressorDicBuilder.scala:141:33] wire io_nb_seq_valid_0 = io_nb_seq_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [63:0] io_nb_seq_bits_0 = io_nb_seq_bits; // @[FSECompressorDicBuilder.scala:39:7] wire [5:0] io_ll_stream_available_output_bytes_0 = io_ll_stream_available_output_bytes; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_stream_output_valid_0 = io_ll_stream_output_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [255:0] io_ll_stream_output_data_0 = io_ll_stream_output_data; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_stream_output_last_chunk_0 = io_ll_stream_output_last_chunk; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_table_log_ready_0 = io_ll_table_log_ready; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_0_valid_0 = io_symbol_info_0_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [7:0] io_symbol_info_0_bits_symbol_0 = io_symbol_info_0_bits_symbol; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_0_bits_last_symbol_0 = io_symbol_info_0_bits_last_symbol; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_1_valid_0 = io_symbol_info_1_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [7:0] io_symbol_info_1_bits_symbol_0 = io_symbol_info_1_bits_symbol; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_1_bits_last_symbol_0 = io_symbol_info_1_bits_last_symbol; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbolTT_info_0_ready_0 = io_symbolTT_info_0_ready; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbolTT_info_1_ready_0 = io_symbolTT_info_1_ready; // @[FSECompressorDicBuilder.scala:39:7] wire [15:0] io_state_table_idx_0_0 = io_state_table_idx_0; // @[FSECompressorDicBuilder.scala:39:7] wire [15:0] io_state_table_idx_1_0 = io_state_table_idx_1; // @[FSECompressorDicBuilder.scala:39:7] wire io_header_writes_ready_0 = io_header_writes_ready; // @[FSECompressorDicBuilder.scala:39:7] wire io_lookup_done_valid_0 = io_lookup_done_valid; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] _rtbTable_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _rtbTable_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:57:33] wire [31:0] _ll_count_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_8 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_9 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_10 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_11 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_count_WIRE_12 = 32'h0; // @[FSECompressorDicBuilder.scala:169:33] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_8 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_9 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_10 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_11 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaNbBits_WIRE_12 = 32'h0; // @[FSECompressorDicBuilder.scala:412:47] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_7 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_8 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_9 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_10 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_11 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _ll_symbolTTDeltaFindState_WIRE_12 = 32'h0; // @[FSECompressorDicBuilder.scala:413:50] wire [31:0] _shifted_thresholds_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_thresholds_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:484:44] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_0 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_1 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_2 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_3 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_4 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_5 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [31:0] _shifted_threshold_small_or_eq_remaining_WIRE_6 = 32'h0; // @[FSECompressorDicBuilder.scala:490:65] wire [3:0] io_ll_table_log_bits = 4'h6; // @[FSECompressorDicBuilder.scala:39:7] wire io_header_writes_bits_end_of_message = 1'h0; // @[FSECompressorDicBuilder.scala:39:7] wire _table_WIRE_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_1_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_2_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_3_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_4_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_5_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_6_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_7_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_8_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_9_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_10_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_11_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_0 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_1 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_2 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _table_WIRE_12_3 = 1'h0; // @[FSECompressorDicBuilder.scala:179:58] wire _has_value_WIRE_0 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_1 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_2 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_3 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_4 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_5 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_6 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_7 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_8 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_9 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_10 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_11 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _has_value_WIRE_12 = 1'h0; // @[FSECompressorDicBuilder.scala:191:35] wire _symbolTT_lookup_fire_and_last_vec_WIRE_0 = 1'h0; // @[FSECompressorDicBuilder.scala:422:59] wire _symbolTT_lookup_fire_and_last_vec_WIRE_1 = 1'h0; // @[FSECompressorDicBuilder.scala:422:59] wire io_predefined_mode_ready = 1'h1; // @[FSECompressorDicBuilder.scala:39:7] wire io_lookup_done_ready = 1'h1; // @[FSECompressorDicBuilder.scala:39:7] wire io_lookup_done_bits = 1'h1; // @[FSECompressorDicBuilder.scala:39:7] wire [6:0] _ll_cumul_T_1 = 7'h41; // @[FSECompressorDicBuilder.scala:703:43] wire [6:0] _remaining_T_1 = 7'h41; // @[FSECompressorDicBuilder.scala:793:35] wire [31:0] _maxBitsOut_highBit_T_46 = 32'hAAAAAAAA; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_41 = 32'h55555555; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_40 = 32'h66666666; // @[FSECompressorDicBuilder.scala:52:49] wire [30:0] _maxBitsOut_highBit_T_39 = 31'h33333333; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_36 = 32'hCCCCCCCC; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_31 = 32'h33333333; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_30 = 32'h3C3C3C3C; // @[FSECompressorDicBuilder.scala:52:49] wire [29:0] _maxBitsOut_highBit_T_29 = 30'hF0F0F0F; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_26 = 32'hF0F0F0F0; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_21 = 32'hF0F0F0F; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_20 = 32'hFF00FF0; // @[FSECompressorDicBuilder.scala:52:49] wire [27:0] _maxBitsOut_highBit_T_19 = 28'hFF00FF; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_16 = 32'hFF00FF00; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_11 = 32'hFF00FF; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_10 = 32'hFFFF00; // @[FSECompressorDicBuilder.scala:52:49] wire [23:0] _maxBitsOut_highBit_T_9 = 24'hFFFF; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T = 32'hFFFF0000; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_6 = 32'hFFFF0000; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_1 = 32'hFFFF; // @[FSECompressorDicBuilder.scala:52:49] wire [12:0] uPosition_63 = 13'h15; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_63 = 13'hA95; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_62 = 13'h2A; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_62 = 13'hA6A; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_61 = 13'h3F; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_61 = 13'hA3F; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_60 = 13'h14; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_60 = 13'hA14; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_59 = 13'h29; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_59 = 13'h9E9; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_58 = 13'h3E; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_58 = 13'h9BE; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_57 = 13'h13; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_57 = 13'h993; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_56 = 13'h28; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_56 = 13'h968; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_55 = 13'h3D; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_55 = 13'h93D; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_54 = 13'h12; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_54 = 13'h912; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_53 = 13'h27; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_53 = 13'h8E7; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_52 = 13'h3C; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_52 = 13'h8BC; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_51 = 13'h11; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_51 = 13'h891; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_50 = 13'h26; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_50 = 13'h866; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_49 = 13'h3B; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_49 = 13'h83B; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_48 = 13'h10; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_48 = 13'h810; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_47 = 13'h25; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_47 = 13'h7E5; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_46 = 13'h3A; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_46 = 13'h7BA; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_45 = 13'hF; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_45 = 13'h78F; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_44 = 13'h24; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_44 = 13'h764; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_43 = 13'h39; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_43 = 13'h739; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_42 = 13'hE; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_42 = 13'h70E; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_41 = 13'h23; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_41 = 13'h6E3; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_40 = 13'h38; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_40 = 13'h6B8; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_39 = 13'hD; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_39 = 13'h68D; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_38 = 13'h22; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_38 = 13'h662; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_37 = 13'h37; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_37 = 13'h637; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_36 = 13'hC; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_36 = 13'h60C; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_35 = 13'h21; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_35 = 13'h5E1; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_34 = 13'h36; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_34 = 13'h5B6; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_33 = 13'hB; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_33 = 13'h58B; // @[FSECompressorDicBuilder.scala:736:34] wire [12:0] uPosition_32 = 13'h20; // @[FSECompressorDicBuilder.scala:736:54] wire [12:0] _uPosition_T_32 = 13'h560; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_31 = 12'h35; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_31 = 12'h535; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_30 = 12'hA; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_30 = 12'h50A; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_29 = 12'h1F; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_29 = 12'h4DF; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_28 = 12'h34; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_28 = 12'h4B4; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_27 = 12'h9; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_27 = 12'h489; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_26 = 12'h1E; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_26 = 12'h45E; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_25 = 12'h33; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_25 = 12'h433; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_24 = 12'h8; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_24 = 12'h408; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_23 = 12'h1D; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_23 = 12'h3DD; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_22 = 12'h32; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_22 = 12'h3B2; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_21 = 12'h7; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_21 = 12'h387; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_20 = 12'h1C; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_20 = 12'h35C; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_19 = 12'h31; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_19 = 12'h331; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_18 = 12'h6; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_18 = 12'h306; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_17 = 12'h1B; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_17 = 12'h2DB; // @[FSECompressorDicBuilder.scala:736:34] wire [11:0] uPosition_16 = 12'h30; // @[FSECompressorDicBuilder.scala:736:54] wire [11:0] _uPosition_T_16 = 12'h2B0; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_15 = 11'h5; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_15 = 11'h285; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_14 = 11'h1A; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_14 = 11'h25A; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_13 = 11'h2F; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_13 = 11'h22F; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_12 = 11'h4; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_12 = 11'h204; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_11 = 11'h19; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_11 = 11'h1D9; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_10 = 11'h2E; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_10 = 11'h1AE; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_9 = 11'h3; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_9 = 11'h183; // @[FSECompressorDicBuilder.scala:736:34] wire [10:0] uPosition_8 = 11'h18; // @[FSECompressorDicBuilder.scala:736:54] wire [10:0] _uPosition_T_8 = 11'h158; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_7 = 10'h2D; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_7 = 10'h12D; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_6 = 10'h2; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_6 = 10'h102; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_5 = 10'h17; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_5 = 10'hD7; // @[FSECompressorDicBuilder.scala:736:34] wire [9:0] uPosition_4 = 10'h2C; // @[FSECompressorDicBuilder.scala:736:54] wire [9:0] _uPosition_T_4 = 10'hAC; // @[FSECompressorDicBuilder.scala:736:34] wire [8:0] uPosition_3 = 9'h1; // @[FSECompressorDicBuilder.scala:736:54] wire [8:0] _uPosition_T_3 = 9'h81; // @[FSECompressorDicBuilder.scala:736:34] wire [8:0] uPosition_2 = 9'h16; // @[FSECompressorDicBuilder.scala:736:54] wire [8:0] _uPosition_T_2 = 9'h56; // @[FSECompressorDicBuilder.scala:736:34] wire [7:0] _ll_fse_tablestep_T_4 = 8'h2B; // @[FSECompressorDicBuilder.scala:405:72] wire [7:0] _uPosition_T_1 = 8'h2B; // @[FSECompressorDicBuilder.scala:736:34] wire [7:0] uPosition_1 = 8'h2B; // @[FSECompressorDicBuilder.scala:736:54] wire [7:0] _input_ll_symbols_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _input_ll_symbols_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _input_ll_symbols_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _input_ll_symbols_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:172:42] wire [7:0] _ll_tableSymbol_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_32 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_33 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_34 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_35 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_36 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_37 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_38 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_39 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_40 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_41 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_42 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_43 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_44 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_45 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_46 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_47 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_48 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_49 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_50 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_51 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_52 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_53 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_54 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_55 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_56 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_57 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_58 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_59 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_60 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_61 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_62 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_tableSymbol_WIRE_63 = 8'h0; // @[FSECompressorDicBuilder.scala:383:39] wire [7:0] _ll_normCountEqsNegOne_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] _ll_normCountEqsNegOne_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:388:47] wire [7:0] ll_normCountEqsNegOne_12 = 8'h0; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_normCountEqsNegOneCumul_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:389:52] wire [7:0] _ll_spread_WIRE_0 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_1 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_2 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_3 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_4 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_5 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_6 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_7 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_8 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_9 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_10 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_11 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_12 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_13 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_14 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_15 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_16 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_17 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_18 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_19 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_20 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_21 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_22 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_23 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_24 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_25 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_26 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_27 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_28 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_29 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_30 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_31 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_32 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_33 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_34 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_35 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_36 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_37 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_38 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_39 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_40 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_41 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_42 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_43 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_44 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_45 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_46 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_47 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_48 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_49 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_50 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_51 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_52 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_53 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_54 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_55 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_56 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_57 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_58 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_59 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_60 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_61 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_62 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_63 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_64 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_65 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_66 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_67 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_68 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_69 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_70 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _ll_spread_WIRE_71 = 8'h0; // @[FSECompressorDicBuilder.scala:400:34] wire [7:0] _uPosition_T = 8'h0; // @[FSECompressorDicBuilder.scala:736:34] wire [7:0] uPosition = 8'h0; // @[FSECompressorDicBuilder.scala:736:54] wire [15:0] _ll_proba_base_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_base_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:264:39] wire [15:0] _ll_proba_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_proba_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:265:34] wire [15:0] _ll_normalizedCounter_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounter_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:277:46] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterMaxAdjusted_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:278:57] wire [15:0] _ll_normalizedCounterIdx_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] _ll_normalizedCounterIdx_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:301:49] wire [15:0] ll_normalizedCounterIdx_0 = 16'h0; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] _ll_normalizedCounterReg_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_normalizedCounterReg_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:337:48] wire [15:0] _ll_cumul_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumul_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:382:34] wire [15:0] _ll_cumulReg_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_cumulReg_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:394:36] wire [15:0] _ll_tableU16_WIRE_0 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_1 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_2 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_3 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_4 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_5 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_6 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_7 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_8 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_9 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_10 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_11 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_12 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_13 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_14 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_15 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_16 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_17 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_18 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_19 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_20 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_21 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_22 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_23 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_24 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_25 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_26 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_27 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_28 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_29 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_30 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_31 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_32 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_33 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_34 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_35 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_36 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_37 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_38 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_39 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_40 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_41 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_42 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_43 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_44 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_45 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_46 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_47 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_48 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_49 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_50 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_51 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_52 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_53 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_54 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_55 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_56 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_57 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_58 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_59 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_60 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_61 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_62 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [15:0] _ll_tableU16_WIRE_63 = 16'h0; // @[FSECompressorDicBuilder.scala:411:36] wire [6:0] ll_fse_tablestep = 7'h2B; // @[FSECompressorDicBuilder.scala:405:72] wire [6:0] _ll_fse_tablestep_T_3 = 7'h28; // @[FSECompressorDicBuilder.scala:405:48] wire [7:0] _ll_fse_tablestep_T_2 = 8'h28; // @[FSECompressorDicBuilder.scala:405:48] wire [31:0] ll_highThresholdBeforeCumul = 32'h3F; // @[FSECompressorDicBuilder.scala:385:45] wire [6:0] ll_tableMask = 7'h3F; // @[FSECompressorDicBuilder.scala:381:35] wire [6:0] _ll_highThresholdBeforeCumul_T_1 = 7'h3F; // @[FSECompressorDicBuilder.scala:386:47] wire [15:0] ll_normalizedCounterIdx_12 = 16'hC; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_11 = 16'hB; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_10 = 16'hA; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_9 = 16'h9; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_8 = 16'h8; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_7 = 16'h7; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_6 = 16'h6; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_5 = 16'h5; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_4 = 16'h4; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_3 = 16'h3; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_2 = 16'h2; // @[FSECompressorDicBuilder.scala:301:41] wire [15:0] ll_normalizedCounterIdx_1 = 16'h1; // @[FSECompressorDicBuilder.scala:301:41] wire [63:0] ll_vStep = 64'h1000000000; // @[FSECompressorDicBuilder.scala:257:22] wire [127:0] _ll_vStep_T = 128'h1000000000; // @[FSECompressorDicBuilder.scala:258:19] wire [6:0] ll_scale_20 = 7'h24; // @[FSECompressorDicBuilder.scala:255:25] wire [6:0] _ll_scale_20_T_1 = 7'h24; // @[FSECompressorDicBuilder.scala:256:27] wire [7:0] _ll_scale_20_T = 8'h24; // @[FSECompressorDicBuilder.scala:256:27] wire [6:0] ll_scale = 7'h38; // @[FSECompressorDicBuilder.scala:251:22] wire [6:0] _ll_scale_T = 7'h38; // @[FSECompressorDicBuilder.scala:252:20] wire [5:0] _ll_scale_T_1 = 6'h38; // @[FSECompressorDicBuilder.scala:252:20] wire [7:0] _ll_cumul_T = 8'h41; // @[FSECompressorDicBuilder.scala:703:43] wire [7:0] _remaining_T = 8'h41; // @[FSECompressorDicBuilder.scala:793:35] wire [6:0] _ll_fse_tablestep_T_1 = 7'h8; // @[FSECompressorDicBuilder.scala:405:64] wire [6:0] _ll_fse_tablestep_T = 7'h20; // @[FSECompressorDicBuilder.scala:405:40] wire [7:0] _ll_tableMask_T = 8'h3F; // @[FSECompressorDicBuilder.scala:381:35] wire [7:0] _ll_highThresholdBeforeCumul_T = 8'h3F; // @[FSECompressorDicBuilder.scala:386:47] wire [2:0] _stat_sum_WIRE_0 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_1 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_2 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_3 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_4 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_5 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_6 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_7 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_8 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_9 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_10 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_11 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _stat_sum_WIRE_12 = 3'h0; // @[FSECompressorDicBuilder.scala:186:34] wire [2:0] _io_ll_table_log_bits_T = 3'h6; // @[FSECompressorDicBuilder.scala:452:30] wire [63:0] _ll_count_times_step_WIRE_0 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_1 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_2 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_3 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_4 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_5 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_6 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_7 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_8 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_9 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_10 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_11 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [63:0] _ll_count_times_step_WIRE_12 = 64'h0; // @[FSECompressorDicBuilder.scala:266:45] wire [255:0] _input_ll_symbols_0_T = io_ll_stream_output_data_0; // @[FSECompressorDicBuilder.scala:39:7, :174:53] wire _io_ll_table_log_valid_T_2; // @[FSECompressorDicBuilder.scala:453:48] wire _io_symbol_info_0_ready_T; // @[Misc.scala:26:53] wire io_symbolTT_info_0_bits_from_last_symbol_0 = io_symbol_info_0_bits_last_symbol_0; // @[FSECompressorDicBuilder.scala:39:7] wire _io_symbol_info_1_ready_T; // @[Misc.scala:26:53] wire io_symbolTT_info_1_bits_from_last_symbol_0 = io_symbol_info_1_bits_last_symbol_0; // @[FSECompressorDicBuilder.scala:39:7] wire _io_symbolTT_info_0_valid_T; // @[Misc.scala:26:53] wire [31:0] _io_symbolTT_info_0_bits_findstate_T_1; // @[FSECompressorDicBuilder.scala:435:81] wire _io_symbolTT_info_1_valid_T; // @[Misc.scala:26:53] wire [31:0] _io_symbolTT_info_1_bits_findstate_T_1; // @[FSECompressorDicBuilder.scala:435:81] wire _io_new_state_0_valid_T; // @[FSECompressorDicBuilder.scala:438:47] wire _io_new_state_1_valid_T; // @[FSECompressorDicBuilder.scala:438:47] wire io_nb_seq_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire [5:0] io_ll_stream_user_consumed_bytes_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_stream_output_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_ll_table_log_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_0_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbol_info_1_ready_0; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] io_symbolTT_info_0_bits_nbbit_0; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] io_symbolTT_info_0_bits_findstate_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbolTT_info_0_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] io_symbolTT_info_1_bits_nbbit_0; // @[FSECompressorDicBuilder.scala:39:7] wire [31:0] io_symbolTT_info_1_bits_findstate_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_symbolTT_info_1_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_new_state_0_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire [15:0] io_new_state_0_bits_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_new_state_1_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire [15:0] io_new_state_1_bits_0; // @[FSECompressorDicBuilder.scala:39:7] wire [255:0] io_header_writes_bits_data_0; // @[FSECompressorDicBuilder.scala:39:7] wire [5:0] io_header_writes_bits_validbytes_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_header_writes_valid_0; // @[FSECompressorDicBuilder.scala:39:7] wire io_predefined_mode_valid; // @[FSECompressorDicBuilder.scala:39:7] wire io_predefined_mode_bits; // @[FSECompressorDicBuilder.scala:39:7] reg rtbTable_initialized; // @[FSECompressorDicBuilder.scala:56:37] reg [31:0] rtbTable_1; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_2; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_3; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_4; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_5; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_6; // @[FSECompressorDicBuilder.scala:57:25] reg [31:0] rtbTable_7; // @[FSECompressorDicBuilder.scala:57:25] reg [3:0] dicBuilderState; // @[FSECompressorDicBuilder.scala:156:32] reg [31:0] ll_count_0; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_1; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_2; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_3; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_4; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_5; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_6; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_7; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_8; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_9; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_10; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_11; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_count_12; // @[FSECompressorDicBuilder.scala:169:25] reg [31:0] ll_max_symbol_value; // @[FSECompressorDicBuilder.scala:170:36] reg [63:0] ll_nbseq_1; // @[FSECompressorDicBuilder.scala:171:27] wire [7:0] input_ll_symbols_0; // @[FSECompressorDicBuilder.scala:172:34] wire [7:0] input_ll_symbols_1; // @[FSECompressorDicBuilder.scala:172:34] wire [7:0] input_ll_symbols_2; // @[FSECompressorDicBuilder.scala:172:34] wire [7:0] input_ll_symbols_3; // @[FSECompressorDicBuilder.scala:172:34] assign input_ll_symbols_0 = _input_ll_symbols_0_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire [255:0] _input_ll_symbols_1_T = {8'h0, io_ll_stream_output_data_0[255:8]}; // @[FSECompressorDicBuilder.scala:39:7, :174:53] assign input_ll_symbols_1 = _input_ll_symbols_1_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire [255:0] _input_ll_symbols_2_T = {16'h0, io_ll_stream_output_data_0[255:16]}; // @[FSECompressorDicBuilder.scala:39:7, :174:53] assign input_ll_symbols_2 = _input_ll_symbols_2_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire [255:0] _input_ll_symbols_3_T = {24'h0, io_ll_stream_output_data_0[255:24]}; // @[FSECompressorDicBuilder.scala:39:7, :174:53] assign input_ll_symbols_3 = _input_ll_symbols_3_T[7:0]; // @[FSECompressorDicBuilder.scala:172:34, :174:{25,53}] wire _table_0_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_0_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_0_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_0_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_0_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_0_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_0_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_0_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_1_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_1_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_1_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_1_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_1_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_1_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_1_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_1_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_2_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_2_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_2_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_2_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_2_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_2_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_2_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_2_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_3_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_3_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_3_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_3_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_3_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_3_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_3_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_3_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_4_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_4_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_4_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_4_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_4_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_4_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_4_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_4_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_5_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_5_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_5_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_5_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_5_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_5_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_5_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_5_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_6_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_6_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_6_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_6_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_6_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_6_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_6_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_6_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_7_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_7_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_7_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_7_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_7_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_7_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_7_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_7_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_8_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_8_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_8_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_8_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_8_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_8_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_8_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_8_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_9_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_9_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_9_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_9_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_9_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_9_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_9_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_9_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_10_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_10_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_10_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_10_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_10_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_10_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_10_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_10_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_11_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_11_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_11_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_11_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_11_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_11_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_11_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_11_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_12_0_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_12_1_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_12_2_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire _table_12_3_T_3; // @[FSECompressorDicBuilder.scala:182:25] wire table_12_0; // @[FSECompressorDicBuilder.scala:179:50] wire table_12_1; // @[FSECompressorDicBuilder.scala:179:50] wire table_12_2; // @[FSECompressorDicBuilder.scala:179:50] wire table_12_3; // @[FSECompressorDicBuilder.scala:179:50] wire _table_0_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_0_T_1 = input_ll_symbols_0 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_0_T_2 = _table_0_0_T & _table_0_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_0_T_3 = _table_0_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_0 = _table_0_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_0_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_1_T_1 = input_ll_symbols_1 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_1_T_2 = _table_0_1_T & _table_0_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_1_T_3 = _table_0_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_1 = _table_0_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _GEN = io_ll_stream_available_output_bytes_0 > 6'h2; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_0_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_1_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_1_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_2_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_2_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_3_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_3_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_4_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_4_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_5_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_5_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_6_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_6_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_7_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_7_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_8_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_8_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_9_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_9_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_10_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_10_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_11_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_11_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_12_2_T; // @[FSECompressorDicBuilder.scala:182:30] assign _table_12_2_T = _GEN; // @[FSECompressorDicBuilder.scala:182:30] wire _table_0_2_T_1 = input_ll_symbols_2 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_2_T_2 = _table_0_2_T & _table_0_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_2_T_3 = _table_0_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_2 = _table_0_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_0_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_0_3_T_1 = input_ll_symbols_3 == 8'h0; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_0_3_T_2 = _table_0_3_T & _table_0_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_0_3_T_3 = _table_0_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_0_3 = _table_0_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_1_0_T_1 = input_ll_symbols_0 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_0_T_2 = _table_1_0_T & _table_1_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_0_T_3 = _table_1_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_0 = _table_1_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_1_1_T_1 = input_ll_symbols_1 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_1_T_2 = _table_1_1_T & _table_1_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_1_T_3 = _table_1_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_1 = _table_1_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_2_T_1 = input_ll_symbols_2 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_2_T_2 = _table_1_2_T & _table_1_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_2_T_3 = _table_1_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_2 = _table_1_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_1_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_1_3_T_1 = input_ll_symbols_3 == 8'h1; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_1_3_T_2 = _table_1_3_T & _table_1_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_1_3_T_3 = _table_1_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_1_3 = _table_1_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_2_0_T_1 = input_ll_symbols_0 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_0_T_2 = _table_2_0_T & _table_2_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_0_T_3 = _table_2_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_0 = _table_2_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_2_1_T_1 = input_ll_symbols_1 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_1_T_2 = _table_2_1_T & _table_2_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_1_T_3 = _table_2_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_1 = _table_2_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_2_T_1 = input_ll_symbols_2 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_2_T_2 = _table_2_2_T & _table_2_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_2_T_3 = _table_2_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_2 = _table_2_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_2_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_2_3_T_1 = input_ll_symbols_3 == 8'h2; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_2_3_T_2 = _table_2_3_T & _table_2_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_2_3_T_3 = _table_2_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_2_3 = _table_2_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_3_0_T_1 = input_ll_symbols_0 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_0_T_2 = _table_3_0_T & _table_3_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_0_T_3 = _table_3_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_0 = _table_3_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_3_1_T_1 = input_ll_symbols_1 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_1_T_2 = _table_3_1_T & _table_3_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_1_T_3 = _table_3_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_1 = _table_3_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_2_T_1 = input_ll_symbols_2 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_2_T_2 = _table_3_2_T & _table_3_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_2_T_3 = _table_3_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_2 = _table_3_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_3_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_3_3_T_1 = input_ll_symbols_3 == 8'h3; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_3_3_T_2 = _table_3_3_T & _table_3_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_3_3_T_3 = _table_3_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_3_3 = _table_3_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_4_0_T_1 = input_ll_symbols_0 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_0_T_2 = _table_4_0_T & _table_4_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_0_T_3 = _table_4_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_0 = _table_4_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_4_1_T_1 = input_ll_symbols_1 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_1_T_2 = _table_4_1_T & _table_4_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_1_T_3 = _table_4_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_1 = _table_4_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_2_T_1 = input_ll_symbols_2 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_2_T_2 = _table_4_2_T & _table_4_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_2_T_3 = _table_4_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_2 = _table_4_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_4_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_4_3_T_1 = input_ll_symbols_3 == 8'h4; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_4_3_T_2 = _table_4_3_T & _table_4_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_4_3_T_3 = _table_4_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_4_3 = _table_4_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_5_0_T_1 = input_ll_symbols_0 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_0_T_2 = _table_5_0_T & _table_5_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_0_T_3 = _table_5_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_0 = _table_5_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_5_1_T_1 = input_ll_symbols_1 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_1_T_2 = _table_5_1_T & _table_5_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_1_T_3 = _table_5_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_1 = _table_5_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_2_T_1 = input_ll_symbols_2 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_2_T_2 = _table_5_2_T & _table_5_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_2_T_3 = _table_5_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_2 = _table_5_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_5_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_5_3_T_1 = input_ll_symbols_3 == 8'h5; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_5_3_T_2 = _table_5_3_T & _table_5_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_5_3_T_3 = _table_5_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_5_3 = _table_5_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_6_0_T_1 = input_ll_symbols_0 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_0_T_2 = _table_6_0_T & _table_6_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_0_T_3 = _table_6_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_0 = _table_6_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_6_1_T_1 = input_ll_symbols_1 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_1_T_2 = _table_6_1_T & _table_6_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_1_T_3 = _table_6_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_1 = _table_6_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_2_T_1 = input_ll_symbols_2 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_2_T_2 = _table_6_2_T & _table_6_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_2_T_3 = _table_6_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_2 = _table_6_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_6_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_6_3_T_1 = input_ll_symbols_3 == 8'h6; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_6_3_T_2 = _table_6_3_T & _table_6_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_6_3_T_3 = _table_6_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_6_3 = _table_6_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_7_0_T_1 = input_ll_symbols_0 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_0_T_2 = _table_7_0_T & _table_7_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_0_T_3 = _table_7_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_0 = _table_7_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_7_1_T_1 = input_ll_symbols_1 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_1_T_2 = _table_7_1_T & _table_7_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_1_T_3 = _table_7_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_1 = _table_7_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_2_T_1 = input_ll_symbols_2 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_2_T_2 = _table_7_2_T & _table_7_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_2_T_3 = _table_7_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_2 = _table_7_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_7_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_7_3_T_1 = input_ll_symbols_3 == 8'h7; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_7_3_T_2 = _table_7_3_T & _table_7_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_7_3_T_3 = _table_7_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_7_3 = _table_7_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_8_0_T_1 = input_ll_symbols_0 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_0_T_2 = _table_8_0_T & _table_8_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_0_T_3 = _table_8_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_0 = _table_8_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_8_1_T_1 = input_ll_symbols_1 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_1_T_2 = _table_8_1_T & _table_8_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_1_T_3 = _table_8_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_1 = _table_8_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_2_T_1 = input_ll_symbols_2 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_2_T_2 = _table_8_2_T & _table_8_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_2_T_3 = _table_8_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_2 = _table_8_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_8_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_8_3_T_1 = input_ll_symbols_3 == 8'h8; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_8_3_T_2 = _table_8_3_T & _table_8_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_8_3_T_3 = _table_8_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_8_3 = _table_8_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_9_0_T_1 = input_ll_symbols_0 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_0_T_2 = _table_9_0_T & _table_9_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_0_T_3 = _table_9_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_0 = _table_9_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_9_1_T_1 = input_ll_symbols_1 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_1_T_2 = _table_9_1_T & _table_9_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_1_T_3 = _table_9_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_1 = _table_9_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_2_T_1 = input_ll_symbols_2 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_2_T_2 = _table_9_2_T & _table_9_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_2_T_3 = _table_9_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_2 = _table_9_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_9_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_9_3_T_1 = input_ll_symbols_3 == 8'h9; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_9_3_T_2 = _table_9_3_T & _table_9_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_9_3_T_3 = _table_9_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_9_3 = _table_9_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_10_0_T_1 = input_ll_symbols_0 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_0_T_2 = _table_10_0_T & _table_10_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_0_T_3 = _table_10_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_0 = _table_10_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_10_1_T_1 = input_ll_symbols_1 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_1_T_2 = _table_10_1_T & _table_10_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_1_T_3 = _table_10_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_1 = _table_10_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_2_T_1 = input_ll_symbols_2 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_2_T_2 = _table_10_2_T & _table_10_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_2_T_3 = _table_10_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_2 = _table_10_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_10_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_10_3_T_1 = input_ll_symbols_3 == 8'hA; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_10_3_T_2 = _table_10_3_T & _table_10_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_10_3_T_3 = _table_10_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_10_3 = _table_10_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_11_0_T_1 = input_ll_symbols_0 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_0_T_2 = _table_11_0_T & _table_11_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_0_T_3 = _table_11_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_0 = _table_11_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_11_1_T_1 = input_ll_symbols_1 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_1_T_2 = _table_11_1_T & _table_11_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_1_T_3 = _table_11_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_1 = _table_11_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_2_T_1 = input_ll_symbols_2 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_2_T_2 = _table_11_2_T & _table_11_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_2_T_3 = _table_11_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_2 = _table_11_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_11_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_11_3_T_1 = input_ll_symbols_3 == 8'hB; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_11_3_T_2 = _table_11_3_T & _table_11_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_11_3_T_3 = _table_11_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_11_3 = _table_11_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_0_T = |io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_12_0_T_1 = input_ll_symbols_0 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_0_T_2 = _table_12_0_T & _table_12_0_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_0_T_3 = _table_12_0_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_0 = _table_12_0_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_1_T = |(io_ll_stream_available_output_bytes_0[5:1]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_12_1_T_1 = input_ll_symbols_1 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_1_T_2 = _table_12_1_T & _table_12_1_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_1_T_3 = _table_12_1_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_1 = _table_12_1_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_2_T_1 = input_ll_symbols_2 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_2_T_2 = _table_12_2_T & _table_12_2_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_2_T_3 = _table_12_2_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_2 = _table_12_2_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire _table_12_3_T = |(io_ll_stream_available_output_bytes_0[5:2]); // @[FSECompressorDicBuilder.scala:39:7, :182:30] wire _table_12_3_T_1 = input_ll_symbols_3 == 8'hC; // @[FSECompressorDicBuilder.scala:172:34, :182:68] wire _table_12_3_T_2 = _table_12_3_T & _table_12_3_T_1; // @[FSECompressorDicBuilder.scala:182:{30,44,68}] assign _table_12_3_T_3 = _table_12_3_T_2; // @[FSECompressorDicBuilder.scala:182:{25,44}] assign table_12_3 = _table_12_3_T_3; // @[FSECompressorDicBuilder.scala:179:50, :182:25] wire [2:0] stat_sum_0; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_1; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_2; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_3; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_4; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_5; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_6; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_7; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_8; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_9; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_10; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_11; // @[FSECompressorDicBuilder.scala:186:26] wire [2:0] stat_sum_12; // @[FSECompressorDicBuilder.scala:186:26] wire [1:0] _stat_sum_0_T = {1'h0, table_0_0} + {1'h0, table_0_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_0_T_1 = {1'h0, _stat_sum_0_T} + {2'h0, table_0_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_0_T_2 = {1'h0, _stat_sum_0_T_1} + {3'h0, table_0_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_0 = _stat_sum_0_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_1_T = {1'h0, table_1_0} + {1'h0, table_1_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_1_T_1 = {1'h0, _stat_sum_1_T} + {2'h0, table_1_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_1_T_2 = {1'h0, _stat_sum_1_T_1} + {3'h0, table_1_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_1 = _stat_sum_1_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_2_T = {1'h0, table_2_0} + {1'h0, table_2_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_2_T_1 = {1'h0, _stat_sum_2_T} + {2'h0, table_2_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_2_T_2 = {1'h0, _stat_sum_2_T_1} + {3'h0, table_2_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_2 = _stat_sum_2_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_3_T = {1'h0, table_3_0} + {1'h0, table_3_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_3_T_1 = {1'h0, _stat_sum_3_T} + {2'h0, table_3_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_3_T_2 = {1'h0, _stat_sum_3_T_1} + {3'h0, table_3_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_3 = _stat_sum_3_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_4_T = {1'h0, table_4_0} + {1'h0, table_4_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_4_T_1 = {1'h0, _stat_sum_4_T} + {2'h0, table_4_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_4_T_2 = {1'h0, _stat_sum_4_T_1} + {3'h0, table_4_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_4 = _stat_sum_4_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_5_T = {1'h0, table_5_0} + {1'h0, table_5_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_5_T_1 = {1'h0, _stat_sum_5_T} + {2'h0, table_5_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_5_T_2 = {1'h0, _stat_sum_5_T_1} + {3'h0, table_5_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_5 = _stat_sum_5_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_6_T = {1'h0, table_6_0} + {1'h0, table_6_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_6_T_1 = {1'h0, _stat_sum_6_T} + {2'h0, table_6_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_6_T_2 = {1'h0, _stat_sum_6_T_1} + {3'h0, table_6_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_6 = _stat_sum_6_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_7_T = {1'h0, table_7_0} + {1'h0, table_7_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_7_T_1 = {1'h0, _stat_sum_7_T} + {2'h0, table_7_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_7_T_2 = {1'h0, _stat_sum_7_T_1} + {3'h0, table_7_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_7 = _stat_sum_7_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_8_T = {1'h0, table_8_0} + {1'h0, table_8_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_8_T_1 = {1'h0, _stat_sum_8_T} + {2'h0, table_8_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_8_T_2 = {1'h0, _stat_sum_8_T_1} + {3'h0, table_8_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_8 = _stat_sum_8_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_9_T = {1'h0, table_9_0} + {1'h0, table_9_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_9_T_1 = {1'h0, _stat_sum_9_T} + {2'h0, table_9_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_9_T_2 = {1'h0, _stat_sum_9_T_1} + {3'h0, table_9_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_9 = _stat_sum_9_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_10_T = {1'h0, table_10_0} + {1'h0, table_10_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_10_T_1 = {1'h0, _stat_sum_10_T} + {2'h0, table_10_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_10_T_2 = {1'h0, _stat_sum_10_T_1} + {3'h0, table_10_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_10 = _stat_sum_10_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_11_T = {1'h0, table_11_0} + {1'h0, table_11_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_11_T_1 = {1'h0, _stat_sum_11_T} + {2'h0, table_11_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_11_T_2 = {1'h0, _stat_sum_11_T_1} + {3'h0, table_11_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_11 = _stat_sum_11_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire [1:0] _stat_sum_12_T = {1'h0, table_12_0} + {1'h0, table_12_1}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [2:0] _stat_sum_12_T_1 = {1'h0, _stat_sum_12_T} + {2'h0, table_12_2}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] wire [3:0] _stat_sum_12_T_2 = {1'h0, _stat_sum_12_T_1} + {3'h0, table_12_3}; // @[FSECompressorDicBuilder.scala:179:50, :188:38] assign stat_sum_12 = _stat_sum_12_T_2[2:0]; // @[FSECompressorDicBuilder.scala:186:26, :188:{17,38}] wire _has_value_0_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_1_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_2_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_3_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_4_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_5_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_6_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_7_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_8_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_9_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_10_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_11_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire _has_value_12_T_1; // @[FSECompressorDicBuilder.scala:193:24] wire has_value_0; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_1; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_2; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_3; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_4; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_5; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_6; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_7; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_8; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_9; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_10; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_11; // @[FSECompressorDicBuilder.scala:191:27] wire has_value_12; // @[FSECompressorDicBuilder.scala:191:27] wire _has_value_0_T = |stat_sum_0; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_0_T_1 = _has_value_0_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_0 = _has_value_0_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_1_T = |stat_sum_1; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_1_T_1 = _has_value_1_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_1 = _has_value_1_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_2_T = |stat_sum_2; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_2_T_1 = _has_value_2_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_2 = _has_value_2_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_3_T = |stat_sum_3; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_3_T_1 = _has_value_3_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_3 = _has_value_3_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_4_T = |stat_sum_4; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_4_T_1 = _has_value_4_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_4 = _has_value_4_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_5_T = |stat_sum_5; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_5_T_1 = _has_value_5_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_5 = _has_value_5_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_6_T = |stat_sum_6; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_6_T_1 = _has_value_6_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_6 = _has_value_6_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_7_T = |stat_sum_7; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_7_T_1 = _has_value_7_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_7 = _has_value_7_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_8_T = |stat_sum_8; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_8_T_1 = _has_value_8_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_8 = _has_value_8_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_9_T = |stat_sum_9; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_9_T_1 = _has_value_9_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_9 = _has_value_9_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_10_T = |stat_sum_10; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_10_T_1 = _has_value_10_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_10 = _has_value_10_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_11_T = |stat_sum_11; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_11_T_1 = _has_value_11_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_11 = _has_value_11_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire _has_value_12_T = |stat_sum_12; // @[FSECompressorDicBuilder.scala:186:26, :193:37] assign _has_value_12_T_1 = _has_value_12_T; // @[FSECompressorDicBuilder.scala:193:{24,37}] assign has_value_12 = _has_value_12_T_1; // @[FSECompressorDicBuilder.scala:191:27, :193:24] wire [1:0] has_value_cat_lo_lo_hi = {has_value_10, has_value_11}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [2:0] has_value_cat_lo_lo = {has_value_cat_lo_lo_hi, has_value_12}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_lo_hi_hi = {has_value_7, has_value_8}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [2:0] has_value_cat_lo_hi = {has_value_cat_lo_hi_hi, has_value_9}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [5:0] has_value_cat_lo = {has_value_cat_lo_hi, has_value_cat_lo_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [1:0] has_value_cat_hi_lo_hi = {has_value_4, has_value_5}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [2:0] has_value_cat_hi_lo = {has_value_cat_hi_lo_hi, has_value_6}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_hi_lo = {has_value_2, has_value_3}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [1:0] has_value_cat_hi_hi_hi = {has_value_0, has_value_1}; // @[FSECompressorDicBuilder.scala:191:27, :195:26] wire [3:0] has_value_cat_hi_hi = {has_value_cat_hi_hi_hi, has_value_cat_hi_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [6:0] has_value_cat_hi = {has_value_cat_hi_hi, has_value_cat_hi_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire [12:0] has_value_cat = {has_value_cat_hi, has_value_cat_lo}; // @[FSECompressorDicBuilder.scala:195:26] wire _cur_max_value_T = has_value_cat[0]; // @[OneHot.scala:48:45] wire _cur_max_value_T_1 = has_value_cat[1]; // @[OneHot.scala:48:45] wire _cur_max_value_T_2 = has_value_cat[2]; // @[OneHot.scala:48:45] wire _cur_max_value_T_3 = has_value_cat[3]; // @[OneHot.scala:48:45] wire _cur_max_value_T_4 = has_value_cat[4]; // @[OneHot.scala:48:45] wire _cur_max_value_T_5 = has_value_cat[5]; // @[OneHot.scala:48:45] wire _cur_max_value_T_6 = has_value_cat[6]; // @[OneHot.scala:48:45] wire _cur_max_value_T_7 = has_value_cat[7]; // @[OneHot.scala:48:45] wire _cur_max_value_T_8 = has_value_cat[8]; // @[OneHot.scala:48:45] wire _cur_max_value_T_9 = has_value_cat[9]; // @[OneHot.scala:48:45] wire _cur_max_value_T_10 = has_value_cat[10]; // @[OneHot.scala:48:45] wire _cur_max_value_T_11 = has_value_cat[11]; // @[OneHot.scala:48:45] wire _cur_max_value_T_12 = has_value_cat[12]; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_13 = _cur_max_value_T_11 ? 4'hB : 4'hC; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_14 = _cur_max_value_T_10 ? 4'hA : _cur_max_value_T_13; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_15 = _cur_max_value_T_9 ? 4'h9 : _cur_max_value_T_14; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_16 = _cur_max_value_T_8 ? 4'h8 : _cur_max_value_T_15; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_17 = _cur_max_value_T_7 ? 4'h7 : _cur_max_value_T_16; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_18 = _cur_max_value_T_6 ? 4'h6 : _cur_max_value_T_17; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_19 = _cur_max_value_T_5 ? 4'h5 : _cur_max_value_T_18; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_20 = _cur_max_value_T_4 ? 4'h4 : _cur_max_value_T_19; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_21 = _cur_max_value_T_3 ? 4'h3 : _cur_max_value_T_20; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_22 = _cur_max_value_T_2 ? 4'h2 : _cur_max_value_T_21; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_23 = _cur_max_value_T_1 ? 4'h1 : _cur_max_value_T_22; // @[OneHot.scala:48:45] wire [3:0] _cur_max_value_T_24 = _cur_max_value_T ? 4'h0 : _cur_max_value_T_23; // @[OneHot.scala:48:45] wire [4:0] _cur_max_value_T_25 = 5'hC - {1'h0, _cur_max_value_T_24}; // @[Mux.scala:50:70] wire [3:0] cur_max_value = _cur_max_value_T_25[3:0]; // @[FSECompressorDicBuilder.scala:196:48] wire _T_384 = dicBuilderState == 4'h1; // @[FSECompressorDicBuilder.scala:156:32, :198:25] wire [32:0] _GEN_0 = {1'h0, ll_count_0} + {30'h0, stat_sum_0}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_0_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_0_T = _GEN_0; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_0_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_0_T_2 = _GEN_0; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_0_T_1 = _ll_count_0_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_1 = {1'h0, ll_count_1} + {30'h0, stat_sum_1}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_1_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_1_T = _GEN_1; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_1_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_1_T_2 = _GEN_1; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_1_T_1 = _ll_count_1_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_2 = {1'h0, ll_count_2} + {30'h0, stat_sum_2}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_2_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_2_T = _GEN_2; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_2_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_2_T_2 = _GEN_2; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_2_T_1 = _ll_count_2_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_3 = {1'h0, ll_count_3} + {30'h0, stat_sum_3}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_3_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_3_T = _GEN_3; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_3_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_3_T_2 = _GEN_3; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_3_T_1 = _ll_count_3_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_4 = {1'h0, ll_count_4} + {30'h0, stat_sum_4}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_4_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_4_T = _GEN_4; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_4_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_4_T_2 = _GEN_4; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_4_T_1 = _ll_count_4_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_5 = {1'h0, ll_count_5} + {30'h0, stat_sum_5}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_5_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_5_T = _GEN_5; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_5_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_5_T_2 = _GEN_5; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_5_T_1 = _ll_count_5_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_6 = {1'h0, ll_count_6} + {30'h0, stat_sum_6}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_6_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_6_T = _GEN_6; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_6_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_6_T_2 = _GEN_6; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_6_T_1 = _ll_count_6_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_7 = {1'h0, ll_count_7} + {30'h0, stat_sum_7}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_7_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_7_T = _GEN_7; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_7_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_7_T_2 = _GEN_7; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_7_T_1 = _ll_count_7_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_8 = {1'h0, ll_count_8} + {30'h0, stat_sum_8}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_8_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_8_T = _GEN_8; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_8_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_8_T_2 = _GEN_8; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_8_T_1 = _ll_count_8_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_9 = {1'h0, ll_count_9} + {30'h0, stat_sum_9}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_9_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_9_T = _GEN_9; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_9_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_9_T_2 = _GEN_9; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_9_T_1 = _ll_count_9_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_10 = {1'h0, ll_count_10} + {30'h0, stat_sum_10}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_10_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_10_T = _GEN_10; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_10_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_10_T_2 = _GEN_10; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_10_T_1 = _ll_count_10_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_11 = {1'h0, ll_count_11} + {30'h0, stat_sum_11}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_11_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_11_T = _GEN_11; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_11_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_11_T_2 = _GEN_11; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_11_T_1 = _ll_count_11_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _GEN_12 = {1'h0, ll_count_12} + {30'h0, stat_sum_12}; // @[FSECompressorDicBuilder.scala:169:25, :186:26, :201:36] wire [32:0] _ll_count_12_T; // @[FSECompressorDicBuilder.scala:201:36] assign _ll_count_12_T = _GEN_12; // @[FSECompressorDicBuilder.scala:201:36] wire [32:0] _ll_count_12_T_2; // @[FSECompressorDicBuilder.scala:566:38] assign _ll_count_12_T_2 = _GEN_12; // @[FSECompressorDicBuilder.scala:201:36, :566:38] wire [31:0] _ll_count_12_T_1 = _ll_count_12_T[31:0]; // @[FSECompressorDicBuilder.scala:201:36] wire [31:0] _GEN_13 = {28'h0, cur_max_value}; // @[FSECompressorDicBuilder.scala:196:48, :204:54] wire _GEN_14 = ll_max_symbol_value > _GEN_13; // @[FSECompressorDicBuilder.scala:170:36, :204:54] wire _ll_max_symbol_value_T; // @[FSECompressorDicBuilder.scala:204:54] assign _ll_max_symbol_value_T = _GEN_14; // @[FSECompressorDicBuilder.scala:204:54] wire _ll_max_symbol_value_T_2; // @[FSECompressorDicBuilder.scala:569:56] assign _ll_max_symbol_value_T_2 = _GEN_14; // @[FSECompressorDicBuilder.scala:204:54, :569:56] wire [31:0] _ll_max_symbol_value_T_1 = _ll_max_symbol_value_T ? ll_max_symbol_value : _GEN_13; // @[FSECompressorDicBuilder.scala:170:36, :204:{33,54}] wire ll_useLowProbCount = ll_nbseq_1 > 64'hFFFFFFFE; // @[FSECompressorDicBuilder.scala:171:27, :248:39] wire [15:0] _ll_lowProbCount_T; // @[FSECompressorDicBuilder.scala:250:25] wire [15:0] ll_lowProbCount; // @[FSECompressorDicBuilder.scala:249:29] assign _ll_lowProbCount_T = ll_useLowProbCount ? 16'hFFFF : 16'h1; // @[FSECompressorDicBuilder.scala:248:39, :250:25] assign ll_lowProbCount = _ll_lowProbCount_T; // @[FSECompressorDicBuilder.scala:249:29, :250:25] wire [63:0] ll_step; // @[FSECompressorDicBuilder.scala:253:21] wire [63:0] _GEN_15 = 64'h4000000000000000 / ll_nbseq_1; // @[FSECompressorDicBuilder.scala:171:27, :254:47] wire [62:0] _ll_step_T = _GEN_15[62:0]; // @[FSECompressorDicBuilder.scala:254:47] assign ll_step = {1'h0, _ll_step_T}; // @[FSECompressorDicBuilder.scala:253:21, :254:{11,47}] wire [31:0] ll_lowThreshold; // @[FSECompressorDicBuilder.scala:260:29] wire [63:0] _ll_lowThreshold_T = {6'h0, ll_nbseq_1[63:6]}; // @[FSECompressorDicBuilder.scala:171:27, :261:33] assign ll_lowThreshold = _ll_lowThreshold_T[31:0]; // @[FSECompressorDicBuilder.scala:260:29, :261:{19,33}] wire [15:0] ll_proba_base_0; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_1; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_2; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_3; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_4; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_5; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_6; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_7; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_8; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_9; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_10; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_11; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] ll_proba_base_12; // @[FSECompressorDicBuilder.scala:264:31] wire [15:0] _ll_proba_0_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_1_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_2_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_3_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_4_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_5_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_6_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_7_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_8_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_9_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_10_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_11_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] _ll_proba_12_T_3; // @[FSECompressorDicBuilder.scala:273:23] wire [15:0] ll_proba_0; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_1; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_2; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_3; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_4; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_5; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_6; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_7; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_8; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_9; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_10; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_11; // @[FSECompressorDicBuilder.scala:265:26] wire [15:0] ll_proba_12; // @[FSECompressorDicBuilder.scala:265:26] wire [63:0] ll_count_times_step_0; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_1; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_2; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_3; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_4; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_5; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_6; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_7; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_8; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_9; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_10; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_11; // @[FSECompressorDicBuilder.scala:266:37] wire [63:0] ll_count_times_step_12; // @[FSECompressorDicBuilder.scala:266:37] wire [95:0] _GEN_16 = {32'h0, ll_step}; // @[FSECompressorDicBuilder.scala:253:21, :268:43] wire [95:0] _GEN_17 = {64'h0, ll_count_0} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_0_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_0_T = _GEN_17; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T = _GEN_17; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_0 = _ll_count_times_step_0_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_0_T = {56'h0, ll_count_times_step_0[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_0 = _ll_proba_base_0_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T = ll_proba_base_0[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [7:0][31:0] _GEN_18 = {{rtbTable_7}, {rtbTable_6}, {rtbTable_5}, {rtbTable_4}, {rtbTable_3}, {rtbTable_2}, {rtbTable_1}, {32'h0}}; // @[FSECompressorDicBuilder.scala:57:25, :271:31] wire [95:0] restToBeat = {28'h0, _GEN_18[_restToBeat_T], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_1 = {71'h0, ll_proba_base_0, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_2 = {48'h0, _ll_add_to_proba_base_T} - {1'h0, _ll_add_to_proba_base_T_1}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_3 = _ll_add_to_proba_base_T_2[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_4 = _ll_add_to_proba_base_T_3 > {47'h0, restToBeat}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base = _ll_add_to_proba_base_T_4; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_0_T = ll_proba_base_0 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_0_T_1 = {1'h0, ll_proba_base_0} + {16'h0, ll_add_to_proba_base}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_0_T_2 = _ll_proba_0_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_0_T_3 = _ll_proba_0_T ? _ll_proba_0_T_2 : ll_proba_base_0; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_0 = _ll_proba_0_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_19 = {64'h0, ll_count_1} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_1_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_1_T = _GEN_19; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_5; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_5 = _GEN_19; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_1 = _ll_count_times_step_1_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_1_T = {56'h0, ll_count_times_step_1[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_1 = _ll_proba_base_1_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_1 = ll_proba_base_1[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_1 = {28'h0, _GEN_18[_restToBeat_T_1], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_6 = {71'h0, ll_proba_base_1, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_7 = {48'h0, _ll_add_to_proba_base_T_5} - {1'h0, _ll_add_to_proba_base_T_6}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_8 = _ll_add_to_proba_base_T_7[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_9 = _ll_add_to_proba_base_T_8 > {47'h0, restToBeat_1}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_1 = _ll_add_to_proba_base_T_9; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_1_T = ll_proba_base_1 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_1_T_1 = {1'h0, ll_proba_base_1} + {16'h0, ll_add_to_proba_base_1}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_1_T_2 = _ll_proba_1_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_1_T_3 = _ll_proba_1_T ? _ll_proba_1_T_2 : ll_proba_base_1; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_1 = _ll_proba_1_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_20 = {64'h0, ll_count_2} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_2_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_2_T = _GEN_20; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_10; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_10 = _GEN_20; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_2 = _ll_count_times_step_2_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_2_T = {56'h0, ll_count_times_step_2[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_2 = _ll_proba_base_2_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_2 = ll_proba_base_2[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_2 = {28'h0, _GEN_18[_restToBeat_T_2], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_11 = {71'h0, ll_proba_base_2, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_12 = {48'h0, _ll_add_to_proba_base_T_10} - {1'h0, _ll_add_to_proba_base_T_11}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_13 = _ll_add_to_proba_base_T_12[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_14 = _ll_add_to_proba_base_T_13 > {47'h0, restToBeat_2}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_2 = _ll_add_to_proba_base_T_14; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_2_T = ll_proba_base_2 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_2_T_1 = {1'h0, ll_proba_base_2} + {16'h0, ll_add_to_proba_base_2}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_2_T_2 = _ll_proba_2_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_2_T_3 = _ll_proba_2_T ? _ll_proba_2_T_2 : ll_proba_base_2; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_2 = _ll_proba_2_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_21 = {64'h0, ll_count_3} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_3_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_3_T = _GEN_21; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_15; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_15 = _GEN_21; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_3 = _ll_count_times_step_3_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_3_T = {56'h0, ll_count_times_step_3[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_3 = _ll_proba_base_3_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_3 = ll_proba_base_3[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_3 = {28'h0, _GEN_18[_restToBeat_T_3], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_16 = {71'h0, ll_proba_base_3, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_17 = {48'h0, _ll_add_to_proba_base_T_15} - {1'h0, _ll_add_to_proba_base_T_16}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_18 = _ll_add_to_proba_base_T_17[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_19 = _ll_add_to_proba_base_T_18 > {47'h0, restToBeat_3}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_3 = _ll_add_to_proba_base_T_19; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_3_T = ll_proba_base_3 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_3_T_1 = {1'h0, ll_proba_base_3} + {16'h0, ll_add_to_proba_base_3}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_3_T_2 = _ll_proba_3_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_3_T_3 = _ll_proba_3_T ? _ll_proba_3_T_2 : ll_proba_base_3; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_3 = _ll_proba_3_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_22 = {64'h0, ll_count_4} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_4_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_4_T = _GEN_22; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_20; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_20 = _GEN_22; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_4 = _ll_count_times_step_4_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_4_T = {56'h0, ll_count_times_step_4[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_4 = _ll_proba_base_4_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_4 = ll_proba_base_4[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_4 = {28'h0, _GEN_18[_restToBeat_T_4], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_21 = {71'h0, ll_proba_base_4, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_22 = {48'h0, _ll_add_to_proba_base_T_20} - {1'h0, _ll_add_to_proba_base_T_21}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_23 = _ll_add_to_proba_base_T_22[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_24 = _ll_add_to_proba_base_T_23 > {47'h0, restToBeat_4}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_4 = _ll_add_to_proba_base_T_24; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_4_T = ll_proba_base_4 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_4_T_1 = {1'h0, ll_proba_base_4} + {16'h0, ll_add_to_proba_base_4}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_4_T_2 = _ll_proba_4_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_4_T_3 = _ll_proba_4_T ? _ll_proba_4_T_2 : ll_proba_base_4; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_4 = _ll_proba_4_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_23 = {64'h0, ll_count_5} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_5_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_5_T = _GEN_23; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_25; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_25 = _GEN_23; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_5 = _ll_count_times_step_5_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_5_T = {56'h0, ll_count_times_step_5[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_5 = _ll_proba_base_5_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_5 = ll_proba_base_5[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_5 = {28'h0, _GEN_18[_restToBeat_T_5], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_26 = {71'h0, ll_proba_base_5, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_27 = {48'h0, _ll_add_to_proba_base_T_25} - {1'h0, _ll_add_to_proba_base_T_26}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_28 = _ll_add_to_proba_base_T_27[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_29 = _ll_add_to_proba_base_T_28 > {47'h0, restToBeat_5}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_5 = _ll_add_to_proba_base_T_29; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_5_T = ll_proba_base_5 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_5_T_1 = {1'h0, ll_proba_base_5} + {16'h0, ll_add_to_proba_base_5}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_5_T_2 = _ll_proba_5_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_5_T_3 = _ll_proba_5_T ? _ll_proba_5_T_2 : ll_proba_base_5; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_5 = _ll_proba_5_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_24 = {64'h0, ll_count_6} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_6_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_6_T = _GEN_24; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_30; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_30 = _GEN_24; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_6 = _ll_count_times_step_6_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_6_T = {56'h0, ll_count_times_step_6[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_6 = _ll_proba_base_6_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_6 = ll_proba_base_6[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_6 = {28'h0, _GEN_18[_restToBeat_T_6], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_31 = {71'h0, ll_proba_base_6, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_32 = {48'h0, _ll_add_to_proba_base_T_30} - {1'h0, _ll_add_to_proba_base_T_31}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_33 = _ll_add_to_proba_base_T_32[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_34 = _ll_add_to_proba_base_T_33 > {47'h0, restToBeat_6}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_6 = _ll_add_to_proba_base_T_34; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_6_T = ll_proba_base_6 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_6_T_1 = {1'h0, ll_proba_base_6} + {16'h0, ll_add_to_proba_base_6}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_6_T_2 = _ll_proba_6_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_6_T_3 = _ll_proba_6_T ? _ll_proba_6_T_2 : ll_proba_base_6; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_6 = _ll_proba_6_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_25 = {64'h0, ll_count_7} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_7_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_7_T = _GEN_25; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_35; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_35 = _GEN_25; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_7 = _ll_count_times_step_7_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_7_T = {56'h0, ll_count_times_step_7[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_7 = _ll_proba_base_7_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_7 = ll_proba_base_7[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_7 = {28'h0, _GEN_18[_restToBeat_T_7], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_36 = {71'h0, ll_proba_base_7, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_37 = {48'h0, _ll_add_to_proba_base_T_35} - {1'h0, _ll_add_to_proba_base_T_36}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_38 = _ll_add_to_proba_base_T_37[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_39 = _ll_add_to_proba_base_T_38 > {47'h0, restToBeat_7}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_7 = _ll_add_to_proba_base_T_39; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_7_T = ll_proba_base_7 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_7_T_1 = {1'h0, ll_proba_base_7} + {16'h0, ll_add_to_proba_base_7}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_7_T_2 = _ll_proba_7_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_7_T_3 = _ll_proba_7_T ? _ll_proba_7_T_2 : ll_proba_base_7; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_7 = _ll_proba_7_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_26 = {64'h0, ll_count_8} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_8_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_8_T = _GEN_26; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_40; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_40 = _GEN_26; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_8 = _ll_count_times_step_8_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_8_T = {56'h0, ll_count_times_step_8[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_8 = _ll_proba_base_8_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_8 = ll_proba_base_8[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_8 = {28'h0, _GEN_18[_restToBeat_T_8], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_41 = {71'h0, ll_proba_base_8, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_42 = {48'h0, _ll_add_to_proba_base_T_40} - {1'h0, _ll_add_to_proba_base_T_41}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_43 = _ll_add_to_proba_base_T_42[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_44 = _ll_add_to_proba_base_T_43 > {47'h0, restToBeat_8}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_8 = _ll_add_to_proba_base_T_44; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_8_T = ll_proba_base_8 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_8_T_1 = {1'h0, ll_proba_base_8} + {16'h0, ll_add_to_proba_base_8}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_8_T_2 = _ll_proba_8_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_8_T_3 = _ll_proba_8_T ? _ll_proba_8_T_2 : ll_proba_base_8; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_8 = _ll_proba_8_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_27 = {64'h0, ll_count_9} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_9_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_9_T = _GEN_27; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_45; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_45 = _GEN_27; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_9 = _ll_count_times_step_9_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_9_T = {56'h0, ll_count_times_step_9[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_9 = _ll_proba_base_9_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_9 = ll_proba_base_9[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_9 = {28'h0, _GEN_18[_restToBeat_T_9], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_46 = {71'h0, ll_proba_base_9, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_47 = {48'h0, _ll_add_to_proba_base_T_45} - {1'h0, _ll_add_to_proba_base_T_46}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_48 = _ll_add_to_proba_base_T_47[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_49 = _ll_add_to_proba_base_T_48 > {47'h0, restToBeat_9}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_9 = _ll_add_to_proba_base_T_49; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_9_T = ll_proba_base_9 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_9_T_1 = {1'h0, ll_proba_base_9} + {16'h0, ll_add_to_proba_base_9}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_9_T_2 = _ll_proba_9_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_9_T_3 = _ll_proba_9_T ? _ll_proba_9_T_2 : ll_proba_base_9; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_9 = _ll_proba_9_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_28 = {64'h0, ll_count_10} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_10_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_10_T = _GEN_28; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_50; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_50 = _GEN_28; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_10 = _ll_count_times_step_10_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_10_T = {56'h0, ll_count_times_step_10[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_10 = _ll_proba_base_10_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_10 = ll_proba_base_10[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_10 = {28'h0, _GEN_18[_restToBeat_T_10], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_51 = {71'h0, ll_proba_base_10, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_52 = {48'h0, _ll_add_to_proba_base_T_50} - {1'h0, _ll_add_to_proba_base_T_51}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_53 = _ll_add_to_proba_base_T_52[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_54 = _ll_add_to_proba_base_T_53 > {47'h0, restToBeat_10}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_10 = _ll_add_to_proba_base_T_54; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_10_T = ll_proba_base_10 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_10_T_1 = {1'h0, ll_proba_base_10} + {16'h0, ll_add_to_proba_base_10}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_10_T_2 = _ll_proba_10_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_10_T_3 = _ll_proba_10_T ? _ll_proba_10_T_2 : ll_proba_base_10; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_10 = _ll_proba_10_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_29 = {64'h0, ll_count_11} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_11_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_11_T = _GEN_29; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_55; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_55 = _GEN_29; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_11 = _ll_count_times_step_11_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_11_T = {56'h0, ll_count_times_step_11[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_11 = _ll_proba_base_11_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_11 = ll_proba_base_11[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_11 = {28'h0, _GEN_18[_restToBeat_T_11], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_56 = {71'h0, ll_proba_base_11, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_57 = {48'h0, _ll_add_to_proba_base_T_55} - {1'h0, _ll_add_to_proba_base_T_56}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_58 = _ll_add_to_proba_base_T_57[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_59 = _ll_add_to_proba_base_T_58 > {47'h0, restToBeat_11}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_11 = _ll_add_to_proba_base_T_59; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_11_T = ll_proba_base_11 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_11_T_1 = {1'h0, ll_proba_base_11} + {16'h0, ll_add_to_proba_base_11}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_11_T_2 = _ll_proba_11_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_11_T_3 = _ll_proba_11_T ? _ll_proba_11_T_2 : ll_proba_base_11; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_11 = _ll_proba_11_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [95:0] _GEN_30 = {64'h0, ll_count_12} * _GEN_16; // @[FSECompressorDicBuilder.scala:169:25, :268:43] wire [95:0] _ll_count_times_step_12_T; // @[FSECompressorDicBuilder.scala:268:43] assign _ll_count_times_step_12_T = _GEN_30; // @[FSECompressorDicBuilder.scala:268:43] wire [95:0] _ll_add_to_proba_base_T_60; // @[FSECompressorDicBuilder.scala:272:48] assign _ll_add_to_proba_base_T_60 = _GEN_30; // @[FSECompressorDicBuilder.scala:268:43, :272:48] assign ll_count_times_step_12 = _ll_count_times_step_12_T[63:0]; // @[FSECompressorDicBuilder.scala:266:37, :268:{28,43}] wire [63:0] _ll_proba_base_12_T = {56'h0, ll_count_times_step_12[63:56]}; // @[FSECompressorDicBuilder.scala:266:37, :269:48] assign ll_proba_base_12 = _ll_proba_base_12_T[15:0]; // @[FSECompressorDicBuilder.scala:264:31, :269:{22,48}] wire [2:0] _restToBeat_T_12 = ll_proba_base_12[2:0]; // @[FSECompressorDicBuilder.scala:264:31] wire [95:0] restToBeat_12 = {28'h0, _GEN_18[_restToBeat_T_12], 36'h0}; // @[FSECompressorDicBuilder.scala:271:31] wire [142:0] _ll_add_to_proba_base_T_61 = {71'h0, ll_proba_base_12, 56'h0}; // @[FSECompressorDicBuilder.scala:264:31, :272:78] wire [143:0] _ll_add_to_proba_base_T_62 = {48'h0, _ll_add_to_proba_base_T_60} - {1'h0, _ll_add_to_proba_base_T_61}; // @[FSECompressorDicBuilder.scala:272:{48,58,78}] wire [142:0] _ll_add_to_proba_base_T_63 = _ll_add_to_proba_base_T_62[142:0]; // @[FSECompressorDicBuilder.scala:272:58] wire _ll_add_to_proba_base_T_64 = _ll_add_to_proba_base_T_63 > {47'h0, restToBeat_12}; // @[FSECompressorDicBuilder.scala:271:31, :272:{58,91}] wire ll_add_to_proba_base_12 = _ll_add_to_proba_base_T_64; // @[FSECompressorDicBuilder.scala:272:{35,91}] wire _ll_proba_12_T = ll_proba_base_12 < 16'h8; // @[FSECompressorDicBuilder.scala:264:31, :273:41] wire [16:0] _ll_proba_12_T_1 = {1'h0, ll_proba_base_12} + {16'h0, ll_add_to_proba_base_12}; // @[FSECompressorDicBuilder.scala:264:31, :272:35, :273:65] wire [15:0] _ll_proba_12_T_2 = _ll_proba_12_T_1[15:0]; // @[FSECompressorDicBuilder.scala:273:65] assign _ll_proba_12_T_3 = _ll_proba_12_T ? _ll_proba_12_T_2 : ll_proba_base_12; // @[FSECompressorDicBuilder.scala:264:31, :273:{23,41,65}] assign ll_proba_12 = _ll_proba_12_T_3; // @[FSECompressorDicBuilder.scala:265:26, :273:23] wire [15:0] _ll_normalizedCounter_0_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_normalizedCounter_1_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T = ll_normalizedCounter_0; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_2_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_4 = ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_3_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_8 = ll_normalizedCounter_2; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_4_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_12 = ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_5_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_16 = ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_6_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_20 = ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_7_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_24 = ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_8_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_28 = ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_9_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_32 = ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_10_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_36 = ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_11_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_40 = ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] _ll_normalizedCounter_12_T_3; // @[FSECompressorDicBuilder.scala:285:35] wire [15:0] _ll_ncountSumStill2Dist_T_44 = ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38] wire [15:0] _ll_ncountSumStill2Dist_T_48 = ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38, :320:61] wire [15:0] ll_normalizedCounterMaxAdjusted_0; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_1; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_2; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_3; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_4; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_5; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_6; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_7; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_8; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_9; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_10; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_11; // @[FSECompressorDicBuilder.scala:278:49] wire [15:0] ll_normalizedCounterMaxAdjusted_12; // @[FSECompressorDicBuilder.scala:278:49] wire _GEN_31 = {32'h0, ll_count_0} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T = _GEN_31; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T = _GEN_31; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_32 = {32'h0, ll_count_1} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_1; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_1 = _GEN_32; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_6; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_6 = _GEN_32; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_33 = {32'h0, ll_count_2} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_2; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_2 = _GEN_33; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_12; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_12 = _GEN_33; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_34 = {32'h0, ll_count_3} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_3; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_3 = _GEN_34; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_18; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_18 = _GEN_34; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_35 = {32'h0, ll_count_4} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_4; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_4 = _GEN_35; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_24; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_24 = _GEN_35; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_36 = {32'h0, ll_count_5} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_5; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_5 = _GEN_36; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_30; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_30 = _GEN_36; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_37 = {32'h0, ll_count_6} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_6; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_6 = _GEN_37; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_36; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_36 = _GEN_37; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_38 = {32'h0, ll_count_7} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_7; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_7 = _GEN_38; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_42; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_42 = _GEN_38; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_39 = {32'h0, ll_count_8} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_8; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_8 = _GEN_39; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_48; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_48 = _GEN_39; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_40 = {32'h0, ll_count_9} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_9; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_9 = _GEN_40; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_54; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_54 = _GEN_40; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_41 = {32'h0, ll_count_10} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_10; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_10 = _GEN_41; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_60; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_60 = _GEN_41; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_42 = {32'h0, ll_count_11} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_11; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_11 = _GEN_42; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_66; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_66 = _GEN_42; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _GEN_43 = {32'h0, ll_count_12} == ll_nbseq_1; // @[FSECompressorDicBuilder.scala:169:25, :171:27, :280:11] wire _ll_count_has_nbseq_1_as_value_T_12; // @[FSECompressorDicBuilder.scala:280:11] assign _ll_count_has_nbseq_1_as_value_T_12 = _GEN_43; // @[FSECompressorDicBuilder.scala:280:11] wire _ll_largerThanLowThresholdProbaSum_T_72; // @[FSECompressorDicBuilder.scala:295:16] assign _ll_largerThanLowThresholdProbaSum_T_72 = _GEN_43; // @[FSECompressorDicBuilder.scala:280:11, :295:16] wire _ll_count_has_nbseq_1_as_value_T_13 = _ll_count_has_nbseq_1_as_value_T | _ll_count_has_nbseq_1_as_value_T_1; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_14 = _ll_count_has_nbseq_1_as_value_T_13 | _ll_count_has_nbseq_1_as_value_T_2; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_15 = _ll_count_has_nbseq_1_as_value_T_14 | _ll_count_has_nbseq_1_as_value_T_3; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_16 = _ll_count_has_nbseq_1_as_value_T_15 | _ll_count_has_nbseq_1_as_value_T_4; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_17 = _ll_count_has_nbseq_1_as_value_T_16 | _ll_count_has_nbseq_1_as_value_T_5; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_18 = _ll_count_has_nbseq_1_as_value_T_17 | _ll_count_has_nbseq_1_as_value_T_6; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_19 = _ll_count_has_nbseq_1_as_value_T_18 | _ll_count_has_nbseq_1_as_value_T_7; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_20 = _ll_count_has_nbseq_1_as_value_T_19 | _ll_count_has_nbseq_1_as_value_T_8; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_21 = _ll_count_has_nbseq_1_as_value_T_20 | _ll_count_has_nbseq_1_as_value_T_9; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_22 = _ll_count_has_nbseq_1_as_value_T_21 | _ll_count_has_nbseq_1_as_value_T_10; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _ll_count_has_nbseq_1_as_value_T_23 = _ll_count_has_nbseq_1_as_value_T_22 | _ll_count_has_nbseq_1_as_value_T_11; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire ll_count_has_nbseq_1_as_value = _ll_count_has_nbseq_1_as_value_T_23 | _ll_count_has_nbseq_1_as_value_T_12; // @[FSECompressorDicBuilder.scala:280:11, :281:14] wire _GEN_44 = ll_count_0 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_0_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_0_T = _GEN_44; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_1; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_1 = _GEN_44; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_45 = ll_count_0 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_0_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_0_T_1 = _GEN_45; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T = _GEN_45; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_3; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_3 = _GEN_45; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_0_T_2 = _ll_normalizedCounter_0_T_1 ? ll_lowProbCount : ll_proba_0; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_0_T_3 = _ll_normalizedCounter_0_T ? 16'h0 : _ll_normalizedCounter_0_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_0 = _ll_normalizedCounter_0_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_46 = ll_count_1 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_1_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_1_T = _GEN_46; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_7; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_7 = _GEN_46; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_47 = ll_count_1 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_1_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_1_T_1 = _GEN_47; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_3; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_3 = _GEN_47; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_9; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_9 = _GEN_47; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_1_T_2 = _ll_normalizedCounter_1_T_1 ? ll_lowProbCount : ll_proba_1; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_1_T_3 = _ll_normalizedCounter_1_T ? 16'h0 : _ll_normalizedCounter_1_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_1 = _ll_normalizedCounter_1_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_48 = ll_count_2 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_2_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_2_T = _GEN_48; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_13; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_13 = _GEN_48; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_49 = ll_count_2 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_2_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_2_T_1 = _GEN_49; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_6; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_6 = _GEN_49; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_15; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_15 = _GEN_49; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_2_T_2 = _ll_normalizedCounter_2_T_1 ? ll_lowProbCount : ll_proba_2; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_2_T_3 = _ll_normalizedCounter_2_T ? 16'h0 : _ll_normalizedCounter_2_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_2 = _ll_normalizedCounter_2_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_50 = ll_count_3 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_3_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_3_T = _GEN_50; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_19; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_19 = _GEN_50; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_51 = ll_count_3 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_3_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_3_T_1 = _GEN_51; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_9; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_9 = _GEN_51; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_21; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_21 = _GEN_51; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_3_T_2 = _ll_normalizedCounter_3_T_1 ? ll_lowProbCount : ll_proba_3; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_3_T_3 = _ll_normalizedCounter_3_T ? 16'h0 : _ll_normalizedCounter_3_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_3 = _ll_normalizedCounter_3_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_52 = ll_count_4 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_4_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_4_T = _GEN_52; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_25; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_25 = _GEN_52; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_53 = ll_count_4 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_4_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_4_T_1 = _GEN_53; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_12; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_12 = _GEN_53; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_27; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_27 = _GEN_53; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_4_T_2 = _ll_normalizedCounter_4_T_1 ? ll_lowProbCount : ll_proba_4; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_4_T_3 = _ll_normalizedCounter_4_T ? 16'h0 : _ll_normalizedCounter_4_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_4 = _ll_normalizedCounter_4_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_54 = ll_count_5 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_5_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_5_T = _GEN_54; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_31; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_31 = _GEN_54; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_55 = ll_count_5 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_5_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_5_T_1 = _GEN_55; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_15; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_15 = _GEN_55; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_33; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_33 = _GEN_55; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_5_T_2 = _ll_normalizedCounter_5_T_1 ? ll_lowProbCount : ll_proba_5; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_5_T_3 = _ll_normalizedCounter_5_T ? 16'h0 : _ll_normalizedCounter_5_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_5 = _ll_normalizedCounter_5_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_56 = ll_count_6 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_6_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_6_T = _GEN_56; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_37; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_37 = _GEN_56; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_57 = ll_count_6 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_6_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_6_T_1 = _GEN_57; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_18; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_18 = _GEN_57; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_39; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_39 = _GEN_57; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_6_T_2 = _ll_normalizedCounter_6_T_1 ? ll_lowProbCount : ll_proba_6; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_6_T_3 = _ll_normalizedCounter_6_T ? 16'h0 : _ll_normalizedCounter_6_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_6 = _ll_normalizedCounter_6_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_58 = ll_count_7 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_7_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_7_T = _GEN_58; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_43; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_43 = _GEN_58; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_59 = ll_count_7 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_7_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_7_T_1 = _GEN_59; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_21; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_21 = _GEN_59; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_45; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_45 = _GEN_59; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_7_T_2 = _ll_normalizedCounter_7_T_1 ? ll_lowProbCount : ll_proba_7; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_7_T_3 = _ll_normalizedCounter_7_T ? 16'h0 : _ll_normalizedCounter_7_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_7 = _ll_normalizedCounter_7_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_60 = ll_count_8 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_8_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_8_T = _GEN_60; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_49; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_49 = _GEN_60; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_61 = ll_count_8 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_8_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_8_T_1 = _GEN_61; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_24; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_24 = _GEN_61; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_51; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_51 = _GEN_61; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_8_T_2 = _ll_normalizedCounter_8_T_1 ? ll_lowProbCount : ll_proba_8; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_8_T_3 = _ll_normalizedCounter_8_T ? 16'h0 : _ll_normalizedCounter_8_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_8 = _ll_normalizedCounter_8_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_62 = ll_count_9 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_9_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_9_T = _GEN_62; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_55; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_55 = _GEN_62; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_63 = ll_count_9 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_9_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_9_T_1 = _GEN_63; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_27; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_27 = _GEN_63; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_57; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_57 = _GEN_63; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_9_T_2 = _ll_normalizedCounter_9_T_1 ? ll_lowProbCount : ll_proba_9; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_9_T_3 = _ll_normalizedCounter_9_T ? 16'h0 : _ll_normalizedCounter_9_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_9 = _ll_normalizedCounter_9_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_64 = ll_count_10 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_10_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_10_T = _GEN_64; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_61; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_61 = _GEN_64; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_65 = ll_count_10 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_10_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_10_T_1 = _GEN_65; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_30; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_30 = _GEN_65; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_63; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_63 = _GEN_65; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_10_T_2 = _ll_normalizedCounter_10_T_1 ? ll_lowProbCount : ll_proba_10; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_10_T_3 = _ll_normalizedCounter_10_T ? 16'h0 : _ll_normalizedCounter_10_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_10 = _ll_normalizedCounter_10_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_66 = ll_count_11 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_11_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_11_T = _GEN_66; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_67; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_67 = _GEN_66; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_67 = ll_count_11 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_11_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_11_T_1 = _GEN_67; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_33; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_33 = _GEN_67; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_69; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_69 = _GEN_67; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_11_T_2 = _ll_normalizedCounter_11_T_1 ? ll_lowProbCount : ll_proba_11; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_11_T_3 = _ll_normalizedCounter_11_T ? 16'h0 : _ll_normalizedCounter_11_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_11 = _ll_normalizedCounter_11_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _GEN_68 = ll_count_12 == 32'h0; // @[FSECompressorDicBuilder.scala:169:25, :285:48] wire _ll_normalizedCounter_12_T; // @[FSECompressorDicBuilder.scala:285:48] assign _ll_normalizedCounter_12_T = _GEN_68; // @[FSECompressorDicBuilder.scala:285:48] wire _ll_largerThanLowThresholdProbaSum_T_73; // @[FSECompressorDicBuilder.scala:295:42] assign _ll_largerThanLowThresholdProbaSum_T_73 = _GEN_68; // @[FSECompressorDicBuilder.scala:285:48, :295:42] wire _GEN_69 = ll_count_12 <= ll_lowThreshold; // @[FSECompressorDicBuilder.scala:169:25, :260:29, :286:49] wire _ll_normalizedCounter_12_T_1; // @[FSECompressorDicBuilder.scala:286:49] assign _ll_normalizedCounter_12_T_1 = _GEN_69; // @[FSECompressorDicBuilder.scala:286:49] wire _ll_smallOrEqToLowThresholdCount_T_36; // @[FSECompressorDicBuilder.scala:291:13] assign _ll_smallOrEqToLowThresholdCount_T_36 = _GEN_69; // @[FSECompressorDicBuilder.scala:286:49, :291:13] wire _ll_largerThanLowThresholdProbaSum_T_75; // @[FSECompressorDicBuilder.scala:295:61] assign _ll_largerThanLowThresholdProbaSum_T_75 = _GEN_69; // @[FSECompressorDicBuilder.scala:286:49, :295:61] wire [15:0] _ll_normalizedCounter_12_T_2 = _ll_normalizedCounter_12_T_1 ? ll_lowProbCount : ll_proba_12; // @[FSECompressorDicBuilder.scala:249:29, :265:26, :286:{36,49}] assign _ll_normalizedCounter_12_T_3 = _ll_normalizedCounter_12_T ? 16'h0 : _ll_normalizedCounter_12_T_2; // @[FSECompressorDicBuilder.scala:285:{35,48}, :286:36] assign ll_normalizedCounter_12 = _ll_normalizedCounter_12_T_3; // @[FSECompressorDicBuilder.scala:277:38, :285:35] wire _ll_smallOrEqToLowThresholdCount_T_1 = |ll_count_0; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_2 = _ll_smallOrEqToLowThresholdCount_T & _ll_smallOrEqToLowThresholdCount_T_1; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_4 = |ll_count_1; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_5 = _ll_smallOrEqToLowThresholdCount_T_3 & _ll_smallOrEqToLowThresholdCount_T_4; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_7 = |ll_count_2; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_8 = _ll_smallOrEqToLowThresholdCount_T_6 & _ll_smallOrEqToLowThresholdCount_T_7; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_10 = |ll_count_3; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_11 = _ll_smallOrEqToLowThresholdCount_T_9 & _ll_smallOrEqToLowThresholdCount_T_10; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_13 = |ll_count_4; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_14 = _ll_smallOrEqToLowThresholdCount_T_12 & _ll_smallOrEqToLowThresholdCount_T_13; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_16 = |ll_count_5; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_17 = _ll_smallOrEqToLowThresholdCount_T_15 & _ll_smallOrEqToLowThresholdCount_T_16; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_19 = |ll_count_6; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_20 = _ll_smallOrEqToLowThresholdCount_T_18 & _ll_smallOrEqToLowThresholdCount_T_19; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_22 = |ll_count_7; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_23 = _ll_smallOrEqToLowThresholdCount_T_21 & _ll_smallOrEqToLowThresholdCount_T_22; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_25 = |ll_count_8; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_26 = _ll_smallOrEqToLowThresholdCount_T_24 & _ll_smallOrEqToLowThresholdCount_T_25; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_28 = |ll_count_9; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_29 = _ll_smallOrEqToLowThresholdCount_T_27 & _ll_smallOrEqToLowThresholdCount_T_28; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_31 = |ll_count_10; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_32 = _ll_smallOrEqToLowThresholdCount_T_30 & _ll_smallOrEqToLowThresholdCount_T_31; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_34 = |ll_count_11; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_35 = _ll_smallOrEqToLowThresholdCount_T_33 & _ll_smallOrEqToLowThresholdCount_T_34; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire _ll_smallOrEqToLowThresholdCount_T_37 = |ll_count_12; // @[FSECompressorDicBuilder.scala:169:25, :291:43] wire _ll_smallOrEqToLowThresholdCount_T_38 = _ll_smallOrEqToLowThresholdCount_T_36 & _ll_smallOrEqToLowThresholdCount_T_37; // @[FSECompressorDicBuilder.scala:291:{13,33,43}] wire [1:0] _ll_smallOrEqToLowThresholdCount_T_39 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_2} + {1'h0, _ll_smallOrEqToLowThresholdCount_T_5}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [2:0] _ll_smallOrEqToLowThresholdCount_T_40 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_39} + {2'h0, _ll_smallOrEqToLowThresholdCount_T_8}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [3:0] _ll_smallOrEqToLowThresholdCount_T_41 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_40} + {3'h0, _ll_smallOrEqToLowThresholdCount_T_11}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [4:0] _ll_smallOrEqToLowThresholdCount_T_42 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_41} + {4'h0, _ll_smallOrEqToLowThresholdCount_T_14}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [5:0] _ll_smallOrEqToLowThresholdCount_T_43 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_42} + {5'h0, _ll_smallOrEqToLowThresholdCount_T_17}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [6:0] _ll_smallOrEqToLowThresholdCount_T_44 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_43} + {6'h0, _ll_smallOrEqToLowThresholdCount_T_20}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [7:0] _ll_smallOrEqToLowThresholdCount_T_45 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_44} + {7'h0, _ll_smallOrEqToLowThresholdCount_T_23}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [8:0] _ll_smallOrEqToLowThresholdCount_T_46 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_45} + {8'h0, _ll_smallOrEqToLowThresholdCount_T_26}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [9:0] _ll_smallOrEqToLowThresholdCount_T_47 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_46} + {9'h0, _ll_smallOrEqToLowThresholdCount_T_29}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [10:0] _ll_smallOrEqToLowThresholdCount_T_48 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_47} + {10'h0, _ll_smallOrEqToLowThresholdCount_T_32}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [11:0] _ll_smallOrEqToLowThresholdCount_T_49 = {1'h0, _ll_smallOrEqToLowThresholdCount_T_48} + {11'h0, _ll_smallOrEqToLowThresholdCount_T_35}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire [12:0] ll_smallOrEqToLowThresholdCount = {1'h0, _ll_smallOrEqToLowThresholdCount_T_49} + {12'h0, _ll_smallOrEqToLowThresholdCount_T_38}; // @[FSECompressorDicBuilder.scala:291:33, :292:14] wire _ll_largerThanLowThresholdProbaSum_T_2 = _ll_largerThanLowThresholdProbaSum_T | _ll_largerThanLowThresholdProbaSum_T_1; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_4 = _ll_largerThanLowThresholdProbaSum_T_2 | _ll_largerThanLowThresholdProbaSum_T_3; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_5 = _ll_largerThanLowThresholdProbaSum_T_4 ? 16'h0 : ll_proba_0; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_8 = _ll_largerThanLowThresholdProbaSum_T_6 | _ll_largerThanLowThresholdProbaSum_T_7; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_10 = _ll_largerThanLowThresholdProbaSum_T_8 | _ll_largerThanLowThresholdProbaSum_T_9; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_11 = _ll_largerThanLowThresholdProbaSum_T_10 ? 16'h0 : ll_proba_1; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_14 = _ll_largerThanLowThresholdProbaSum_T_12 | _ll_largerThanLowThresholdProbaSum_T_13; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_16 = _ll_largerThanLowThresholdProbaSum_T_14 | _ll_largerThanLowThresholdProbaSum_T_15; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_17 = _ll_largerThanLowThresholdProbaSum_T_16 ? 16'h0 : ll_proba_2; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_20 = _ll_largerThanLowThresholdProbaSum_T_18 | _ll_largerThanLowThresholdProbaSum_T_19; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_22 = _ll_largerThanLowThresholdProbaSum_T_20 | _ll_largerThanLowThresholdProbaSum_T_21; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_23 = _ll_largerThanLowThresholdProbaSum_T_22 ? 16'h0 : ll_proba_3; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_26 = _ll_largerThanLowThresholdProbaSum_T_24 | _ll_largerThanLowThresholdProbaSum_T_25; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_28 = _ll_largerThanLowThresholdProbaSum_T_26 | _ll_largerThanLowThresholdProbaSum_T_27; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_29 = _ll_largerThanLowThresholdProbaSum_T_28 ? 16'h0 : ll_proba_4; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_32 = _ll_largerThanLowThresholdProbaSum_T_30 | _ll_largerThanLowThresholdProbaSum_T_31; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_34 = _ll_largerThanLowThresholdProbaSum_T_32 | _ll_largerThanLowThresholdProbaSum_T_33; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_35 = _ll_largerThanLowThresholdProbaSum_T_34 ? 16'h0 : ll_proba_5; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_38 = _ll_largerThanLowThresholdProbaSum_T_36 | _ll_largerThanLowThresholdProbaSum_T_37; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_40 = _ll_largerThanLowThresholdProbaSum_T_38 | _ll_largerThanLowThresholdProbaSum_T_39; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_41 = _ll_largerThanLowThresholdProbaSum_T_40 ? 16'h0 : ll_proba_6; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_44 = _ll_largerThanLowThresholdProbaSum_T_42 | _ll_largerThanLowThresholdProbaSum_T_43; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_46 = _ll_largerThanLowThresholdProbaSum_T_44 | _ll_largerThanLowThresholdProbaSum_T_45; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_47 = _ll_largerThanLowThresholdProbaSum_T_46 ? 16'h0 : ll_proba_7; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_50 = _ll_largerThanLowThresholdProbaSum_T_48 | _ll_largerThanLowThresholdProbaSum_T_49; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_52 = _ll_largerThanLowThresholdProbaSum_T_50 | _ll_largerThanLowThresholdProbaSum_T_51; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_53 = _ll_largerThanLowThresholdProbaSum_T_52 ? 16'h0 : ll_proba_8; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_56 = _ll_largerThanLowThresholdProbaSum_T_54 | _ll_largerThanLowThresholdProbaSum_T_55; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_58 = _ll_largerThanLowThresholdProbaSum_T_56 | _ll_largerThanLowThresholdProbaSum_T_57; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_59 = _ll_largerThanLowThresholdProbaSum_T_58 ? 16'h0 : ll_proba_9; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_62 = _ll_largerThanLowThresholdProbaSum_T_60 | _ll_largerThanLowThresholdProbaSum_T_61; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_64 = _ll_largerThanLowThresholdProbaSum_T_62 | _ll_largerThanLowThresholdProbaSum_T_63; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_65 = _ll_largerThanLowThresholdProbaSum_T_64 ? 16'h0 : ll_proba_10; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_68 = _ll_largerThanLowThresholdProbaSum_T_66 | _ll_largerThanLowThresholdProbaSum_T_67; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_70 = _ll_largerThanLowThresholdProbaSum_T_68 | _ll_largerThanLowThresholdProbaSum_T_69; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_71 = _ll_largerThanLowThresholdProbaSum_T_70 ? 16'h0 : ll_proba_11; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire _ll_largerThanLowThresholdProbaSum_T_74 = _ll_largerThanLowThresholdProbaSum_T_72 | _ll_largerThanLowThresholdProbaSum_T_73; // @[FSECompressorDicBuilder.scala:295:{16,32,42}] wire _ll_largerThanLowThresholdProbaSum_T_76 = _ll_largerThanLowThresholdProbaSum_T_74 | _ll_largerThanLowThresholdProbaSum_T_75; // @[FSECompressorDicBuilder.scala:295:{32,51,61}] wire [15:0] _ll_largerThanLowThresholdProbaSum_T_77 = _ll_largerThanLowThresholdProbaSum_T_76 ? 16'h0 : ll_proba_12; // @[FSECompressorDicBuilder.scala:265:26, :295:{8,51}] wire [16:0] _ll_largerThanLowThresholdProbaSum_T_78 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_5} + {1'h0, _ll_largerThanLowThresholdProbaSum_T_11}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [17:0] _ll_largerThanLowThresholdProbaSum_T_79 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_78} + {2'h0, _ll_largerThanLowThresholdProbaSum_T_17}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [18:0] _ll_largerThanLowThresholdProbaSum_T_80 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_79} + {3'h0, _ll_largerThanLowThresholdProbaSum_T_23}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [19:0] _ll_largerThanLowThresholdProbaSum_T_81 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_80} + {4'h0, _ll_largerThanLowThresholdProbaSum_T_29}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [20:0] _ll_largerThanLowThresholdProbaSum_T_82 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_81} + {5'h0, _ll_largerThanLowThresholdProbaSum_T_35}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [21:0] _ll_largerThanLowThresholdProbaSum_T_83 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_82} + {6'h0, _ll_largerThanLowThresholdProbaSum_T_41}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [22:0] _ll_largerThanLowThresholdProbaSum_T_84 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_83} + {7'h0, _ll_largerThanLowThresholdProbaSum_T_47}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [23:0] _ll_largerThanLowThresholdProbaSum_T_85 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_84} + {8'h0, _ll_largerThanLowThresholdProbaSum_T_53}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [24:0] _ll_largerThanLowThresholdProbaSum_T_86 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_85} + {9'h0, _ll_largerThanLowThresholdProbaSum_T_59}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [25:0] _ll_largerThanLowThresholdProbaSum_T_87 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_86} + {10'h0, _ll_largerThanLowThresholdProbaSum_T_65}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [26:0] _ll_largerThanLowThresholdProbaSum_T_88 = {1'h0, _ll_largerThanLowThresholdProbaSum_T_87} + {11'h0, _ll_largerThanLowThresholdProbaSum_T_71}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire [27:0] ll_largerThanLowThresholdProbaSum = {1'h0, _ll_largerThanLowThresholdProbaSum_T_88} + {12'h0, _ll_largerThanLowThresholdProbaSum_T_77}; // @[FSECompressorDicBuilder.scala:295:8, :298:14] wire _ll_normalizedCounterMax_T = ll_normalizedCounter_3 > ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_1 = _ll_normalizedCounterMax_T ? ll_normalizedCounter_3 : ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_2 = ll_normalizedCounter_5 > ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_3 = _ll_normalizedCounterMax_T_2 ? ll_normalizedCounter_5 : ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_4 = ll_normalizedCounter_7 > ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_5 = _ll_normalizedCounterMax_T_4 ? ll_normalizedCounter_7 : ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_6 = ll_normalizedCounter_9 > ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_7 = _ll_normalizedCounterMax_T_6 ? ll_normalizedCounter_9 : ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_8 = ll_normalizedCounter_11 > ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_9 = _ll_normalizedCounterMax_T_8 ? ll_normalizedCounter_11 : ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_10 = ll_normalizedCounter_0 > ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :300:81] wire [15:0] _ll_normalizedCounterMax_T_11 = _ll_normalizedCounterMax_T_10 ? ll_normalizedCounter_0 : ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_12 = ll_normalizedCounter_2 > _ll_normalizedCounterMax_T_1; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_13 = _ll_normalizedCounterMax_T_12 ? ll_normalizedCounter_2 : _ll_normalizedCounterMax_T_1; // @[FSECompressorDicBuilder.scala:277:38, :300:{78,81}] wire _ll_normalizedCounterMax_T_14 = _ll_normalizedCounterMax_T_3 > _ll_normalizedCounterMax_T_5; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_15 = _ll_normalizedCounterMax_T_14 ? _ll_normalizedCounterMax_T_3 : _ll_normalizedCounterMax_T_5; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_16 = _ll_normalizedCounterMax_T_7 > _ll_normalizedCounterMax_T_9; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_17 = _ll_normalizedCounterMax_T_16 ? _ll_normalizedCounterMax_T_7 : _ll_normalizedCounterMax_T_9; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_18 = _ll_normalizedCounterMax_T_11 > _ll_normalizedCounterMax_T_13; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_19 = _ll_normalizedCounterMax_T_18 ? _ll_normalizedCounterMax_T_11 : _ll_normalizedCounterMax_T_13; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_20 = _ll_normalizedCounterMax_T_15 > _ll_normalizedCounterMax_T_17; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] _ll_normalizedCounterMax_T_21 = _ll_normalizedCounterMax_T_20 ? _ll_normalizedCounterMax_T_15 : _ll_normalizedCounterMax_T_17; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _ll_normalizedCounterMax_T_22 = _ll_normalizedCounterMax_T_19 > _ll_normalizedCounterMax_T_21; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire [15:0] ll_normalizedCounterMax = _ll_normalizedCounterMax_T_22 ? _ll_normalizedCounterMax_T_19 : _ll_normalizedCounterMax_T_21; // @[FSECompressorDicBuilder.scala:300:{78,81}] wire _GEN_70 = ll_normalizedCounter_0 < ll_normalizedCounter_1; // @[FSECompressorDicBuilder.scala:277:38, :307:15] wire _ll_normalizedCounterMaxIdx_T; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T = _GEN_70; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_2; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_2 = _GEN_70; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_1 = _ll_normalizedCounterMaxIdx_T ? ll_normalizedCounter_1 : ll_normalizedCounter_0; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_3 = {15'h0, _ll_normalizedCounterMaxIdx_T_2}; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_71 = _ll_normalizedCounterMaxIdx_T_1 < ll_normalizedCounter_2; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_4; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_4 = _GEN_71; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_6; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_6 = _GEN_71; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_5 = _ll_normalizedCounterMaxIdx_T_4 ? ll_normalizedCounter_2 : _ll_normalizedCounterMaxIdx_T_1; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_7 = _ll_normalizedCounterMaxIdx_T_6 ? 16'h2 : _ll_normalizedCounterMaxIdx_T_3; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_72 = _ll_normalizedCounterMaxIdx_T_5 < ll_normalizedCounter_3; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_8; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_8 = _GEN_72; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_10; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_10 = _GEN_72; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_9 = _ll_normalizedCounterMaxIdx_T_8 ? ll_normalizedCounter_3 : _ll_normalizedCounterMaxIdx_T_5; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_11 = _ll_normalizedCounterMaxIdx_T_10 ? 16'h3 : _ll_normalizedCounterMaxIdx_T_7; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_73 = _ll_normalizedCounterMaxIdx_T_9 < ll_normalizedCounter_4; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_12; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_12 = _GEN_73; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_14; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_14 = _GEN_73; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_13 = _ll_normalizedCounterMaxIdx_T_12 ? ll_normalizedCounter_4 : _ll_normalizedCounterMaxIdx_T_9; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_15 = _ll_normalizedCounterMaxIdx_T_14 ? 16'h4 : _ll_normalizedCounterMaxIdx_T_11; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_74 = _ll_normalizedCounterMaxIdx_T_13 < ll_normalizedCounter_5; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_16; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_16 = _GEN_74; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_18; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_18 = _GEN_74; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_17 = _ll_normalizedCounterMaxIdx_T_16 ? ll_normalizedCounter_5 : _ll_normalizedCounterMaxIdx_T_13; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_19 = _ll_normalizedCounterMaxIdx_T_18 ? 16'h5 : _ll_normalizedCounterMaxIdx_T_15; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_75 = _ll_normalizedCounterMaxIdx_T_17 < ll_normalizedCounter_6; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_20; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_20 = _GEN_75; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_22; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_22 = _GEN_75; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_21 = _ll_normalizedCounterMaxIdx_T_20 ? ll_normalizedCounter_6 : _ll_normalizedCounterMaxIdx_T_17; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_23 = _ll_normalizedCounterMaxIdx_T_22 ? 16'h6 : _ll_normalizedCounterMaxIdx_T_19; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_76 = _ll_normalizedCounterMaxIdx_T_21 < ll_normalizedCounter_7; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_24; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_24 = _GEN_76; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_26; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_26 = _GEN_76; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_25 = _ll_normalizedCounterMaxIdx_T_24 ? ll_normalizedCounter_7 : _ll_normalizedCounterMaxIdx_T_21; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_27 = _ll_normalizedCounterMaxIdx_T_26 ? 16'h7 : _ll_normalizedCounterMaxIdx_T_23; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_77 = _ll_normalizedCounterMaxIdx_T_25 < ll_normalizedCounter_8; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_28; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_28 = _GEN_77; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_30; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_30 = _GEN_77; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_29 = _ll_normalizedCounterMaxIdx_T_28 ? ll_normalizedCounter_8 : _ll_normalizedCounterMaxIdx_T_25; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_31 = _ll_normalizedCounterMaxIdx_T_30 ? 16'h8 : _ll_normalizedCounterMaxIdx_T_27; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_78 = _ll_normalizedCounterMaxIdx_T_29 < ll_normalizedCounter_9; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_32; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_32 = _GEN_78; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_34; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_34 = _GEN_78; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_33 = _ll_normalizedCounterMaxIdx_T_32 ? ll_normalizedCounter_9 : _ll_normalizedCounterMaxIdx_T_29; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_35 = _ll_normalizedCounterMaxIdx_T_34 ? 16'h9 : _ll_normalizedCounterMaxIdx_T_31; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_79 = _ll_normalizedCounterMaxIdx_T_33 < ll_normalizedCounter_10; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_36; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_36 = _GEN_79; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_38; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_38 = _GEN_79; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_37 = _ll_normalizedCounterMaxIdx_T_36 ? ll_normalizedCounter_10 : _ll_normalizedCounterMaxIdx_T_33; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_39 = _ll_normalizedCounterMaxIdx_T_38 ? 16'hA : _ll_normalizedCounterMaxIdx_T_35; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_80 = _ll_normalizedCounterMaxIdx_T_37 < ll_normalizedCounter_11; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_40; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_40 = _GEN_80; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_42; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_42 = _GEN_80; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_41 = _ll_normalizedCounterMaxIdx_T_40 ? ll_normalizedCounter_11 : _ll_normalizedCounterMaxIdx_T_37; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] _ll_normalizedCounterMaxIdx_T_43 = _ll_normalizedCounterMaxIdx_T_42 ? 16'hB : _ll_normalizedCounterMaxIdx_T_39; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire _GEN_81 = _ll_normalizedCounterMaxIdx_T_41 < ll_normalizedCounter_12; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire _ll_normalizedCounterMaxIdx_T_44; // @[FSECompressorDicBuilder.scala:307:15] assign _ll_normalizedCounterMaxIdx_T_44 = _GEN_81; // @[FSECompressorDicBuilder.scala:307:15] wire _ll_normalizedCounterMaxIdx_T_46; // @[FSECompressorDicBuilder.scala:307:45] assign _ll_normalizedCounterMaxIdx_T_46 = _GEN_81; // @[FSECompressorDicBuilder.scala:307:{15,45}] wire [15:0] _ll_normalizedCounterMaxIdx_T_45 = _ll_normalizedCounterMaxIdx_T_44 ? ll_normalizedCounter_12 : _ll_normalizedCounterMaxIdx_T_41; // @[FSECompressorDicBuilder.scala:277:38, :307:{9,15}] wire [15:0] ll_normalizedCounterMaxIdx = _ll_normalizedCounterMaxIdx_T_46 ? 16'hC : _ll_normalizedCounterMaxIdx_T_43; // @[FSECompressorDicBuilder.scala:307:{39,45}] wire [28:0] _ll_nxtStillToDistribute_T = 29'h40 - {1'h0, ll_largerThanLowThresholdProbaSum}; // @[FSECompressorDicBuilder.scala:298:14, :310:57] wire [27:0] _ll_nxtStillToDistribute_T_1 = _ll_nxtStillToDistribute_T[27:0]; // @[FSECompressorDicBuilder.scala:310:57] wire [28:0] _ll_nxtStillToDistribute_T_2 = {1'h0, _ll_nxtStillToDistribute_T_1} - {16'h0, ll_smallOrEqToLowThresholdCount}; // @[FSECompressorDicBuilder.scala:292:14, :310:{57,93}] wire [27:0] _ll_nxtStillToDistribute_T_3 = _ll_nxtStillToDistribute_T_2[27:0]; // @[FSECompressorDicBuilder.scala:310:93] wire [27:0] ll_nxtStillToDistribute = _ll_nxtStillToDistribute_T_3; // @[FSECompressorDicBuilder.scala:310:{93,128}] wire [28:0] _GEN_82 = {ll_nxtStillToDistribute[27], ll_nxtStillToDistribute}; // @[FSECompressorDicBuilder.scala:310:128, :311:43] wire [28:0] ll_negNxtStillToDistribute = _GEN_82 * 29'h1FFFFFFF; // @[FSECompressorDicBuilder.scala:311:43] wire [15:0] _fse_normalize_corner_case_T = {1'h0, ll_normalizedCounterMax[15:1]}; // @[FSECompressorDicBuilder.scala:300:78, :313:90] wire [15:0] _fse_normalize_corner_case_T_1 = _fse_normalize_corner_case_T; // @[FSECompressorDicBuilder.scala:313:{90,98}] wire fse_normalize_corner_case = $signed(ll_negNxtStillToDistribute) >= $signed({{13{_fse_normalize_corner_case_T_1[15]}}, _fse_normalize_corner_case_T_1}); // @[FSECompressorDicBuilder.scala:311:43, :313:{62,98}] reg fse_normalize_corner_case_reg; // @[FSECompressorDicBuilder.scala:314:46] wire _T_390 = dicBuilderState == 4'h2; // @[FSECompressorDicBuilder.scala:156:32, :316:25] wire _T_3 = _T_390 & _predefined_mode_q_io_enq_ready; // @[FSECompressorDicBuilder.scala:141:33, :316:{25,45}] wire [28:0] _ll_ncountSumStill2Dist_T_1 = {{13{_ll_ncountSumStill2Dist_T[15]}}, _ll_ncountSumStill2Dist_T} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_2 = _ll_ncountSumStill2Dist_T_1[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_3 = _ll_ncountSumStill2Dist_T_2; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist = _ll_ncountSumStill2Dist_T_3; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_0_T = ll_normalizedCounterMaxIdx == 16'h0; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_0_T_1 = _ll_normalizedCounterMaxAdjusted_0_T ? ll_ncountSumStill2Dist : {12'h0, ll_normalizedCounter_0}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_0 = _T_3 ? _ll_normalizedCounterMaxAdjusted_0_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_5 = {{13{_ll_ncountSumStill2Dist_T_4[15]}}, _ll_ncountSumStill2Dist_T_4} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_6 = _ll_ncountSumStill2Dist_T_5[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_7 = _ll_ncountSumStill2Dist_T_6; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_1 = _ll_ncountSumStill2Dist_T_7; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_1_T = ll_normalizedCounterMaxIdx == 16'h1; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_1_T_1 = _ll_normalizedCounterMaxAdjusted_1_T ? ll_ncountSumStill2Dist_1 : {12'h0, ll_normalizedCounter_1}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_1 = _T_3 ? _ll_normalizedCounterMaxAdjusted_1_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_9 = {{13{_ll_ncountSumStill2Dist_T_8[15]}}, _ll_ncountSumStill2Dist_T_8} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_10 = _ll_ncountSumStill2Dist_T_9[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_11 = _ll_ncountSumStill2Dist_T_10; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_2 = _ll_ncountSumStill2Dist_T_11; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_2_T = ll_normalizedCounterMaxIdx == 16'h2; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_2_T_1 = _ll_normalizedCounterMaxAdjusted_2_T ? ll_ncountSumStill2Dist_2 : {12'h0, ll_normalizedCounter_2}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_2 = _T_3 ? _ll_normalizedCounterMaxAdjusted_2_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_13 = {{13{_ll_ncountSumStill2Dist_T_12[15]}}, _ll_ncountSumStill2Dist_T_12} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_14 = _ll_ncountSumStill2Dist_T_13[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_15 = _ll_ncountSumStill2Dist_T_14; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_3 = _ll_ncountSumStill2Dist_T_15; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_3_T = ll_normalizedCounterMaxIdx == 16'h3; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_3_T_1 = _ll_normalizedCounterMaxAdjusted_3_T ? ll_ncountSumStill2Dist_3 : {12'h0, ll_normalizedCounter_3}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_3 = _T_3 ? _ll_normalizedCounterMaxAdjusted_3_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_17 = {{13{_ll_ncountSumStill2Dist_T_16[15]}}, _ll_ncountSumStill2Dist_T_16} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_18 = _ll_ncountSumStill2Dist_T_17[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_19 = _ll_ncountSumStill2Dist_T_18; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_4 = _ll_ncountSumStill2Dist_T_19; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_4_T = ll_normalizedCounterMaxIdx == 16'h4; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_4_T_1 = _ll_normalizedCounterMaxAdjusted_4_T ? ll_ncountSumStill2Dist_4 : {12'h0, ll_normalizedCounter_4}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_4 = _T_3 ? _ll_normalizedCounterMaxAdjusted_4_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_21 = {{13{_ll_ncountSumStill2Dist_T_20[15]}}, _ll_ncountSumStill2Dist_T_20} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_22 = _ll_ncountSumStill2Dist_T_21[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_23 = _ll_ncountSumStill2Dist_T_22; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_5 = _ll_ncountSumStill2Dist_T_23; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_5_T = ll_normalizedCounterMaxIdx == 16'h5; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_5_T_1 = _ll_normalizedCounterMaxAdjusted_5_T ? ll_ncountSumStill2Dist_5 : {12'h0, ll_normalizedCounter_5}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_5 = _T_3 ? _ll_normalizedCounterMaxAdjusted_5_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_25 = {{13{_ll_ncountSumStill2Dist_T_24[15]}}, _ll_ncountSumStill2Dist_T_24} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_26 = _ll_ncountSumStill2Dist_T_25[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_27 = _ll_ncountSumStill2Dist_T_26; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_6 = _ll_ncountSumStill2Dist_T_27; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_6_T = ll_normalizedCounterMaxIdx == 16'h6; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_6_T_1 = _ll_normalizedCounterMaxAdjusted_6_T ? ll_ncountSumStill2Dist_6 : {12'h0, ll_normalizedCounter_6}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_6 = _T_3 ? _ll_normalizedCounterMaxAdjusted_6_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_29 = {{13{_ll_ncountSumStill2Dist_T_28[15]}}, _ll_ncountSumStill2Dist_T_28} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_30 = _ll_ncountSumStill2Dist_T_29[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_31 = _ll_ncountSumStill2Dist_T_30; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_7 = _ll_ncountSumStill2Dist_T_31; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_7_T = ll_normalizedCounterMaxIdx == 16'h7; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_7_T_1 = _ll_normalizedCounterMaxAdjusted_7_T ? ll_ncountSumStill2Dist_7 : {12'h0, ll_normalizedCounter_7}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_7 = _T_3 ? _ll_normalizedCounterMaxAdjusted_7_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_33 = {{13{_ll_ncountSumStill2Dist_T_32[15]}}, _ll_ncountSumStill2Dist_T_32} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_34 = _ll_ncountSumStill2Dist_T_33[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_35 = _ll_ncountSumStill2Dist_T_34; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_8 = _ll_ncountSumStill2Dist_T_35; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_8_T = ll_normalizedCounterMaxIdx == 16'h8; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_8_T_1 = _ll_normalizedCounterMaxAdjusted_8_T ? ll_ncountSumStill2Dist_8 : {12'h0, ll_normalizedCounter_8}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_8 = _T_3 ? _ll_normalizedCounterMaxAdjusted_8_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_37 = {{13{_ll_ncountSumStill2Dist_T_36[15]}}, _ll_ncountSumStill2Dist_T_36} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_38 = _ll_ncountSumStill2Dist_T_37[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_39 = _ll_ncountSumStill2Dist_T_38; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_9 = _ll_ncountSumStill2Dist_T_39; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_9_T = ll_normalizedCounterMaxIdx == 16'h9; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_9_T_1 = _ll_normalizedCounterMaxAdjusted_9_T ? ll_ncountSumStill2Dist_9 : {12'h0, ll_normalizedCounter_9}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_9 = _T_3 ? _ll_normalizedCounterMaxAdjusted_9_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_41 = {{13{_ll_ncountSumStill2Dist_T_40[15]}}, _ll_ncountSumStill2Dist_T_40} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_42 = _ll_ncountSumStill2Dist_T_41[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_43 = _ll_ncountSumStill2Dist_T_42; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_10 = _ll_ncountSumStill2Dist_T_43; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_10_T = ll_normalizedCounterMaxIdx == 16'hA; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_10_T_1 = _ll_normalizedCounterMaxAdjusted_10_T ? ll_ncountSumStill2Dist_10 : {12'h0, ll_normalizedCounter_10}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_10 = _T_3 ? _ll_normalizedCounterMaxAdjusted_10_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_45 = {{13{_ll_ncountSumStill2Dist_T_44[15]}}, _ll_ncountSumStill2Dist_T_44} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_46 = _ll_ncountSumStill2Dist_T_45[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_47 = _ll_ncountSumStill2Dist_T_46; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_11 = _ll_ncountSumStill2Dist_T_47; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_11_T = ll_normalizedCounterMaxIdx == 16'hB; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_11_T_1 = _ll_normalizedCounterMaxAdjusted_11_T ? ll_ncountSumStill2Dist_11 : {12'h0, ll_normalizedCounter_11}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_11 = _T_3 ? _ll_normalizedCounterMaxAdjusted_11_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] wire [28:0] _ll_ncountSumStill2Dist_T_49 = {{13{_ll_ncountSumStill2Dist_T_48[15]}}, _ll_ncountSumStill2Dist_T_48} + _GEN_82; // @[FSECompressorDicBuilder.scala:311:43, :320:{61,68}] wire [27:0] _ll_ncountSumStill2Dist_T_50 = _ll_ncountSumStill2Dist_T_49[27:0]; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] _ll_ncountSumStill2Dist_T_51 = _ll_ncountSumStill2Dist_T_50; // @[FSECompressorDicBuilder.scala:320:68] wire [27:0] ll_ncountSumStill2Dist_12 = _ll_ncountSumStill2Dist_T_51; // @[FSECompressorDicBuilder.scala:320:{68,95}] wire _ll_normalizedCounterMaxAdjusted_12_T = ll_normalizedCounterMaxIdx == 16'hC; // @[FSECompressorDicBuilder.scala:307:39, :322:53] wire [27:0] _ll_normalizedCounterMaxAdjusted_12_T_1 = _ll_normalizedCounterMaxAdjusted_12_T ? ll_ncountSumStill2Dist_12 : {12'h0, ll_normalizedCounter_12}; // @[FSECompressorDicBuilder.scala:277:38, :320:95, :322:{48,53}] assign ll_normalizedCounterMaxAdjusted_12 = _T_3 ? _ll_normalizedCounterMaxAdjusted_12_T_1[15:0] : 16'h0; // @[FSECompressorDicBuilder.scala:278:49, :316:{45,80}, :322:{42,48}] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [15:0] ll_normalizedCounterReg_0; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_1; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_2; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_3; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_4; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_5; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_6; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_7; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_8; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_9; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_10; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_11; // @[FSECompressorDicBuilder.scala:337:40] reg [15:0] ll_normalizedCounterReg_12; // @[FSECompressorDicBuilder.scala:337:40] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_45; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_90 = {1'h0, loginfo_cycles_45} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_91 = _loginfo_cycles_T_90[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_46; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_92 = {1'h0, loginfo_cycles_46} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_93 = _loginfo_cycles_T_92[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_47; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_94 = {1'h0, loginfo_cycles_47} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_95 = _loginfo_cycles_T_94[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_48; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_96 = {1'h0, loginfo_cycles_48} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_97 = _loginfo_cycles_T_96[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_49; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_98 = {1'h0, loginfo_cycles_49} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_99 = _loginfo_cycles_T_98[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_50; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_100 = {1'h0, loginfo_cycles_50} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_101 = _loginfo_cycles_T_100[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_51; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_102 = {1'h0, loginfo_cycles_51} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_103 = _loginfo_cycles_T_102[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_52; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_104 = {1'h0, loginfo_cycles_52} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_105 = _loginfo_cycles_T_104[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_53; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_106 = {1'h0, loginfo_cycles_53} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_107 = _loginfo_cycles_T_106[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_54; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_108 = {1'h0, loginfo_cycles_54} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_109 = _loginfo_cycles_T_108[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_55; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_110 = {1'h0, loginfo_cycles_55} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_111 = _loginfo_cycles_T_110[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_56; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_112 = {1'h0, loginfo_cycles_56} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_113 = _loginfo_cycles_T_112[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_57; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_114 = {1'h0, loginfo_cycles_57} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_115 = _loginfo_cycles_T_114[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_58; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_116 = {1'h0, loginfo_cycles_58} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_117 = _loginfo_cycles_T_116[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_59; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_118 = {1'h0, loginfo_cycles_59} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_119 = _loginfo_cycles_T_118[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_60; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_120 = {1'h0, loginfo_cycles_60} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_121 = _loginfo_cycles_T_120[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_61; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_122 = {1'h0, loginfo_cycles_61} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_123 = _loginfo_cycles_T_122[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_62; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_124 = {1'h0, loginfo_cycles_62} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_125 = _loginfo_cycles_T_124[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_63; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_126 = {1'h0, loginfo_cycles_63} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_127 = _loginfo_cycles_T_126[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_64; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_128 = {1'h0, loginfo_cycles_64} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_129 = _loginfo_cycles_T_128[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_65; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_130 = {1'h0, loginfo_cycles_65} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_131 = _loginfo_cycles_T_130[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_66; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_132 = {1'h0, loginfo_cycles_66} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_133 = _loginfo_cycles_T_132[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_67; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_134 = {1'h0, loginfo_cycles_67} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_135 = _loginfo_cycles_T_134[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_68; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_136 = {1'h0, loginfo_cycles_68} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_137 = _loginfo_cycles_T_136[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_69; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_138 = {1'h0, loginfo_cycles_69} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_139 = _loginfo_cycles_T_138[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_70; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_140 = {1'h0, loginfo_cycles_70} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_141 = _loginfo_cycles_T_140[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_71; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_142 = {1'h0, loginfo_cycles_71} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_143 = _loginfo_cycles_T_142[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_72; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_144 = {1'h0, loginfo_cycles_72} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_145 = _loginfo_cycles_T_144[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_73; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_146 = {1'h0, loginfo_cycles_73} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_147 = _loginfo_cycles_T_146[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_74; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_148 = {1'h0, loginfo_cycles_74} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_149 = _loginfo_cycles_T_148[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_75; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_150 = {1'h0, loginfo_cycles_75} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_151 = _loginfo_cycles_T_150[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_76; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_152 = {1'h0, loginfo_cycles_76} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_153 = _loginfo_cycles_T_152[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_77; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_154 = {1'h0, loginfo_cycles_77} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_155 = _loginfo_cycles_T_154[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_78; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_156 = {1'h0, loginfo_cycles_78} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_157 = _loginfo_cycles_T_156[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_79; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_158 = {1'h0, loginfo_cycles_79} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_159 = _loginfo_cycles_T_158[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_80; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_160 = {1'h0, loginfo_cycles_80} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_161 = _loginfo_cycles_T_160[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_81; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_162 = {1'h0, loginfo_cycles_81} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_163 = _loginfo_cycles_T_162[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_82; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_164 = {1'h0, loginfo_cycles_82} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_165 = _loginfo_cycles_T_164[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_83; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_166 = {1'h0, loginfo_cycles_83} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_167 = _loginfo_cycles_T_166[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_84; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_168 = {1'h0, loginfo_cycles_84} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_169 = _loginfo_cycles_T_168[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_85; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_170 = {1'h0, loginfo_cycles_85} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_171 = _loginfo_cycles_T_170[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_86; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_172 = {1'h0, loginfo_cycles_86} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_173 = _loginfo_cycles_T_172[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_87; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_174 = {1'h0, loginfo_cycles_87} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_175 = _loginfo_cycles_T_174[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_88; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_176 = {1'h0, loginfo_cycles_88} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_177 = _loginfo_cycles_T_176[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_89; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_178 = {1'h0, loginfo_cycles_89} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_179 = _loginfo_cycles_T_178[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_90; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_180 = {1'h0, loginfo_cycles_90} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_181 = _loginfo_cycles_T_180[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_91; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_182 = {1'h0, loginfo_cycles_91} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_183 = _loginfo_cycles_T_182[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_92; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_184 = {1'h0, loginfo_cycles_92} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_185 = _loginfo_cycles_T_184[63:0]; // @[Util.scala:19:38] wire [32:0] _GEN_83 = {1'h0, ll_max_symbol_value} + 33'h1; // @[FSECompressorDicBuilder.scala:170:36, :379:39] wire [32:0] _ll_maxSV1_T; // @[FSECompressorDicBuilder.scala:379:39] assign _ll_maxSV1_T = _GEN_83; // @[FSECompressorDicBuilder.scala:379:39] wire [32:0] _alphabetSize_T; // @[FSECompressorDicBuilder.scala:466:42] assign _alphabetSize_T = _GEN_83; // @[FSECompressorDicBuilder.scala:379:39, :466:42] wire [31:0] ll_maxSV1 = _ll_maxSV1_T[31:0]; // @[FSECompressorDicBuilder.scala:379:39] wire [15:0] ll_cumul_0; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_1; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_2; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_3; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_4; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_5; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_6; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_7; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_8; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_9; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_10; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_11; // @[FSECompressorDicBuilder.scala:382:26] wire [15:0] ll_cumul_12; // @[FSECompressorDicBuilder.scala:382:26] reg [7:0] ll_tableSymbol_0; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_1; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_2; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_3; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_4; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_5; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_6; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_7; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_8; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_9; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_10; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_11; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_12; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_13; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_14; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_15; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_16; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_17; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_18; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_19; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_20; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_21; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_22; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_23; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_24; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_25; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_26; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_27; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_28; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_29; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_30; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_31; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_32; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_33; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_34; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_35; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_36; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_37; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_38; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_39; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_40; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_41; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_42; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_43; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_44; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_45; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_46; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_47; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_48; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_49; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_50; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_51; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_52; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_53; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_54; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_55; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_56; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_57; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_58; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_59; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_60; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_61; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_62; // @[FSECompressorDicBuilder.scala:383:31] reg [7:0] ll_tableSymbol_63; // @[FSECompressorDicBuilder.scala:383:31] wire [7:0] ll_normCountEqsNegOne_0; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_1; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_2; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_3; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_4; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_5; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_6; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_7; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_8; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_9; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_10; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOne_11; // @[FSECompressorDicBuilder.scala:388:39] wire [7:0] ll_normCountEqsNegOneCumul_0; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_1; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_2; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_3; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_4; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_5; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_6; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_7; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_8; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_9; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_10; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_11; // @[FSECompressorDicBuilder.scala:389:44] wire [7:0] ll_normCountEqsNegOneCumul_12; // @[FSECompressorDicBuilder.scala:389:44] wire [8:0] _GEN_84 = {1'h0, ll_normCountEqsNegOne_1}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [8:0] _ll_normCountEqsNegOneSum_T = {1'h0, ll_normCountEqsNegOne_0} + _GEN_84; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [9:0] _ll_normCountEqsNegOneSum_T_1 = {1'h0, _ll_normCountEqsNegOneSum_T} + {2'h0, ll_normCountEqsNegOne_2}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [10:0] _ll_normCountEqsNegOneSum_T_2 = {1'h0, _ll_normCountEqsNegOneSum_T_1} + {3'h0, ll_normCountEqsNegOne_3}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [11:0] _ll_normCountEqsNegOneSum_T_3 = {1'h0, _ll_normCountEqsNegOneSum_T_2} + {4'h0, ll_normCountEqsNegOne_4}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [12:0] _ll_normCountEqsNegOneSum_T_4 = {1'h0, _ll_normCountEqsNegOneSum_T_3} + {5'h0, ll_normCountEqsNegOne_5}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [13:0] _ll_normCountEqsNegOneSum_T_5 = {1'h0, _ll_normCountEqsNegOneSum_T_4} + {6'h0, ll_normCountEqsNegOne_6}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [14:0] _ll_normCountEqsNegOneSum_T_6 = {1'h0, _ll_normCountEqsNegOneSum_T_5} + {7'h0, ll_normCountEqsNegOne_7}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [15:0] _ll_normCountEqsNegOneSum_T_7 = {1'h0, _ll_normCountEqsNegOneSum_T_6} + {8'h0, ll_normCountEqsNegOne_8}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [16:0] _ll_normCountEqsNegOneSum_T_8 = {1'h0, _ll_normCountEqsNegOneSum_T_7} + {9'h0, ll_normCountEqsNegOne_9}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [17:0] _ll_normCountEqsNegOneSum_T_9 = {1'h0, _ll_normCountEqsNegOneSum_T_8} + {10'h0, ll_normCountEqsNegOne_10}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [18:0] _ll_normCountEqsNegOneSum_T_10 = {1'h0, _ll_normCountEqsNegOneSum_T_9} + {11'h0, ll_normCountEqsNegOne_11}; // @[FSECompressorDicBuilder.scala:388:39, :390:65] wire [19:0] ll_normCountEqsNegOneSum = {1'h0, _ll_normCountEqsNegOneSum_T_10}; // @[FSECompressorDicBuilder.scala:390:65] reg [31:0] ll_highThresholdAfterCumul; // @[FSECompressorDicBuilder.scala:392:43] reg [15:0] ll_cumulReg_0; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_1; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_2; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_3; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_4; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_5; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_6; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_7; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_8; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_9; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_10; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_11; // @[FSECompressorDicBuilder.scala:394:28] reg [15:0] ll_cumulReg_12; // @[FSECompressorDicBuilder.scala:394:28] reg [7:0] ll_spread_0; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_1; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_2; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_3; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_4; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_5; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_6; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_7; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_8; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_9; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_10; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_11; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_12; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_13; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_14; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_15; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_16; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_17; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_18; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_19; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_20; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_21; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_22; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_23; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_24; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_25; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_26; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_27; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_28; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_29; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_30; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_31; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_32; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_33; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_34; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_35; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_36; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_37; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_38; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_39; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_40; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_41; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_42; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_43; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_44; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_45; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_46; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_47; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_48; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_49; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_50; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_51; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_52; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_53; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_54; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_55; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_56; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_57; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_58; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_59; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_60; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_61; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_62; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_63; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_64; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_65; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_66; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_67; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_68; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_69; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_70; // @[FSECompressorDicBuilder.scala:400:26] reg [7:0] ll_spread_71; // @[FSECompressorDicBuilder.scala:400:26] reg [63:0] ll_pos; // @[FSECompressorDicBuilder.scala:402:23] reg [63:0] ll_s; // @[FSECompressorDicBuilder.scala:403:21] reg [63:0] ll_sv; // @[FSECompressorDicBuilder.scala:404:22] reg [15:0] ll_tableU16_0; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_1; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_2; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_3; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_4; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_5; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_6; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_7; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_8; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_9; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_10; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_11; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_12; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_13; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_14; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_15; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_16; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_17; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_18; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_19; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_20; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_21; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_22; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_23; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_24; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_25; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_26; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_27; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_28; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_29; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_30; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_31; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_32; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_33; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_34; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_35; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_36; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_37; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_38; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_39; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_40; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_41; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_42; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_43; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_44; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_45; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_46; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_47; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_48; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_49; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_50; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_51; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_52; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_53; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_54; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_55; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_56; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_57; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_58; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_59; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_60; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_61; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_62; // @[FSECompressorDicBuilder.scala:411:28] reg [15:0] ll_tableU16_63; // @[FSECompressorDicBuilder.scala:411:28] reg [31:0] ll_symbolTTDeltaNbBits_0; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_1; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_2; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_3; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_4; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_5; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_6; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_7; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_8; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_9; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_10; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_11; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaNbBits_12; // @[FSECompressorDicBuilder.scala:412:39] reg [31:0] ll_symbolTTDeltaFindState_0; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_1; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_2; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_3; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_4; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_5; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_6; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_7; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_8; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_9; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_10; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_11; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_symbolTTDeltaFindState_12; // @[FSECompressorDicBuilder.scala:413:42] reg [31:0] ll_total; // @[FSECompressorDicBuilder.scala:414:25] wire [31:0] normCount; // @[FSECompressorDicBuilder.scala:415:23] wire [3:0] _normCount_T = ll_s[3:0]; // @[FSECompressorDicBuilder.scala:403:21] wire [3:0] _n_T = ll_s[3:0]; // @[FSECompressorDicBuilder.scala:403:21] wire [15:0][15:0] _GEN_85 = {{ll_normalizedCounterReg_0}, {ll_normalizedCounterReg_0}, {ll_normalizedCounterReg_0}, {ll_normalizedCounterReg_12}, {ll_normalizedCounterReg_11}, {ll_normalizedCounterReg_10}, {ll_normalizedCounterReg_9}, {ll_normalizedCounterReg_8}, {ll_normalizedCounterReg_7}, {ll_normalizedCounterReg_6}, {ll_normalizedCounterReg_5}, {ll_normalizedCounterReg_4}, {ll_normalizedCounterReg_3}, {ll_normalizedCounterReg_2}, {ll_normalizedCounterReg_1}, {ll_normalizedCounterReg_0}}; // @[FSECompressorDicBuilder.scala:337:40, :416:13] assign normCount = {16'h0, _GEN_85[_normCount_T]}; // @[FSECompressorDicBuilder.scala:415:23, :416:13] wire _symbolTT_lookup_fire_and_last_vec_0_T_2; // @[FSECompressorDicBuilder.scala:441:71] wire _symbolTT_lookup_fire_and_last_vec_1_T_2; // @[FSECompressorDicBuilder.scala:441:71] wire symbolTT_lookup_fire_and_last_vec_0; // @[FSECompressorDicBuilder.scala:422:51] wire symbolTT_lookup_fire_and_last_vec_1; // @[FSECompressorDicBuilder.scala:422:51] wire _T_1643 = dicBuilderState == 4'h8; // @[FSECompressorDicBuilder.scala:156:32, :429:23] assign _io_new_state_0_valid_T = _T_1643; // @[FSECompressorDicBuilder.scala:429:23, :438:47] assign _io_new_state_1_valid_T = _T_1643; // @[FSECompressorDicBuilder.scala:429:23, :438:47] wire _io_ll_table_log_valid_T_1; // @[FSECompressorDicBuilder.scala:453:68] assign _io_ll_table_log_valid_T_1 = _T_1643; // @[FSECompressorDicBuilder.scala:429:23, :453:68] assign _io_symbol_info_0_ready_T = io_symbolTT_info_0_ready_0 & _T_1643; // @[Misc.scala:26:53] assign io_symbol_info_0_ready_0 = _io_symbol_info_0_ready_T; // @[Misc.scala:26:53] assign _io_symbolTT_info_0_valid_T = io_symbol_info_0_valid_0 & _T_1643; // @[Misc.scala:26:53] assign io_symbolTT_info_0_valid_0 = _io_symbolTT_info_0_valid_T; // @[Misc.scala:26:53] wire [3:0] _io_symbolTT_info_0_bits_nbbit_T = io_symbol_info_0_bits_symbol_0[3:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [3:0] _io_symbolTT_info_0_bits_findstate_T = io_symbol_info_0_bits_symbol_0[3:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [15:0][31:0] _GEN_86 = {{ll_symbolTTDeltaNbBits_0}, {ll_symbolTTDeltaNbBits_0}, {ll_symbolTTDeltaNbBits_0}, {ll_symbolTTDeltaNbBits_12}, {ll_symbolTTDeltaNbBits_11}, {ll_symbolTTDeltaNbBits_10}, {ll_symbolTTDeltaNbBits_9}, {ll_symbolTTDeltaNbBits_8}, {ll_symbolTTDeltaNbBits_7}, {ll_symbolTTDeltaNbBits_6}, {ll_symbolTTDeltaNbBits_5}, {ll_symbolTTDeltaNbBits_4}, {ll_symbolTTDeltaNbBits_3}, {ll_symbolTTDeltaNbBits_2}, {ll_symbolTTDeltaNbBits_1}, {ll_symbolTTDeltaNbBits_0}}; // @[FSECompressorDicBuilder.scala:412:39, :434:36] assign io_symbolTT_info_0_bits_nbbit_0 = _GEN_86[_io_symbolTT_info_0_bits_nbbit_T]; // @[FSECompressorDicBuilder.scala:39:7, :434:36] wire [15:0][31:0] _GEN_87 = {{ll_symbolTTDeltaFindState_0}, {ll_symbolTTDeltaFindState_0}, {ll_symbolTTDeltaFindState_0}, {ll_symbolTTDeltaFindState_12}, {ll_symbolTTDeltaFindState_11}, {ll_symbolTTDeltaFindState_10}, {ll_symbolTTDeltaFindState_9}, {ll_symbolTTDeltaFindState_8}, {ll_symbolTTDeltaFindState_7}, {ll_symbolTTDeltaFindState_6}, {ll_symbolTTDeltaFindState_5}, {ll_symbolTTDeltaFindState_4}, {ll_symbolTTDeltaFindState_3}, {ll_symbolTTDeltaFindState_2}, {ll_symbolTTDeltaFindState_1}, {ll_symbolTTDeltaFindState_0}}; // @[FSECompressorDicBuilder.scala:413:42, :435:81] assign _io_symbolTT_info_0_bits_findstate_T_1 = _GEN_87[_io_symbolTT_info_0_bits_findstate_T]; // @[FSECompressorDicBuilder.scala:435:81] assign io_symbolTT_info_0_bits_findstate_0 = _io_symbolTT_info_0_bits_findstate_T_1; // @[FSECompressorDicBuilder.scala:39:7, :435:81] assign io_new_state_0_valid_0 = _io_new_state_0_valid_T; // @[FSECompressorDicBuilder.scala:39:7, :438:47] wire [5:0] _io_new_state_0_bits_T = io_state_table_idx_0_0[5:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [63:0][15:0] _GEN_88 = {{ll_tableU16_63}, {ll_tableU16_62}, {ll_tableU16_61}, {ll_tableU16_60}, {ll_tableU16_59}, {ll_tableU16_58}, {ll_tableU16_57}, {ll_tableU16_56}, {ll_tableU16_55}, {ll_tableU16_54}, {ll_tableU16_53}, {ll_tableU16_52}, {ll_tableU16_51}, {ll_tableU16_50}, {ll_tableU16_49}, {ll_tableU16_48}, {ll_tableU16_47}, {ll_tableU16_46}, {ll_tableU16_45}, {ll_tableU16_44}, {ll_tableU16_43}, {ll_tableU16_42}, {ll_tableU16_41}, {ll_tableU16_40}, {ll_tableU16_39}, {ll_tableU16_38}, {ll_tableU16_37}, {ll_tableU16_36}, {ll_tableU16_35}, {ll_tableU16_34}, {ll_tableU16_33}, {ll_tableU16_32}, {ll_tableU16_31}, {ll_tableU16_30}, {ll_tableU16_29}, {ll_tableU16_28}, {ll_tableU16_27}, {ll_tableU16_26}, {ll_tableU16_25}, {ll_tableU16_24}, {ll_tableU16_23}, {ll_tableU16_22}, {ll_tableU16_21}, {ll_tableU16_20}, {ll_tableU16_19}, {ll_tableU16_18}, {ll_tableU16_17}, {ll_tableU16_16}, {ll_tableU16_15}, {ll_tableU16_14}, {ll_tableU16_13}, {ll_tableU16_12}, {ll_tableU16_11}, {ll_tableU16_10}, {ll_tableU16_9}, {ll_tableU16_8}, {ll_tableU16_7}, {ll_tableU16_6}, {ll_tableU16_5}, {ll_tableU16_4}, {ll_tableU16_3}, {ll_tableU16_2}, {ll_tableU16_1}, {ll_tableU16_0}}; // @[FSECompressorDicBuilder.scala:411:28, :439:26] assign io_new_state_0_bits_0 = _GEN_88[_io_new_state_0_bits_T]; // @[FSECompressorDicBuilder.scala:39:7, :439:26] wire _symbolTT_lookup_fire_and_last_vec_0_T = io_symbol_info_0_valid_0 & io_symbolTT_info_0_ready_0; // @[Misc.scala:29:18] wire _symbolTT_lookup_fire_and_last_vec_0_T_1 = _symbolTT_lookup_fire_and_last_vec_0_T & _T_1643; // @[Misc.scala:29:18] assign _symbolTT_lookup_fire_and_last_vec_0_T_2 = _symbolTT_lookup_fire_and_last_vec_0_T_1 & io_symbol_info_0_bits_last_symbol_0; // @[Misc.scala:29:18] assign symbolTT_lookup_fire_and_last_vec_0 = _symbolTT_lookup_fire_and_last_vec_0_T_2; // @[FSECompressorDicBuilder.scala:422:51, :441:71] assign _io_symbol_info_1_ready_T = io_symbolTT_info_1_ready_0 & _T_1643; // @[Misc.scala:26:53] assign io_symbol_info_1_ready_0 = _io_symbol_info_1_ready_T; // @[Misc.scala:26:53] assign _io_symbolTT_info_1_valid_T = io_symbol_info_1_valid_0 & _T_1643; // @[Misc.scala:26:53] assign io_symbolTT_info_1_valid_0 = _io_symbolTT_info_1_valid_T; // @[Misc.scala:26:53] wire [3:0] _io_symbolTT_info_1_bits_nbbit_T = io_symbol_info_1_bits_symbol_0[3:0]; // @[FSECompressorDicBuilder.scala:39:7] wire [3:0] _io_symbolTT_info_1_bits_findstate_T = io_symbol_info_1_bits_symbol_0[3:0]; // @[FSECompressorDicBuilder.scala:39:7] assign io_symbolTT_info_1_bits_nbbit_0 = _GEN_86[_io_symbolTT_info_1_bits_nbbit_T]; // @[FSECompressorDicBuilder.scala:39:7, :434:36] assign _io_symbolTT_info_1_bits_findstate_T_1 = _GEN_87[_io_symbolTT_info_1_bits_findstate_T]; // @[FSECompressorDicBuilder.scala:435:81] assign io_symbolTT_info_1_bits_findstate_0 = _io_symbolTT_info_1_bits_findstate_T_1; // @[FSECompressorDicBuilder.scala:39:7, :435:81] assign io_new_state_1_valid_0 = _io_new_state_1_valid_T; // @[FSECompressorDicBuilder.scala:39:7, :438:47] wire [5:0] _io_new_state_1_bits_T = io_state_table_idx_1_0[5:0]; // @[FSECompressorDicBuilder.scala:39:7] assign io_new_state_1_bits_0 = _GEN_88[_io_new_state_1_bits_T]; // @[FSECompressorDicBuilder.scala:39:7, :439:26] wire _symbolTT_lookup_fire_and_last_vec_1_T = io_symbol_info_1_valid_0 & io_symbolTT_info_1_ready_0; // @[Misc.scala:29:18] wire _symbolTT_lookup_fire_and_last_vec_1_T_1 = _symbolTT_lookup_fire_and_last_vec_1_T & _T_1643; // @[Misc.scala:29:18] assign _symbolTT_lookup_fire_and_last_vec_1_T_2 = _symbolTT_lookup_fire_and_last_vec_1_T_1 & io_symbol_info_1_bits_last_symbol_0; // @[Misc.scala:29:18] assign symbolTT_lookup_fire_and_last_vec_1 = _symbolTT_lookup_fire_and_last_vec_1_T_2; // @[FSECompressorDicBuilder.scala:422:51, :441:71] wire dictionary_lookup_done = symbolTT_lookup_fire_and_last_vec_0 | symbolTT_lookup_fire_and_last_vec_1; // @[FSECompressorDicBuilder.scala:422:51, :444:75] wire _use_predefined_mode_T = io_nb_seq_bits_0 < 64'h15; // @[FSECompressorDicBuilder.scala:39:7, :449:45] wire use_predefined_mode = _use_predefined_mode_T | fse_normalize_corner_case_reg; // @[FSECompressorDicBuilder.scala:314:46, :449:{45,87}] reg ll_table_log_fired; // @[FSECompressorDicBuilder.scala:451:35] wire _io_ll_table_log_valid_T = ~ll_table_log_fired; // @[FSECompressorDicBuilder.scala:451:35, :453:28] assign _io_ll_table_log_valid_T_2 = _io_ll_table_log_valid_T & _io_ll_table_log_valid_T_1; // @[FSECompressorDicBuilder.scala:453:{28,48,68}] assign io_ll_table_log_valid_0 = _io_ll_table_log_valid_T_2; // @[FSECompressorDicBuilder.scala:39:7, :453:48] reg print_table; // @[FSECompressorDicBuilder.scala:458:28] reg write_header_started; // @[FSECompressorDicBuilder.scala:461:37] reg [31:0] nbBits; // @[FSECompressorDicBuilder.scala:462:23] reg [31:0] remaining; // @[FSECompressorDicBuilder.scala:463:26] reg [31:0] threshold; // @[FSECompressorDicBuilder.scala:464:26] wire [31:0] shifted_thresholds_0 = threshold; // @[FSECompressorDicBuilder.scala:464:26, :484:36] reg [31:0] symbol; // @[FSECompressorDicBuilder.scala:465:23] wire [31:0] alphabetSize = _alphabetSize_T[31:0]; // @[FSECompressorDicBuilder.scala:466:42] reg previousIs0; // @[FSECompressorDicBuilder.scala:467:28] reg [63:0] bitStream; // @[FSECompressorDicBuilder.scala:468:26] reg [6:0] bitCount; // @[FSECompressorDicBuilder.scala:469:25] reg writeBitStream; // @[FSECompressorDicBuilder.scala:470:31] reg [31:0] start; // @[FSECompressorDicBuilder.scala:471:22] reg start_initialized; // @[FSECompressorDicBuilder.scala:472:34] reg skip_zeros_done; // @[FSECompressorDicBuilder.scala:473:32] reg skip_24_done; // @[FSECompressorDicBuilder.scala:474:29] reg skip_3_done; // @[FSECompressorDicBuilder.scala:475:28] reg writeBitStreamPrev0; // @[FSECompressorDicBuilder.scala:476:36] wire [31:0] _shifted_thresholds_1_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_2_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_3_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_4_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_5_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] _shifted_thresholds_6_T; // @[FSECompressorDicBuilder.scala:487:54] wire [31:0] shifted_thresholds_1; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_2; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_3; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_4; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_5; // @[FSECompressorDicBuilder.scala:484:36] wire [31:0] shifted_thresholds_6; // @[FSECompressorDicBuilder.scala:484:36] assign _shifted_thresholds_1_T = {1'h0, shifted_thresholds_0[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_1 = _shifted_thresholds_1_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_2_T = {1'h0, shifted_thresholds_1[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_2 = _shifted_thresholds_2_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_3_T = {1'h0, shifted_thresholds_2[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_3 = _shifted_thresholds_3_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_4_T = {1'h0, shifted_thresholds_3[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_4 = _shifted_thresholds_4_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_5_T = {1'h0, shifted_thresholds_4[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_5 = _shifted_thresholds_5_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign _shifted_thresholds_6_T = {1'h0, shifted_thresholds_5[31:1]}; // @[FSECompressorDicBuilder.scala:484:36, :487:54] assign shifted_thresholds_6 = _shifted_thresholds_6_T; // @[FSECompressorDicBuilder.scala:484:36, :487:54] wire [31:0] shifted_threshold_small_or_eq_remaining_0; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_1; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_2; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_3; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_4; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_5; // @[FSECompressorDicBuilder.scala:490:57] wire [31:0] shifted_threshold_small_or_eq_remaining_6; // @[FSECompressorDicBuilder.scala:490:57] wire [32:0] _nxt_shifted_threshold_idx_T = {1'h0, shifted_threshold_small_or_eq_remaining_0} + {1'h0, shifted_threshold_small_or_eq_remaining_1}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_1 = _nxt_shifted_threshold_idx_T[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_2 = {1'h0, _nxt_shifted_threshold_idx_T_1} + {1'h0, shifted_threshold_small_or_eq_remaining_2}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_3 = _nxt_shifted_threshold_idx_T_2[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_4 = {1'h0, _nxt_shifted_threshold_idx_T_3} + {1'h0, shifted_threshold_small_or_eq_remaining_3}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_5 = _nxt_shifted_threshold_idx_T_4[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_6 = {1'h0, _nxt_shifted_threshold_idx_T_5} + {1'h0, shifted_threshold_small_or_eq_remaining_4}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_7 = _nxt_shifted_threshold_idx_T_6[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_8 = {1'h0, _nxt_shifted_threshold_idx_T_7} + {1'h0, shifted_threshold_small_or_eq_remaining_5}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] _nxt_shifted_threshold_idx_T_9 = _nxt_shifted_threshold_idx_T_8[31:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nxt_shifted_threshold_idx_T_10 = {1'h0, _nxt_shifted_threshold_idx_T_9} + {1'h0, shifted_threshold_small_or_eq_remaining_6}; // @[FSECompressorDicBuilder.scala:490:57, :491:84] wire [31:0] nxt_shifted_threshold_idx = _nxt_shifted_threshold_idx_T_10[31:0]; // @[FSECompressorDicBuilder.scala:491:84] assign io_ll_stream_output_ready_0 = (|dicBuilderState) & _T_384 & _predefined_mode_q_io_enq_ready; // @[FSECompressorDicBuilder.scala:39:7, :137:29, :141:33, :156:32, :198:25, :551:28, :559:33] wire _io_ll_stream_user_consumed_bytes_T = io_ll_stream_available_output_bytes_0 < 6'h4; // @[FSECompressorDicBuilder.scala:39:7, :560:83] wire [5:0] _io_ll_stream_user_consumed_bytes_T_1 = _io_ll_stream_user_consumed_bytes_T ? io_ll_stream_available_output_bytes_0 : 6'h4; // @[FSECompressorDicBuilder.scala:39:7, :560:{46,83}] assign io_ll_stream_user_consumed_bytes_0 = (|dicBuilderState) & _T_384 ? _io_ll_stream_user_consumed_bytes_T_1 : 6'h0; // @[FSECompressorDicBuilder.scala:39:7, :138:36, :156:32, :198:25, :551:28, :560:46] wire [31:0] _ll_count_0_T_3 = _ll_count_0_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_1_T_3 = _ll_count_1_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_2_T_3 = _ll_count_2_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_3_T_3 = _ll_count_3_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_4_T_3 = _ll_count_4_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_5_T_3 = _ll_count_5_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_6_T_3 = _ll_count_6_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_7_T_3 = _ll_count_7_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_8_T_3 = _ll_count_8_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_9_T_3 = _ll_count_9_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_10_T_3 = _ll_count_10_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_11_T_3 = _ll_count_11_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_count_12_T_3 = _ll_count_12_T_2[31:0]; // @[FSECompressorDicBuilder.scala:566:38] wire [31:0] _ll_max_symbol_value_T_3 = _ll_max_symbol_value_T_2 ? ll_max_symbol_value : _GEN_13; // @[FSECompressorDicBuilder.scala:170:36, :204:54, :569:{35,56}] wire _T_388 = _predefined_mode_q_io_enq_ready & io_ll_stream_output_valid_0 & io_ll_stream_output_last_chunk_0 & io_ll_stream_user_consumed_bytes_0 == io_ll_stream_available_output_bytes_0; // @[FSECompressorDicBuilder.scala:39:7, :141:33, :572:{44,73,107,144}] wire _GEN_89 = _T_384 & _T_388; // @[FSECompressorDicBuilder.scala:198:25, :494:31, :551:28, :572:{44,73,107,186}, :588:22] wire _GEN_90 = (|dicBuilderState) & _GEN_89 & use_predefined_mode; // @[FSECompressorDicBuilder.scala:156:32, :316:80, :449:87, :494:31, :551:28, :572:186, :588:22, :591:37] reg [63:0] loginfo_cycles_93; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_186 = {1'h0, loginfo_cycles_93} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_187 = _loginfo_cycles_T_186[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_94; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_188 = {1'h0, loginfo_cycles_94} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_189 = _loginfo_cycles_T_188[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_95; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_190 = {1'h0, loginfo_cycles_95} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_191 = _loginfo_cycles_T_190[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_96; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_192 = {1'h0, loginfo_cycles_96} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_193 = _loginfo_cycles_T_192[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_97; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_194 = {1'h0, loginfo_cycles_97} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_195 = _loginfo_cycles_T_194[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_98; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_196 = {1'h0, loginfo_cycles_98} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_197 = _loginfo_cycles_T_196[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_99; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_198 = {1'h0, loginfo_cycles_99} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_199 = _loginfo_cycles_T_198[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_100; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_200 = {1'h0, loginfo_cycles_100} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_201 = _loginfo_cycles_T_200[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_101; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_202 = {1'h0, loginfo_cycles_101} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_203 = _loginfo_cycles_T_202[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_102; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_204 = {1'h0, loginfo_cycles_102} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_205 = _loginfo_cycles_T_204[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_103; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_206 = {1'h0, loginfo_cycles_103} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_207 = _loginfo_cycles_T_206[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_104; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_208 = {1'h0, loginfo_cycles_104} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_209 = _loginfo_cycles_T_208[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_105; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_210 = {1'h0, loginfo_cycles_105} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_211 = _loginfo_cycles_T_210[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_106; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_212 = {1'h0, loginfo_cycles_106} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_213 = _loginfo_cycles_T_212[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_107; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_214 = {1'h0, loginfo_cycles_107} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_215 = _loginfo_cycles_T_214[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_108; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_216 = {1'h0, loginfo_cycles_108} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_217 = _loginfo_cycles_T_216[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_109; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_218 = {1'h0, loginfo_cycles_109} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_219 = _loginfo_cycles_T_218[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_110; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_220 = {1'h0, loginfo_cycles_110} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_221 = _loginfo_cycles_T_220[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_111; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_222 = {1'h0, loginfo_cycles_111} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_223 = _loginfo_cycles_T_222[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_112; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_224 = {1'h0, loginfo_cycles_112} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_225 = _loginfo_cycles_T_224[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_113; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_226 = {1'h0, loginfo_cycles_113} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_227 = _loginfo_cycles_T_226[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_114; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_228 = {1'h0, loginfo_cycles_114} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_229 = _loginfo_cycles_T_228[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_115; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_230 = {1'h0, loginfo_cycles_115} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_231 = _loginfo_cycles_T_230[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_116; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_232 = {1'h0, loginfo_cycles_116} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_233 = _loginfo_cycles_T_232[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_117; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_234 = {1'h0, loginfo_cycles_117} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_235 = _loginfo_cycles_T_234[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_118; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_236 = {1'h0, loginfo_cycles_118} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_237 = _loginfo_cycles_T_236[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_119; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_238 = {1'h0, loginfo_cycles_119} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_239 = _loginfo_cycles_T_238[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_120; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_240 = {1'h0, loginfo_cycles_120} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_241 = _loginfo_cycles_T_240[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_121; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_242 = {1'h0, loginfo_cycles_121} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_243 = _loginfo_cycles_T_242[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_122; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_244 = {1'h0, loginfo_cycles_122} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_245 = _loginfo_cycles_T_244[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_123; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_246 = {1'h0, loginfo_cycles_123} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_247 = _loginfo_cycles_T_246[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_124; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_248 = {1'h0, loginfo_cycles_124} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_249 = _loginfo_cycles_T_248[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_125; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_250 = {1'h0, loginfo_cycles_125} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_251 = _loginfo_cycles_T_250[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_126; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_252 = {1'h0, loginfo_cycles_126} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_253 = _loginfo_cycles_T_252[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_127; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_254 = {1'h0, loginfo_cycles_127} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_255 = _loginfo_cycles_T_254[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_128; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_256 = {1'h0, loginfo_cycles_128} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_257 = _loginfo_cycles_T_256[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_129; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_258 = {1'h0, loginfo_cycles_129} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_259 = _loginfo_cycles_T_258[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_130; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_260 = {1'h0, loginfo_cycles_130} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_261 = _loginfo_cycles_T_260[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_131; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_262 = {1'h0, loginfo_cycles_131} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_263 = _loginfo_cycles_T_262[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_132; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_264 = {1'h0, loginfo_cycles_132} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_265 = _loginfo_cycles_T_264[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_133; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_266 = {1'h0, loginfo_cycles_133} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_267 = _loginfo_cycles_T_266[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_134; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_268 = {1'h0, loginfo_cycles_134} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_269 = _loginfo_cycles_T_268[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_135; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_270 = {1'h0, loginfo_cycles_135} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_271 = _loginfo_cycles_T_270[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_136; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_272 = {1'h0, loginfo_cycles_136} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_273 = _loginfo_cycles_T_272[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_137; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_274 = {1'h0, loginfo_cycles_137} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_275 = _loginfo_cycles_T_274[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_138; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_276 = {1'h0, loginfo_cycles_138} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_277 = _loginfo_cycles_T_276[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_139; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_278 = {1'h0, loginfo_cycles_139} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_279 = _loginfo_cycles_T_278[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_140; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_280 = {1'h0, loginfo_cycles_140} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_281 = _loginfo_cycles_T_280[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_141; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_282 = {1'h0, loginfo_cycles_141} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_283 = _loginfo_cycles_T_282[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_142; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_284 = {1'h0, loginfo_cycles_142} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_285 = _loginfo_cycles_T_284[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_143; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_286 = {1'h0, loginfo_cycles_143} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_287 = _loginfo_cycles_T_286[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_144; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_288 = {1'h0, loginfo_cycles_144} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_289 = _loginfo_cycles_T_288[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_145; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_290 = {1'h0, loginfo_cycles_145} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_291 = _loginfo_cycles_T_290[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_146; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_292 = {1'h0, loginfo_cycles_146} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_293 = _loginfo_cycles_T_292[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_147; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_294 = {1'h0, loginfo_cycles_147} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_295 = _loginfo_cycles_T_294[63:0]; // @[Util.scala:19:38] wire _T_611 = dicBuilderState == 4'h3; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire _GEN_91 = ~(|dicBuilderState) | _T_384 | _T_390; // @[FSECompressorDicBuilder.scala:156:32, :198:25, :316:25, :389:44, :551:28] wire _GEN_92 = _GEN_91 | ~_T_611; // @[FSECompressorDicBuilder.scala:389:44, :551:28] assign ll_normCountEqsNegOneCumul_0 = _GEN_92 ? 8'h0 : ll_normCountEqsNegOne_0; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :551:28] assign ll_normCountEqsNegOne_0 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_0)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_93 = {1'h0, ll_cumul_0}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_1_T = _GEN_93 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_1_T_1 = _ll_cumul_1_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_1_T_2 = _GEN_93 + {1'h0, ll_normalizedCounterReg_0}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_1_T_3 = _ll_cumul_1_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_1_T = {1'h0, ll_normCountEqsNegOneCumul_0} + _GEN_84; // @[FSECompressorDicBuilder.scala:389:44, :390:65, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_1_T_1 = _ll_normCountEqsNegOneCumul_1_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_1 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_1_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_1 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_1)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_94 = {1'h0, ll_cumul_1}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_2_T = _GEN_94 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_2_T_1 = _ll_cumul_2_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_2_T_2 = _GEN_94 + {1'h0, ll_normalizedCounterReg_1}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_2_T_3 = _ll_cumul_2_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_2_T = {1'h0, ll_normCountEqsNegOneCumul_1} + {1'h0, ll_normCountEqsNegOne_2}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_2_T_1 = _ll_normCountEqsNegOneCumul_2_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_2 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_2_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_2 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_2)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_95 = {1'h0, ll_cumul_2}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_3_T = _GEN_95 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_3_T_1 = _ll_cumul_3_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_3_T_2 = _GEN_95 + {1'h0, ll_normalizedCounterReg_2}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_3_T_3 = _ll_cumul_3_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_3_T = {1'h0, ll_normCountEqsNegOneCumul_2} + {1'h0, ll_normCountEqsNegOne_3}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_3_T_1 = _ll_normCountEqsNegOneCumul_3_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_3 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_3_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_3 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_3)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_96 = {1'h0, ll_cumul_3}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_4_T = _GEN_96 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_4_T_1 = _ll_cumul_4_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_4_T_2 = _GEN_96 + {1'h0, ll_normalizedCounterReg_3}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_4_T_3 = _ll_cumul_4_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_4_T = {1'h0, ll_normCountEqsNegOneCumul_3} + {1'h0, ll_normCountEqsNegOne_4}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_4_T_1 = _ll_normCountEqsNegOneCumul_4_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_4 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_4_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_4 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_4)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_97 = {1'h0, ll_cumul_4}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_5_T = _GEN_97 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_5_T_1 = _ll_cumul_5_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_5_T_2 = _GEN_97 + {1'h0, ll_normalizedCounterReg_4}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_5_T_3 = _ll_cumul_5_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_5_T = {1'h0, ll_normCountEqsNegOneCumul_4} + {1'h0, ll_normCountEqsNegOne_5}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_5_T_1 = _ll_normCountEqsNegOneCumul_5_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_5 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_5_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_5 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_5)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_98 = {1'h0, ll_cumul_5}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_6_T = _GEN_98 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_6_T_1 = _ll_cumul_6_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_6_T_2 = _GEN_98 + {1'h0, ll_normalizedCounterReg_5}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_6_T_3 = _ll_cumul_6_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_6_T = {1'h0, ll_normCountEqsNegOneCumul_5} + {1'h0, ll_normCountEqsNegOne_6}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_6_T_1 = _ll_normCountEqsNegOneCumul_6_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_6 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_6_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_6 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_6)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_99 = {1'h0, ll_cumul_6}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_7_T = _GEN_99 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_7_T_1 = _ll_cumul_7_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_7_T_2 = _GEN_99 + {1'h0, ll_normalizedCounterReg_6}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_7_T_3 = _ll_cumul_7_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_7_T = {1'h0, ll_normCountEqsNegOneCumul_6} + {1'h0, ll_normCountEqsNegOne_7}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_7_T_1 = _ll_normCountEqsNegOneCumul_7_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_7 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_7_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_7 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_7)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_100 = {1'h0, ll_cumul_7}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_8_T = _GEN_100 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_8_T_1 = _ll_cumul_8_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_8_T_2 = _GEN_100 + {1'h0, ll_normalizedCounterReg_7}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_8_T_3 = _ll_cumul_8_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_8_T = {1'h0, ll_normCountEqsNegOneCumul_7} + {1'h0, ll_normCountEqsNegOne_8}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_8_T_1 = _ll_normCountEqsNegOneCumul_8_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_8 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_8_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_8 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_8)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_101 = {1'h0, ll_cumul_8}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_9_T = _GEN_101 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_9_T_1 = _ll_cumul_9_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_9_T_2 = _GEN_101 + {1'h0, ll_normalizedCounterReg_8}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_9_T_3 = _ll_cumul_9_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_9_T = {1'h0, ll_normCountEqsNegOneCumul_8} + {1'h0, ll_normCountEqsNegOne_9}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_9_T_1 = _ll_normCountEqsNegOneCumul_9_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_9 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_9_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_9 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_9)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_102 = {1'h0, ll_cumul_9}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_10_T = _GEN_102 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_10_T_1 = _ll_cumul_10_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_10_T_2 = _GEN_102 + {1'h0, ll_normalizedCounterReg_9}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_10_T_3 = _ll_cumul_10_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_10_T = {1'h0, ll_normCountEqsNegOneCumul_9} + {1'h0, ll_normCountEqsNegOne_10}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_10_T_1 = _ll_normCountEqsNegOneCumul_10_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_10 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_10_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_10 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_10)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_103 = {1'h0, ll_cumul_10}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_11_T = _GEN_103 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_11_T_1 = _ll_cumul_11_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_11_T_2 = _GEN_103 + {1'h0, ll_normalizedCounterReg_10}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_11_T_3 = _ll_cumul_11_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_11_T = {1'h0, ll_normCountEqsNegOneCumul_10} + {1'h0, ll_normCountEqsNegOne_11}; // @[FSECompressorDicBuilder.scala:388:39, :389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_11_T_1 = _ll_normCountEqsNegOneCumul_11_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_11 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_11_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_normCountEqsNegOne_11 = _GEN_91 ? 8'h0 : {7'h0, _T_611 & (&ll_normalizedCounterReg_11)}; // @[FSECompressorDicBuilder.scala:337:40, :388:39, :389:44, :551:28, :692:{44,66}, :693:38] wire [16:0] _GEN_104 = {1'h0, ll_cumul_11}; // @[FSECompressorDicBuilder.scala:382:26, :694:40] wire [16:0] _ll_cumul_12_T = _GEN_104 + 17'h1; // @[FSECompressorDicBuilder.scala:694:40] wire [15:0] _ll_cumul_12_T_1 = _ll_cumul_12_T[15:0]; // @[FSECompressorDicBuilder.scala:694:40] wire [16:0] _ll_cumul_12_T_2 = _GEN_104 + {1'h0, ll_normalizedCounterReg_11}; // @[FSECompressorDicBuilder.scala:337:40, :694:40, :697:40] wire [15:0] _ll_cumul_12_T_3 = _ll_cumul_12_T_2[15:0]; // @[FSECompressorDicBuilder.scala:697:40] wire [8:0] _ll_normCountEqsNegOneCumul_12_T = {1'h0, ll_normCountEqsNegOneCumul_11}; // @[FSECompressorDicBuilder.scala:389:44, :700:74] wire [7:0] _ll_normCountEqsNegOneCumul_12_T_1 = _ll_normCountEqsNegOneCumul_12_T[7:0]; // @[FSECompressorDicBuilder.scala:700:74] assign ll_normCountEqsNegOneCumul_12 = _GEN_92 ? 8'h0 : _ll_normCountEqsNegOneCumul_12_T_1; // @[FSECompressorDicBuilder.scala:389:44, :551:28, :700:74] assign ll_cumul_0 = _GEN_91 | ~(_T_611 & ll_maxSV1[3:0] == 4'h0) ? 16'h0 : 16'h41; // @[FSECompressorDicBuilder.scala:379:39, :382:26, :389:44, :551:28, :703:27] assign ll_cumul_1 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'h1 ? 16'h41 : (&ll_normalizedCounterReg_0) ? _ll_cumul_1_T_1 : _ll_cumul_1_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_2 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'h2 ? 16'h41 : (&ll_normalizedCounterReg_1) ? _ll_cumul_2_T_1 : _ll_cumul_2_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_3 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'h3 ? 16'h41 : (&ll_normalizedCounterReg_2) ? _ll_cumul_3_T_1 : _ll_cumul_3_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_4 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'h4 ? 16'h41 : (&ll_normalizedCounterReg_3) ? _ll_cumul_4_T_1 : _ll_cumul_4_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_5 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'h5 ? 16'h41 : (&ll_normalizedCounterReg_4) ? _ll_cumul_5_T_1 : _ll_cumul_5_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_6 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'h6 ? 16'h41 : (&ll_normalizedCounterReg_5) ? _ll_cumul_6_T_1 : _ll_cumul_6_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_7 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'h7 ? 16'h41 : (&ll_normalizedCounterReg_6) ? _ll_cumul_7_T_1 : _ll_cumul_7_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_8 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'h8 ? 16'h41 : (&ll_normalizedCounterReg_7) ? _ll_cumul_8_T_1 : _ll_cumul_8_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_9 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'h9 ? 16'h41 : (&ll_normalizedCounterReg_8) ? _ll_cumul_9_T_1 : _ll_cumul_9_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_10 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'hA ? 16'h41 : (&ll_normalizedCounterReg_9) ? _ll_cumul_10_T_1 : _ll_cumul_10_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_11 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'hB ? 16'h41 : (&ll_normalizedCounterReg_10) ? _ll_cumul_11_T_1 : _ll_cumul_11_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] assign ll_cumul_12 = _GEN_92 ? 16'h0 : ll_maxSV1[3:0] == 4'hC ? 16'h41 : (&ll_normalizedCounterReg_11) ? _ll_cumul_12_T_1 : _ll_cumul_12_T_3; // @[FSECompressorDicBuilder.scala:337:40, :379:39, :382:26, :389:44, :551:28, :692:{44,66}, :694:{23,40}, :697:{23,40}, :703:27] wire [32:0] _ll_highThresholdAfterCumul_T = 33'h3F - {13'h0, ll_normCountEqsNegOneSum}; // @[FSECompressorDicBuilder.scala:390:65, :704:65] wire [31:0] _ll_highThresholdAfterCumul_T_1 = _ll_highThresholdAfterCumul_T[31:0]; // @[FSECompressorDicBuilder.scala:704:65] wire _T_685 = dicBuilderState == 4'h4; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire [64:0] _GEN_105 = {1'h0, ll_s}; // @[FSECompressorDicBuilder.scala:403:21, :716:22] wire [64:0] _GEN_106 = _GEN_105 + 65'h1; // @[FSECompressorDicBuilder.scala:716:22] wire [64:0] _ll_s_T; // @[FSECompressorDicBuilder.scala:716:22] assign _ll_s_T = _GEN_106; // @[FSECompressorDicBuilder.scala:716:22] wire [64:0] _ll_s_T_2; // @[FSECompressorDicBuilder.scala:757:20] assign _ll_s_T_2 = _GEN_106; // @[FSECompressorDicBuilder.scala:716:22, :757:20] wire [64:0] _ll_s_T_4; // @[FSECompressorDicBuilder.scala:768:20] assign _ll_s_T_4 = _GEN_106; // @[FSECompressorDicBuilder.scala:716:22, :768:20] wire [63:0] _ll_s_T_1 = _ll_s_T[63:0]; // @[FSECompressorDicBuilder.scala:716:22] wire [64:0] _ll_sv_T = {1'h0, ll_sv} + 65'h101010101010101; // @[FSECompressorDicBuilder.scala:404:22, :717:24] wire [63:0] _ll_sv_T_1 = _ll_sv_T[63:0]; // @[FSECompressorDicBuilder.scala:717:24] wire [15:0] write_spread_cnt = {3'h0, _GEN_85[_n_T][15:3]}; // @[FSECompressorDicBuilder.scala:416:13, :719:34] wire [15:0] _write_extra_T = {13'h0, _GEN_85[_n_T][2:0]}; // @[FSECompressorDicBuilder.scala:416:13, :719:34, :720:30] wire write_extra = |_write_extra_T; // @[FSECompressorDicBuilder.scala:720:{30,37}] wire [16:0] write_spread_cnt_wrapped = {1'h0, write_spread_cnt} + {16'h0, write_extra}; // @[FSECompressorDicBuilder.scala:719:34, :720:37, :721:57] wire [19:0] write_spread_bytes = {write_spread_cnt_wrapped, 3'h0}; // @[FSECompressorDicBuilder.scala:721:57, :722:59] wire [64:0] _GEN_107 = {1'h0, ll_pos}; // @[FSECompressorDicBuilder.scala:402:23, :723:26] wire [64:0] _ll_pos_T = _GEN_107 + {49'h0, _GEN_85[_n_T]}; // @[FSECompressorDicBuilder.scala:416:13, :719:34, :723:26] wire [63:0] _ll_pos_T_1 = _ll_pos_T[63:0]; // @[FSECompressorDicBuilder.scala:723:26] wire [64:0] _GEN_108 = 65'h0 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T = _GEN_108; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_144; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_144 = _GEN_108; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_1 = _shift_bytes_T[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes = _shift_bytes_T_1[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits = {shift_bytes, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_0_T = ll_sv >> shift_bits; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_109 = 65'h1 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_2; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_2 = _GEN_109; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_146; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_146 = _GEN_109; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_3 = _shift_bytes_T_2[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_1 = _shift_bytes_T_3[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_1 = {shift_bytes_1, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_1_T = ll_sv >> shift_bits_1; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_110 = 65'h2 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_4; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_4 = _GEN_110; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_148; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_148 = _GEN_110; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_5 = _shift_bytes_T_4[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_2 = _shift_bytes_T_5[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_2 = {shift_bytes_2, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_2_T = ll_sv >> shift_bits_2; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_111 = 65'h3 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_6; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_6 = _GEN_111; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_150; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_150 = _GEN_111; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_7 = _shift_bytes_T_6[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_3 = _shift_bytes_T_7[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_3 = {shift_bytes_3, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_3_T = ll_sv >> shift_bits_3; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_112 = 65'h4 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_8; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_8 = _GEN_112; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_152; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_152 = _GEN_112; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_9 = _shift_bytes_T_8[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_4 = _shift_bytes_T_9[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_4 = {shift_bytes_4, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_4_T = ll_sv >> shift_bits_4; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_113 = 65'h5 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_10; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_10 = _GEN_113; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_154; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_154 = _GEN_113; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_11 = _shift_bytes_T_10[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_5 = _shift_bytes_T_11[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_5 = {shift_bytes_5, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_5_T = ll_sv >> shift_bits_5; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_114 = 65'h6 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_12; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_12 = _GEN_114; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_156; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_156 = _GEN_114; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_13 = _shift_bytes_T_12[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_6 = _shift_bytes_T_13[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_6 = {shift_bytes_6, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_6_T = ll_sv >> shift_bits_6; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_115 = 65'h7 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_14; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_14 = _GEN_115; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_158; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_158 = _GEN_115; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_15 = _shift_bytes_T_14[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_7 = _shift_bytes_T_15[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_7 = {shift_bytes_7, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_7_T = ll_sv >> shift_bits_7; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_116 = 65'h8 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_16; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_16 = _GEN_116; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_160; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_160 = _GEN_116; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_17 = _shift_bytes_T_16[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_8 = _shift_bytes_T_17[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_8 = {shift_bytes_8, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_8_T = ll_sv >> shift_bits_8; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_117 = 65'h9 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_18; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_18 = _GEN_117; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_162; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_162 = _GEN_117; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_19 = _shift_bytes_T_18[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_9 = _shift_bytes_T_19[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_9 = {shift_bytes_9, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_9_T = ll_sv >> shift_bits_9; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_118 = 65'hA - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_20; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_20 = _GEN_118; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_164; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_164 = _GEN_118; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_21 = _shift_bytes_T_20[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_10 = _shift_bytes_T_21[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_10 = {shift_bytes_10, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_10_T = ll_sv >> shift_bits_10; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_119 = 65'hB - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_22; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_22 = _GEN_119; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_166; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_166 = _GEN_119; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_23 = _shift_bytes_T_22[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_11 = _shift_bytes_T_23[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_11 = {shift_bytes_11, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_11_T = ll_sv >> shift_bits_11; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_120 = 65'hC - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_24; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_24 = _GEN_120; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_168; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_168 = _GEN_120; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_25 = _shift_bytes_T_24[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_12 = _shift_bytes_T_25[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_12 = {shift_bytes_12, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_12_T = ll_sv >> shift_bits_12; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_121 = 65'hD - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_26; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_26 = _GEN_121; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_170; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_170 = _GEN_121; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_27 = _shift_bytes_T_26[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_13 = _shift_bytes_T_27[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_13 = {shift_bytes_13, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_13_T = ll_sv >> shift_bits_13; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_122 = 65'hE - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_28; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_28 = _GEN_122; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_172; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_172 = _GEN_122; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_29 = _shift_bytes_T_28[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_14 = _shift_bytes_T_29[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_14 = {shift_bytes_14, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_14_T = ll_sv >> shift_bits_14; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_123 = 65'hF - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_30; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_30 = _GEN_123; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_174; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_174 = _GEN_123; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_31 = _shift_bytes_T_30[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_15 = _shift_bytes_T_31[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_15 = {shift_bytes_15, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_15_T = ll_sv >> shift_bits_15; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_124 = 65'h10 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_32; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_32 = _GEN_124; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_176; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_176 = _GEN_124; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_33 = _shift_bytes_T_32[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_16 = _shift_bytes_T_33[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_16 = {shift_bytes_16, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_16_T = ll_sv >> shift_bits_16; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_125 = 65'h11 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_34; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_34 = _GEN_125; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_178; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_178 = _GEN_125; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_35 = _shift_bytes_T_34[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_17 = _shift_bytes_T_35[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_17 = {shift_bytes_17, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_17_T = ll_sv >> shift_bits_17; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_126 = 65'h12 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_36; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_36 = _GEN_126; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_180; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_180 = _GEN_126; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_37 = _shift_bytes_T_36[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_18 = _shift_bytes_T_37[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_18 = {shift_bytes_18, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_18_T = ll_sv >> shift_bits_18; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_127 = 65'h13 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_38; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_38 = _GEN_127; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_182; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_182 = _GEN_127; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_39 = _shift_bytes_T_38[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_19 = _shift_bytes_T_39[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_19 = {shift_bytes_19, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_19_T = ll_sv >> shift_bits_19; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_128 = 65'h14 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_40; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_40 = _GEN_128; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_184; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_184 = _GEN_128; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_41 = _shift_bytes_T_40[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_20 = _shift_bytes_T_41[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_20 = {shift_bytes_20, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_20_T = ll_sv >> shift_bits_20; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_129 = 65'h15 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_42; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_42 = _GEN_129; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_186; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_186 = _GEN_129; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_43 = _shift_bytes_T_42[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_21 = _shift_bytes_T_43[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_21 = {shift_bytes_21, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_21_T = ll_sv >> shift_bits_21; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_130 = 65'h16 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_44; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_44 = _GEN_130; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_188; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_188 = _GEN_130; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_45 = _shift_bytes_T_44[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_22 = _shift_bytes_T_45[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_22 = {shift_bytes_22, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_22_T = ll_sv >> shift_bits_22; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_131 = 65'h17 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_46; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_46 = _GEN_131; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_190; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_190 = _GEN_131; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_47 = _shift_bytes_T_46[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_23 = _shift_bytes_T_47[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_23 = {shift_bytes_23, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_23_T = ll_sv >> shift_bits_23; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_132 = 65'h18 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_48; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_48 = _GEN_132; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_192; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_192 = _GEN_132; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_49 = _shift_bytes_T_48[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_24 = _shift_bytes_T_49[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_24 = {shift_bytes_24, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_24_T = ll_sv >> shift_bits_24; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_133 = 65'h19 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_50; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_50 = _GEN_133; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_194; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_194 = _GEN_133; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_51 = _shift_bytes_T_50[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_25 = _shift_bytes_T_51[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_25 = {shift_bytes_25, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_25_T = ll_sv >> shift_bits_25; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_134 = 65'h1A - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_52; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_52 = _GEN_134; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_196; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_196 = _GEN_134; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_53 = _shift_bytes_T_52[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_26 = _shift_bytes_T_53[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_26 = {shift_bytes_26, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_26_T = ll_sv >> shift_bits_26; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_135 = 65'h1B - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_54; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_54 = _GEN_135; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_198; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_198 = _GEN_135; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_55 = _shift_bytes_T_54[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_27 = _shift_bytes_T_55[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_27 = {shift_bytes_27, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_27_T = ll_sv >> shift_bits_27; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_136 = 65'h1C - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_56; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_56 = _GEN_136; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_200; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_200 = _GEN_136; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_57 = _shift_bytes_T_56[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_28 = _shift_bytes_T_57[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_28 = {shift_bytes_28, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_28_T = ll_sv >> shift_bits_28; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_137 = 65'h1D - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_58; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_58 = _GEN_137; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_202; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_202 = _GEN_137; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_59 = _shift_bytes_T_58[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_29 = _shift_bytes_T_59[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_29 = {shift_bytes_29, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_29_T = ll_sv >> shift_bits_29; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_138 = 65'h1E - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_60; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_60 = _GEN_138; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_204; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_204 = _GEN_138; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_61 = _shift_bytes_T_60[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_30 = _shift_bytes_T_61[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_30 = {shift_bytes_30, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_30_T = ll_sv >> shift_bits_30; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_139 = 65'h1F - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_62; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_62 = _GEN_139; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_206; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_206 = _GEN_139; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_63 = _shift_bytes_T_62[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_31 = _shift_bytes_T_63[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_31 = {shift_bytes_31, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_31_T = ll_sv >> shift_bits_31; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_140 = 65'h20 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_64; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_64 = _GEN_140; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_208; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_208 = _GEN_140; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_65 = _shift_bytes_T_64[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_32 = _shift_bytes_T_65[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_32 = {shift_bytes_32, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_32_T = ll_sv >> shift_bits_32; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_141 = 65'h21 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_66; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_66 = _GEN_141; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_210; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_210 = _GEN_141; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_67 = _shift_bytes_T_66[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_33 = _shift_bytes_T_67[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_33 = {shift_bytes_33, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_33_T = ll_sv >> shift_bits_33; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_142 = 65'h22 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_68; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_68 = _GEN_142; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_212; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_212 = _GEN_142; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_69 = _shift_bytes_T_68[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_34 = _shift_bytes_T_69[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_34 = {shift_bytes_34, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_34_T = ll_sv >> shift_bits_34; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_143 = 65'h23 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_70; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_70 = _GEN_143; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_214; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_214 = _GEN_143; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_71 = _shift_bytes_T_70[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_35 = _shift_bytes_T_71[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_35 = {shift_bytes_35, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_35_T = ll_sv >> shift_bits_35; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_144 = 65'h24 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_72; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_72 = _GEN_144; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_216; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_216 = _GEN_144; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_73 = _shift_bytes_T_72[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_36 = _shift_bytes_T_73[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_36 = {shift_bytes_36, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_36_T = ll_sv >> shift_bits_36; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_145 = 65'h25 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_74; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_74 = _GEN_145; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_218; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_218 = _GEN_145; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_75 = _shift_bytes_T_74[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_37 = _shift_bytes_T_75[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_37 = {shift_bytes_37, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_37_T = ll_sv >> shift_bits_37; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_146 = 65'h26 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_76; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_76 = _GEN_146; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_220; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_220 = _GEN_146; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_77 = _shift_bytes_T_76[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_38 = _shift_bytes_T_77[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_38 = {shift_bytes_38, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_38_T = ll_sv >> shift_bits_38; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_147 = 65'h27 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_78; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_78 = _GEN_147; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_222; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_222 = _GEN_147; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_79 = _shift_bytes_T_78[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_39 = _shift_bytes_T_79[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_39 = {shift_bytes_39, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_39_T = ll_sv >> shift_bits_39; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_148 = 65'h28 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_80; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_80 = _GEN_148; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_224; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_224 = _GEN_148; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_81 = _shift_bytes_T_80[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_40 = _shift_bytes_T_81[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_40 = {shift_bytes_40, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_40_T = ll_sv >> shift_bits_40; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_149 = 65'h29 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_82; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_82 = _GEN_149; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_226; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_226 = _GEN_149; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_83 = _shift_bytes_T_82[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_41 = _shift_bytes_T_83[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_41 = {shift_bytes_41, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_41_T = ll_sv >> shift_bits_41; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_150 = 65'h2A - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_84; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_84 = _GEN_150; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_228; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_228 = _GEN_150; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_85 = _shift_bytes_T_84[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_42 = _shift_bytes_T_85[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_42 = {shift_bytes_42, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_42_T = ll_sv >> shift_bits_42; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_151 = 65'h2B - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_86; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_86 = _GEN_151; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_230; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_230 = _GEN_151; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_87 = _shift_bytes_T_86[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_43 = _shift_bytes_T_87[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_43 = {shift_bytes_43, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_43_T = ll_sv >> shift_bits_43; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_152 = 65'h2C - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_88; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_88 = _GEN_152; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_232; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_232 = _GEN_152; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_89 = _shift_bytes_T_88[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_44 = _shift_bytes_T_89[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_44 = {shift_bytes_44, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_44_T = ll_sv >> shift_bits_44; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_153 = 65'h2D - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_90; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_90 = _GEN_153; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_234; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_234 = _GEN_153; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_91 = _shift_bytes_T_90[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_45 = _shift_bytes_T_91[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_45 = {shift_bytes_45, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_45_T = ll_sv >> shift_bits_45; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_154 = 65'h2E - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_92; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_92 = _GEN_154; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_236; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_236 = _GEN_154; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_93 = _shift_bytes_T_92[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_46 = _shift_bytes_T_93[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_46 = {shift_bytes_46, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_46_T = ll_sv >> shift_bits_46; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_155 = 65'h2F - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_94; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_94 = _GEN_155; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_238; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_238 = _GEN_155; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_95 = _shift_bytes_T_94[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_47 = _shift_bytes_T_95[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_47 = {shift_bytes_47, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_47_T = ll_sv >> shift_bits_47; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_156 = 65'h30 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_96; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_96 = _GEN_156; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_240; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_240 = _GEN_156; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_97 = _shift_bytes_T_96[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_48 = _shift_bytes_T_97[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_48 = {shift_bytes_48, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_48_T = ll_sv >> shift_bits_48; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_157 = 65'h31 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_98; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_98 = _GEN_157; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_242; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_242 = _GEN_157; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_99 = _shift_bytes_T_98[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_49 = _shift_bytes_T_99[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_49 = {shift_bytes_49, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_49_T = ll_sv >> shift_bits_49; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_158 = 65'h32 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_100; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_100 = _GEN_158; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_244; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_244 = _GEN_158; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_101 = _shift_bytes_T_100[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_50 = _shift_bytes_T_101[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_50 = {shift_bytes_50, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_50_T = ll_sv >> shift_bits_50; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_159 = 65'h33 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_102; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_102 = _GEN_159; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_246; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_246 = _GEN_159; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_103 = _shift_bytes_T_102[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_51 = _shift_bytes_T_103[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_51 = {shift_bytes_51, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_51_T = ll_sv >> shift_bits_51; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_160 = 65'h34 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_104; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_104 = _GEN_160; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_248; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_248 = _GEN_160; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_105 = _shift_bytes_T_104[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_52 = _shift_bytes_T_105[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_52 = {shift_bytes_52, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_52_T = ll_sv >> shift_bits_52; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_161 = 65'h35 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_106; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_106 = _GEN_161; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_250; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_250 = _GEN_161; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_107 = _shift_bytes_T_106[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_53 = _shift_bytes_T_107[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_53 = {shift_bytes_53, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_53_T = ll_sv >> shift_bits_53; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_162 = 65'h36 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_108; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_108 = _GEN_162; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_252; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_252 = _GEN_162; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_109 = _shift_bytes_T_108[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_54 = _shift_bytes_T_109[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_54 = {shift_bytes_54, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_54_T = ll_sv >> shift_bits_54; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_163 = 65'h37 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_110; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_110 = _GEN_163; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_254; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_254 = _GEN_163; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_111 = _shift_bytes_T_110[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_55 = _shift_bytes_T_111[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_55 = {shift_bytes_55, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_55_T = ll_sv >> shift_bits_55; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_164 = 65'h38 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_112; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_112 = _GEN_164; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_256; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_256 = _GEN_164; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_113 = _shift_bytes_T_112[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_56 = _shift_bytes_T_113[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_56 = {shift_bytes_56, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_56_T = ll_sv >> shift_bits_56; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_165 = 65'h39 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_114; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_114 = _GEN_165; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_258; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_258 = _GEN_165; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_115 = _shift_bytes_T_114[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_57 = _shift_bytes_T_115[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_57 = {shift_bytes_57, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_57_T = ll_sv >> shift_bits_57; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_166 = 65'h3A - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_116; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_116 = _GEN_166; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_260; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_260 = _GEN_166; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_117 = _shift_bytes_T_116[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_58 = _shift_bytes_T_117[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_58 = {shift_bytes_58, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_58_T = ll_sv >> shift_bits_58; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_167 = 65'h3B - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_118; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_118 = _GEN_167; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_262; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_262 = _GEN_167; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_119 = _shift_bytes_T_118[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_59 = _shift_bytes_T_119[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_59 = {shift_bytes_59, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_59_T = ll_sv >> shift_bits_59; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_168 = 65'h3C - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_120; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_120 = _GEN_168; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_264; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_264 = _GEN_168; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_121 = _shift_bytes_T_120[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_60 = _shift_bytes_T_121[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_60 = {shift_bytes_60, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_60_T = ll_sv >> shift_bits_60; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_169 = 65'h3D - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_122; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_122 = _GEN_169; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_266; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_266 = _GEN_169; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_123 = _shift_bytes_T_122[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_61 = _shift_bytes_T_123[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_61 = {shift_bytes_61, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_61_T = ll_sv >> shift_bits_61; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_170 = 65'h3E - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_124; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_124 = _GEN_170; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_268; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_268 = _GEN_170; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_125 = _shift_bytes_T_124[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_62 = _shift_bytes_T_125[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_62 = {shift_bytes_62, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_62_T = ll_sv >> shift_bits_62; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _GEN_171 = 65'h3F - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [64:0] _shift_bytes_T_126; // @[FSECompressorDicBuilder.scala:728:36] assign _shift_bytes_T_126 = _GEN_171; // @[FSECompressorDicBuilder.scala:728:36] wire [64:0] _shift_bytes_T_270; // @[FSECompressorDicBuilder.scala:739:38] assign _shift_bytes_T_270 = _GEN_171; // @[FSECompressorDicBuilder.scala:728:36, :739:38] wire [63:0] _shift_bytes_T_127 = _shift_bytes_T_126[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_63 = _shift_bytes_T_127[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_63 = {shift_bytes_63, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_63_T = ll_sv >> shift_bits_63; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_128 = 65'h40 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_129 = _shift_bytes_T_128[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_64 = _shift_bytes_T_129[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_64 = {shift_bytes_64, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_64_T = ll_sv >> shift_bits_64; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_130 = 65'h41 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_131 = _shift_bytes_T_130[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_65 = _shift_bytes_T_131[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_65 = {shift_bytes_65, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_65_T = ll_sv >> shift_bits_65; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_132 = 65'h42 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_133 = _shift_bytes_T_132[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_66 = _shift_bytes_T_133[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_66 = {shift_bytes_66, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_66_T = ll_sv >> shift_bits_66; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_134 = 65'h43 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_135 = _shift_bytes_T_134[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_67 = _shift_bytes_T_135[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_67 = {shift_bytes_67, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_67_T = ll_sv >> shift_bits_67; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_136 = 65'h44 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_137 = _shift_bytes_T_136[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_68 = _shift_bytes_T_137[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_68 = {shift_bytes_68, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_68_T = ll_sv >> shift_bits_68; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_138 = 65'h45 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_139 = _shift_bytes_T_138[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_69 = _shift_bytes_T_139[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_69 = {shift_bytes_69, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_69_T = ll_sv >> shift_bits_69; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_140 = 65'h46 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_141 = _shift_bytes_T_140[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_70 = _shift_bytes_T_141[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_70 = {shift_bytes_70, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_70_T = ll_sv >> shift_bits_70; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [64:0] _shift_bytes_T_142 = 65'h47 - _GEN_107; // @[FSECompressorDicBuilder.scala:723:26, :728:36] wire [63:0] _shift_bytes_T_143 = _shift_bytes_T_142[63:0]; // @[FSECompressorDicBuilder.scala:728:36] wire [2:0] shift_bytes_71 = _shift_bytes_T_143[2:0]; // @[FSECompressorDicBuilder.scala:728:{36,45}] wire [5:0] shift_bits_71 = {shift_bytes_71, 3'h0}; // @[FSECompressorDicBuilder.scala:728:45, :729:42] wire [63:0] _ll_spread_71_T = ll_sv >> shift_bits_71; // @[FSECompressorDicBuilder.scala:404:22, :729:42, :730:35] wire [63:0] _shift_bytes_T_145 = _shift_bytes_T_144[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_72 = _shift_bytes_T_145[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_72 = {shift_bytes_72, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T = ll_sv >> shift_bits_72; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_147 = _shift_bytes_T_146[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_73 = _shift_bytes_T_147[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_73 = {shift_bytes_73, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_1 = ll_sv >> shift_bits_73; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_149 = _shift_bytes_T_148[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_74 = _shift_bytes_T_149[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_74 = {shift_bytes_74, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_2 = ll_sv >> shift_bits_74; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_151 = _shift_bytes_T_150[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_75 = _shift_bytes_T_151[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_75 = {shift_bytes_75, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_3 = ll_sv >> shift_bits_75; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_153 = _shift_bytes_T_152[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_76 = _shift_bytes_T_153[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_76 = {shift_bytes_76, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_4 = ll_sv >> shift_bits_76; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_155 = _shift_bytes_T_154[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_77 = _shift_bytes_T_155[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_77 = {shift_bytes_77, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_5 = ll_sv >> shift_bits_77; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_157 = _shift_bytes_T_156[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_78 = _shift_bytes_T_157[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_78 = {shift_bytes_78, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_6 = ll_sv >> shift_bits_78; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_159 = _shift_bytes_T_158[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_79 = _shift_bytes_T_159[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_79 = {shift_bytes_79, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_7 = ll_sv >> shift_bits_79; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_161 = _shift_bytes_T_160[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_80 = _shift_bytes_T_161[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_80 = {shift_bytes_80, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_8 = ll_sv >> shift_bits_80; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_163 = _shift_bytes_T_162[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_81 = _shift_bytes_T_163[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_81 = {shift_bytes_81, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_9 = ll_sv >> shift_bits_81; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_165 = _shift_bytes_T_164[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_82 = _shift_bytes_T_165[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_82 = {shift_bytes_82, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_10 = ll_sv >> shift_bits_82; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_167 = _shift_bytes_T_166[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_83 = _shift_bytes_T_167[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_83 = {shift_bytes_83, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_11 = ll_sv >> shift_bits_83; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_169 = _shift_bytes_T_168[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_84 = _shift_bytes_T_169[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_84 = {shift_bytes_84, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_12 = ll_sv >> shift_bits_84; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_171 = _shift_bytes_T_170[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_85 = _shift_bytes_T_171[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_85 = {shift_bytes_85, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_13 = ll_sv >> shift_bits_85; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_173 = _shift_bytes_T_172[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_86 = _shift_bytes_T_173[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_86 = {shift_bytes_86, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_14 = ll_sv >> shift_bits_86; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_175 = _shift_bytes_T_174[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_87 = _shift_bytes_T_175[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_87 = {shift_bytes_87, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_15 = ll_sv >> shift_bits_87; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_177 = _shift_bytes_T_176[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_88 = _shift_bytes_T_177[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_88 = {shift_bytes_88, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_16 = ll_sv >> shift_bits_88; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_179 = _shift_bytes_T_178[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_89 = _shift_bytes_T_179[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_89 = {shift_bytes_89, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_17 = ll_sv >> shift_bits_89; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_181 = _shift_bytes_T_180[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_90 = _shift_bytes_T_181[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_90 = {shift_bytes_90, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_18 = ll_sv >> shift_bits_90; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_183 = _shift_bytes_T_182[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_91 = _shift_bytes_T_183[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_91 = {shift_bytes_91, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_19 = ll_sv >> shift_bits_91; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_185 = _shift_bytes_T_184[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_92 = _shift_bytes_T_185[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_92 = {shift_bytes_92, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_20 = ll_sv >> shift_bits_92; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_187 = _shift_bytes_T_186[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_93 = _shift_bytes_T_187[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_93 = {shift_bytes_93, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_21 = ll_sv >> shift_bits_93; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_189 = _shift_bytes_T_188[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_94 = _shift_bytes_T_189[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_94 = {shift_bytes_94, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_22 = ll_sv >> shift_bits_94; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_191 = _shift_bytes_T_190[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_95 = _shift_bytes_T_191[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_95 = {shift_bytes_95, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_23 = ll_sv >> shift_bits_95; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_193 = _shift_bytes_T_192[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_96 = _shift_bytes_T_193[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_96 = {shift_bytes_96, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_24 = ll_sv >> shift_bits_96; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_195 = _shift_bytes_T_194[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_97 = _shift_bytes_T_195[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_97 = {shift_bytes_97, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_25 = ll_sv >> shift_bits_97; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_197 = _shift_bytes_T_196[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_98 = _shift_bytes_T_197[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_98 = {shift_bytes_98, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_26 = ll_sv >> shift_bits_98; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_199 = _shift_bytes_T_198[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_99 = _shift_bytes_T_199[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_99 = {shift_bytes_99, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_27 = ll_sv >> shift_bits_99; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_201 = _shift_bytes_T_200[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_100 = _shift_bytes_T_201[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_100 = {shift_bytes_100, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_28 = ll_sv >> shift_bits_100; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_203 = _shift_bytes_T_202[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_101 = _shift_bytes_T_203[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_101 = {shift_bytes_101, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_29 = ll_sv >> shift_bits_101; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_205 = _shift_bytes_T_204[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_102 = _shift_bytes_T_205[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_102 = {shift_bytes_102, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_30 = ll_sv >> shift_bits_102; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_207 = _shift_bytes_T_206[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_103 = _shift_bytes_T_207[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_103 = {shift_bytes_103, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_31 = ll_sv >> shift_bits_103; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_209 = _shift_bytes_T_208[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_104 = _shift_bytes_T_209[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_104 = {shift_bytes_104, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_32 = ll_sv >> shift_bits_104; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_211 = _shift_bytes_T_210[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_105 = _shift_bytes_T_211[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_105 = {shift_bytes_105, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_33 = ll_sv >> shift_bits_105; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_213 = _shift_bytes_T_212[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_106 = _shift_bytes_T_213[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_106 = {shift_bytes_106, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_34 = ll_sv >> shift_bits_106; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_215 = _shift_bytes_T_214[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_107 = _shift_bytes_T_215[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_107 = {shift_bytes_107, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_35 = ll_sv >> shift_bits_107; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_217 = _shift_bytes_T_216[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_108 = _shift_bytes_T_217[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_108 = {shift_bytes_108, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_36 = ll_sv >> shift_bits_108; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_219 = _shift_bytes_T_218[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_109 = _shift_bytes_T_219[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_109 = {shift_bytes_109, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_37 = ll_sv >> shift_bits_109; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_221 = _shift_bytes_T_220[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_110 = _shift_bytes_T_221[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_110 = {shift_bytes_110, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_38 = ll_sv >> shift_bits_110; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_223 = _shift_bytes_T_222[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_111 = _shift_bytes_T_223[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_111 = {shift_bytes_111, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_39 = ll_sv >> shift_bits_111; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_225 = _shift_bytes_T_224[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_112 = _shift_bytes_T_225[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_112 = {shift_bytes_112, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_40 = ll_sv >> shift_bits_112; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_227 = _shift_bytes_T_226[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_113 = _shift_bytes_T_227[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_113 = {shift_bytes_113, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_41 = ll_sv >> shift_bits_113; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_229 = _shift_bytes_T_228[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_114 = _shift_bytes_T_229[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_114 = {shift_bytes_114, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_42 = ll_sv >> shift_bits_114; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_231 = _shift_bytes_T_230[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_115 = _shift_bytes_T_231[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_115 = {shift_bytes_115, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_43 = ll_sv >> shift_bits_115; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_233 = _shift_bytes_T_232[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_116 = _shift_bytes_T_233[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_116 = {shift_bytes_116, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_44 = ll_sv >> shift_bits_116; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_235 = _shift_bytes_T_234[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_117 = _shift_bytes_T_235[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_117 = {shift_bytes_117, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_45 = ll_sv >> shift_bits_117; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_237 = _shift_bytes_T_236[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_118 = _shift_bytes_T_237[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_118 = {shift_bytes_118, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_46 = ll_sv >> shift_bits_118; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_239 = _shift_bytes_T_238[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_119 = _shift_bytes_T_239[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_119 = {shift_bytes_119, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_47 = ll_sv >> shift_bits_119; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_241 = _shift_bytes_T_240[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_120 = _shift_bytes_T_241[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_120 = {shift_bytes_120, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_48 = ll_sv >> shift_bits_120; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_243 = _shift_bytes_T_242[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_121 = _shift_bytes_T_243[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_121 = {shift_bytes_121, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_49 = ll_sv >> shift_bits_121; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_245 = _shift_bytes_T_244[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_122 = _shift_bytes_T_245[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_122 = {shift_bytes_122, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_50 = ll_sv >> shift_bits_122; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_247 = _shift_bytes_T_246[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_123 = _shift_bytes_T_247[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_123 = {shift_bytes_123, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_51 = ll_sv >> shift_bits_123; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_249 = _shift_bytes_T_248[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_124 = _shift_bytes_T_249[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_124 = {shift_bytes_124, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_52 = ll_sv >> shift_bits_124; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_251 = _shift_bytes_T_250[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_125 = _shift_bytes_T_251[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_125 = {shift_bytes_125, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_53 = ll_sv >> shift_bits_125; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_253 = _shift_bytes_T_252[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_126 = _shift_bytes_T_253[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_126 = {shift_bytes_126, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_54 = ll_sv >> shift_bits_126; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_255 = _shift_bytes_T_254[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_127 = _shift_bytes_T_255[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_127 = {shift_bytes_127, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_55 = ll_sv >> shift_bits_127; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_257 = _shift_bytes_T_256[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_128 = _shift_bytes_T_257[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_128 = {shift_bytes_128, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_56 = ll_sv >> shift_bits_128; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_259 = _shift_bytes_T_258[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_129 = _shift_bytes_T_259[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_129 = {shift_bytes_129, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_57 = ll_sv >> shift_bits_129; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_261 = _shift_bytes_T_260[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_130 = _shift_bytes_T_261[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_130 = {shift_bytes_130, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_58 = ll_sv >> shift_bits_130; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_263 = _shift_bytes_T_262[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_131 = _shift_bytes_T_263[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_131 = {shift_bytes_131, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_59 = ll_sv >> shift_bits_131; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_265 = _shift_bytes_T_264[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_132 = _shift_bytes_T_265[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_132 = {shift_bytes_132, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_60 = ll_sv >> shift_bits_132; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_267 = _shift_bytes_T_266[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_133 = _shift_bytes_T_267[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_133 = {shift_bytes_133, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_61 = ll_sv >> shift_bits_133; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_269 = _shift_bytes_T_268[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_134 = _shift_bytes_T_269[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_134 = {shift_bytes_134, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_62 = ll_sv >> shift_bits_134; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] wire [63:0] _shift_bytes_T_271 = _shift_bytes_T_270[63:0]; // @[FSECompressorDicBuilder.scala:739:38] wire [2:0] shift_bytes_135 = _shift_bytes_T_271[2:0]; // @[FSECompressorDicBuilder.scala:739:{38,47}] wire [5:0] shift_bits_135 = {shift_bytes_135, 3'h0}; // @[FSECompressorDicBuilder.scala:739:47, :740:44] wire [63:0] _ll_tableSymbol_T_63 = ll_sv >> shift_bits_135; // @[FSECompressorDicBuilder.scala:404:22, :740:44, :741:50] reg [63:0] loginfo_cycles_148; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_296 = {1'h0, loginfo_cycles_148} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_297 = _loginfo_cycles_T_296[63:0]; // @[Util.scala:19:38] wire _T_1505 = dicBuilderState == 4'h5; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire [63:0] _ll_s_T_3 = _ll_s_T_2[63:0]; // @[FSECompressorDicBuilder.scala:757:20] wire [5:0] _s_T = ll_s[5:0]; // @[FSECompressorDicBuilder.scala:403:21] wire [63:0][7:0] _GEN_172 = {{ll_tableSymbol_63}, {ll_tableSymbol_62}, {ll_tableSymbol_61}, {ll_tableSymbol_60}, {ll_tableSymbol_59}, {ll_tableSymbol_58}, {ll_tableSymbol_57}, {ll_tableSymbol_56}, {ll_tableSymbol_55}, {ll_tableSymbol_54}, {ll_tableSymbol_53}, {ll_tableSymbol_52}, {ll_tableSymbol_51}, {ll_tableSymbol_50}, {ll_tableSymbol_49}, {ll_tableSymbol_48}, {ll_tableSymbol_47}, {ll_tableSymbol_46}, {ll_tableSymbol_45}, {ll_tableSymbol_44}, {ll_tableSymbol_43}, {ll_tableSymbol_42}, {ll_tableSymbol_41}, {ll_tableSymbol_40}, {ll_tableSymbol_39}, {ll_tableSymbol_38}, {ll_tableSymbol_37}, {ll_tableSymbol_36}, {ll_tableSymbol_35}, {ll_tableSymbol_34}, {ll_tableSymbol_33}, {ll_tableSymbol_32}, {ll_tableSymbol_31}, {ll_tableSymbol_30}, {ll_tableSymbol_29}, {ll_tableSymbol_28}, {ll_tableSymbol_27}, {ll_tableSymbol_26}, {ll_tableSymbol_25}, {ll_tableSymbol_24}, {ll_tableSymbol_23}, {ll_tableSymbol_22}, {ll_tableSymbol_21}, {ll_tableSymbol_20}, {ll_tableSymbol_19}, {ll_tableSymbol_18}, {ll_tableSymbol_17}, {ll_tableSymbol_16}, {ll_tableSymbol_15}, {ll_tableSymbol_14}, {ll_tableSymbol_13}, {ll_tableSymbol_12}, {ll_tableSymbol_11}, {ll_tableSymbol_10}, {ll_tableSymbol_9}, {ll_tableSymbol_8}, {ll_tableSymbol_7}, {ll_tableSymbol_6}, {ll_tableSymbol_5}, {ll_tableSymbol_4}, {ll_tableSymbol_3}, {ll_tableSymbol_2}, {ll_tableSymbol_1}, {ll_tableSymbol_0}}; // @[FSECompressorDicBuilder.scala:383:31] wire [3:0] _ll_cumulReg_T = _GEN_172[_s_T][3:0]; wire [15:0][15:0] _GEN_173 = {{ll_cumulReg_0}, {ll_cumulReg_0}, {ll_cumulReg_0}, {ll_cumulReg_12}, {ll_cumulReg_11}, {ll_cumulReg_10}, {ll_cumulReg_9}, {ll_cumulReg_8}, {ll_cumulReg_7}, {ll_cumulReg_6}, {ll_cumulReg_5}, {ll_cumulReg_4}, {ll_cumulReg_3}, {ll_cumulReg_2}, {ll_cumulReg_1}, {ll_cumulReg_0}}; // @[FSECompressorDicBuilder.scala:394:28, :759:40] wire [16:0] _ll_cumulReg_T_1 = {1'h0, _GEN_173[_ll_cumulReg_T]} + 17'h1; // @[FSECompressorDicBuilder.scala:759:40] wire [15:0] _ll_cumulReg_T_2 = _ll_cumulReg_T_1[15:0]; // @[FSECompressorDicBuilder.scala:759:40] wire [64:0] _ll_tableU16_T = _GEN_105 + 65'h40; // @[FSECompressorDicBuilder.scala:716:22, :760:51] wire [63:0] _ll_tableU16_T_1 = _ll_tableU16_T[63:0]; // @[FSECompressorDicBuilder.scala:760:51] wire _T_1512 = dicBuilderState == 4'h6; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire [63:0] _ll_s_T_5 = _ll_s_T_4[63:0]; // @[FSECompressorDicBuilder.scala:768:20] wire [32:0] _GEN_174 = {1'h0, ll_total}; // @[FSECompressorDicBuilder.scala:414:25, :774:54] wire [32:0] _ll_symbolTTDeltaFindState_T = _GEN_174 - 33'h1; // @[FSECompressorDicBuilder.scala:774:54] wire [31:0] _ll_symbolTTDeltaFindState_T_1 = _ll_symbolTTDeltaFindState_T[31:0]; // @[FSECompressorDicBuilder.scala:774:54] wire [31:0] _ll_symbolTTDeltaFindState_T_2 = _ll_symbolTTDeltaFindState_T_1; // @[FSECompressorDicBuilder.scala:774:{54,61}] wire [32:0] _ll_total_T = _GEN_174 + 33'h1; // @[FSECompressorDicBuilder.scala:774:54, :775:30] wire [31:0] _ll_total_T_1 = _ll_total_T[31:0]; // @[FSECompressorDicBuilder.scala:775:30] wire [32:0] _GEN_175 = {1'h0, normCount}; // @[FSECompressorDicBuilder.scala:415:23, :777:65] wire [32:0] _maxBitsOut_T = _GEN_175 - 33'h1; // @[FSECompressorDicBuilder.scala:777:65] wire [31:0] _maxBitsOut_T_1 = _maxBitsOut_T[31:0]; // @[FSECompressorDicBuilder.scala:777:65] wire [15:0] _maxBitsOut_highBit_T_2 = _maxBitsOut_T_1[31:16]; // @[FSECompressorDicBuilder.scala:52:49, :777:65] wire [31:0] _maxBitsOut_highBit_T_3 = {16'h0, _maxBitsOut_highBit_T_2}; // @[FSECompressorDicBuilder.scala:52:49] wire [15:0] _maxBitsOut_highBit_T_4 = _maxBitsOut_T_1[15:0]; // @[FSECompressorDicBuilder.scala:52:49, :777:65] wire [31:0] _maxBitsOut_highBit_T_5 = {_maxBitsOut_highBit_T_4, 16'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_7 = _maxBitsOut_highBit_T_5 & 32'hFFFF0000; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_8 = _maxBitsOut_highBit_T_3 | _maxBitsOut_highBit_T_7; // @[FSECompressorDicBuilder.scala:52:49] wire [23:0] _maxBitsOut_highBit_T_12 = _maxBitsOut_highBit_T_8[31:8]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_13 = {8'h0, _maxBitsOut_highBit_T_12 & 24'hFF00FF}; // @[FSECompressorDicBuilder.scala:52:49] wire [23:0] _maxBitsOut_highBit_T_14 = _maxBitsOut_highBit_T_8[23:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_15 = {_maxBitsOut_highBit_T_14, 8'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_17 = _maxBitsOut_highBit_T_15 & 32'hFF00FF00; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_18 = _maxBitsOut_highBit_T_13 | _maxBitsOut_highBit_T_17; // @[FSECompressorDicBuilder.scala:52:49] wire [27:0] _maxBitsOut_highBit_T_22 = _maxBitsOut_highBit_T_18[31:4]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_23 = {4'h0, _maxBitsOut_highBit_T_22 & 28'hF0F0F0F}; // @[FSECompressorDicBuilder.scala:52:49] wire [27:0] _maxBitsOut_highBit_T_24 = _maxBitsOut_highBit_T_18[27:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_25 = {_maxBitsOut_highBit_T_24, 4'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_27 = _maxBitsOut_highBit_T_25 & 32'hF0F0F0F0; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_28 = _maxBitsOut_highBit_T_23 | _maxBitsOut_highBit_T_27; // @[FSECompressorDicBuilder.scala:52:49] wire [29:0] _maxBitsOut_highBit_T_32 = _maxBitsOut_highBit_T_28[31:2]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_33 = {2'h0, _maxBitsOut_highBit_T_32 & 30'h33333333}; // @[FSECompressorDicBuilder.scala:52:49] wire [29:0] _maxBitsOut_highBit_T_34 = _maxBitsOut_highBit_T_28[29:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_35 = {_maxBitsOut_highBit_T_34, 2'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_37 = _maxBitsOut_highBit_T_35 & 32'hCCCCCCCC; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_38 = _maxBitsOut_highBit_T_33 | _maxBitsOut_highBit_T_37; // @[FSECompressorDicBuilder.scala:52:49] wire [30:0] _maxBitsOut_highBit_T_42 = _maxBitsOut_highBit_T_38[31:1]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_43 = {1'h0, _maxBitsOut_highBit_T_42 & 31'h55555555}; // @[FSECompressorDicBuilder.scala:52:49] wire [30:0] _maxBitsOut_highBit_T_44 = _maxBitsOut_highBit_T_38[30:0]; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_45 = {_maxBitsOut_highBit_T_44, 1'h0}; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_47 = _maxBitsOut_highBit_T_45 & 32'hAAAAAAAA; // @[FSECompressorDicBuilder.scala:52:49] wire [31:0] _maxBitsOut_highBit_T_48 = _maxBitsOut_highBit_T_43 | _maxBitsOut_highBit_T_47; // @[FSECompressorDicBuilder.scala:52:49] wire _maxBitsOut_highBit_T_49 = _maxBitsOut_highBit_T_48[0]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_50 = _maxBitsOut_highBit_T_48[1]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_51 = _maxBitsOut_highBit_T_48[2]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_52 = _maxBitsOut_highBit_T_48[3]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_53 = _maxBitsOut_highBit_T_48[4]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_54 = _maxBitsOut_highBit_T_48[5]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_55 = _maxBitsOut_highBit_T_48[6]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_56 = _maxBitsOut_highBit_T_48[7]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_57 = _maxBitsOut_highBit_T_48[8]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_58 = _maxBitsOut_highBit_T_48[9]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_59 = _maxBitsOut_highBit_T_48[10]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_60 = _maxBitsOut_highBit_T_48[11]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_61 = _maxBitsOut_highBit_T_48[12]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_62 = _maxBitsOut_highBit_T_48[13]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_63 = _maxBitsOut_highBit_T_48[14]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_64 = _maxBitsOut_highBit_T_48[15]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_65 = _maxBitsOut_highBit_T_48[16]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_66 = _maxBitsOut_highBit_T_48[17]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_67 = _maxBitsOut_highBit_T_48[18]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_68 = _maxBitsOut_highBit_T_48[19]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_69 = _maxBitsOut_highBit_T_48[20]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_70 = _maxBitsOut_highBit_T_48[21]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_71 = _maxBitsOut_highBit_T_48[22]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_72 = _maxBitsOut_highBit_T_48[23]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_73 = _maxBitsOut_highBit_T_48[24]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_74 = _maxBitsOut_highBit_T_48[25]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_75 = _maxBitsOut_highBit_T_48[26]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_76 = _maxBitsOut_highBit_T_48[27]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_77 = _maxBitsOut_highBit_T_48[28]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_78 = _maxBitsOut_highBit_T_48[29]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_79 = _maxBitsOut_highBit_T_48[30]; // @[OneHot.scala:48:45] wire _maxBitsOut_highBit_T_80 = _maxBitsOut_highBit_T_48[31]; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_81 = {4'hF, ~_maxBitsOut_highBit_T_79}; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_82 = _maxBitsOut_highBit_T_78 ? 5'h1D : _maxBitsOut_highBit_T_81; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_83 = _maxBitsOut_highBit_T_77 ? 5'h1C : _maxBitsOut_highBit_T_82; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_84 = _maxBitsOut_highBit_T_76 ? 5'h1B : _maxBitsOut_highBit_T_83; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_85 = _maxBitsOut_highBit_T_75 ? 5'h1A : _maxBitsOut_highBit_T_84; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_86 = _maxBitsOut_highBit_T_74 ? 5'h19 : _maxBitsOut_highBit_T_85; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_87 = _maxBitsOut_highBit_T_73 ? 5'h18 : _maxBitsOut_highBit_T_86; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_88 = _maxBitsOut_highBit_T_72 ? 5'h17 : _maxBitsOut_highBit_T_87; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_89 = _maxBitsOut_highBit_T_71 ? 5'h16 : _maxBitsOut_highBit_T_88; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_90 = _maxBitsOut_highBit_T_70 ? 5'h15 : _maxBitsOut_highBit_T_89; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_91 = _maxBitsOut_highBit_T_69 ? 5'h14 : _maxBitsOut_highBit_T_90; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_92 = _maxBitsOut_highBit_T_68 ? 5'h13 : _maxBitsOut_highBit_T_91; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_93 = _maxBitsOut_highBit_T_67 ? 5'h12 : _maxBitsOut_highBit_T_92; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_94 = _maxBitsOut_highBit_T_66 ? 5'h11 : _maxBitsOut_highBit_T_93; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_95 = _maxBitsOut_highBit_T_65 ? 5'h10 : _maxBitsOut_highBit_T_94; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_96 = _maxBitsOut_highBit_T_64 ? 5'hF : _maxBitsOut_highBit_T_95; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_97 = _maxBitsOut_highBit_T_63 ? 5'hE : _maxBitsOut_highBit_T_96; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_98 = _maxBitsOut_highBit_T_62 ? 5'hD : _maxBitsOut_highBit_T_97; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_99 = _maxBitsOut_highBit_T_61 ? 5'hC : _maxBitsOut_highBit_T_98; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_100 = _maxBitsOut_highBit_T_60 ? 5'hB : _maxBitsOut_highBit_T_99; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_101 = _maxBitsOut_highBit_T_59 ? 5'hA : _maxBitsOut_highBit_T_100; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_102 = _maxBitsOut_highBit_T_58 ? 5'h9 : _maxBitsOut_highBit_T_101; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_103 = _maxBitsOut_highBit_T_57 ? 5'h8 : _maxBitsOut_highBit_T_102; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_104 = _maxBitsOut_highBit_T_56 ? 5'h7 : _maxBitsOut_highBit_T_103; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_105 = _maxBitsOut_highBit_T_55 ? 5'h6 : _maxBitsOut_highBit_T_104; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_106 = _maxBitsOut_highBit_T_54 ? 5'h5 : _maxBitsOut_highBit_T_105; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_107 = _maxBitsOut_highBit_T_53 ? 5'h4 : _maxBitsOut_highBit_T_106; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_108 = _maxBitsOut_highBit_T_52 ? 5'h3 : _maxBitsOut_highBit_T_107; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_109 = _maxBitsOut_highBit_T_51 ? 5'h2 : _maxBitsOut_highBit_T_108; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_110 = _maxBitsOut_highBit_T_50 ? 5'h1 : _maxBitsOut_highBit_T_109; // @[OneHot.scala:48:45] wire [4:0] _maxBitsOut_highBit_T_111 = _maxBitsOut_highBit_T_49 ? 5'h0 : _maxBitsOut_highBit_T_110; // @[OneHot.scala:48:45] wire [5:0] _maxBitsOut_highBit_T_112 = 6'h1F - {1'h0, _maxBitsOut_highBit_T_111}; // @[Mux.scala:50:70] wire [4:0] maxBitsOut_highBit = _maxBitsOut_highBit_T_112[4:0]; // @[FSECompressorDicBuilder.scala:52:24] wire [5:0] _maxBitsOut_T_2 = 6'h6 - {1'h0, maxBitsOut_highBit}; // @[FSECompressorDicBuilder.scala:52:24, :777:39] wire [4:0] maxBitsOut = _maxBitsOut_T_2[4:0]; // @[FSECompressorDicBuilder.scala:777:39] wire [3:0] _minStatePlus_T = maxBitsOut[3:0]; // @[FSECompressorDicBuilder.scala:777:39, :778:51] wire [46:0] minStatePlus = {15'h0, normCount} << _minStatePlus_T; // @[FSECompressorDicBuilder.scala:415:23, :778:{38,51}] wire [35:0] _ll_symbolTTDeltaNbBits_T = {15'h0, maxBitsOut, 16'h0}; // @[FSECompressorDicBuilder.scala:777:39, :779:53] wire [47:0] _ll_symbolTTDeltaNbBits_T_1 = {12'h0, _ll_symbolTTDeltaNbBits_T} - {1'h0, minStatePlus}; // @[FSECompressorDicBuilder.scala:778:38, :779:{53,62}] wire [46:0] _ll_symbolTTDeltaNbBits_T_2 = _ll_symbolTTDeltaNbBits_T_1[46:0]; // @[FSECompressorDicBuilder.scala:779:62] wire [32:0] _ll_symbolTTDeltaFindState_T_3 = _GEN_174 - _GEN_175; // @[FSECompressorDicBuilder.scala:774:54, :777:65, :780:54] wire [31:0] _ll_symbolTTDeltaFindState_T_4 = _ll_symbolTTDeltaFindState_T_3[31:0]; // @[FSECompressorDicBuilder.scala:780:54] wire [31:0] _ll_symbolTTDeltaFindState_T_5 = _ll_symbolTTDeltaFindState_T_4; // @[FSECompressorDicBuilder.scala:780:{54,67}] wire [32:0] _ll_total_T_2 = _GEN_174 + _GEN_175; // @[FSECompressorDicBuilder.scala:774:54, :777:65, :781:30] wire [31:0] _ll_total_T_3 = _ll_total_T_2[31:0]; // @[FSECompressorDicBuilder.scala:781:30] wire _T_1522 = dicBuilderState == 4'h7; // @[FSECompressorDicBuilder.scala:156:32, :551:28] wire _GEN_176 = ~(|dicBuilderState) | _T_384 | _T_390 | _T_611 | _T_685 | _T_1505 | _T_1512; // @[FSECompressorDicBuilder.scala:156:32, :198:25, :316:25, :494:31, :551:28] wire _T_1526 = symbol < alphabetSize & (|(remaining[31:1])); // @[FSECompressorDicBuilder.scala:463:26, :465:23, :466:42, :799:{23,39,53}] wire [63:0] _GEN_177 = {16'h0, bitStream[63:16]}; // @[FSECompressorDicBuilder.scala:468:26, :803:38] wire [63:0] _bitStream_T; // @[FSECompressorDicBuilder.scala:803:38] assign _bitStream_T = _GEN_177; // @[FSECompressorDicBuilder.scala:803:38] wire [63:0] _bitStream_T_1; // @[FSECompressorDicBuilder.scala:816:38] assign _bitStream_T_1 = _GEN_177; // @[FSECompressorDicBuilder.scala:803:38, :816:38] wire [7:0] _GEN_178 = {1'h0, bitCount}; // @[FSECompressorDicBuilder.scala:469:25, :804:36] wire [7:0] _bitCount_T = _GEN_178 - 8'h10; // @[FSECompressorDicBuilder.scala:804:36] wire [6:0] _bitCount_T_1 = _bitCount_T[6:0]; // @[FSECompressorDicBuilder.scala:804:36] reg [63:0] loginfo_cycles_149; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_298 = {1'h0, loginfo_cycles_149} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_299 = _loginfo_cycles_T_298[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_150; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_300 = {1'h0, loginfo_cycles_150} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_301 = _loginfo_cycles_T_300[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_151; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_302 = {1'h0, loginfo_cycles_151} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_303 = _loginfo_cycles_T_302[63:0]; // @[Util.scala:19:38] wire _GEN_179 = writeBitStream | writeBitStreamPrev0; // @[FSECompressorDicBuilder.scala:470:31, :476:36, :481:36, :800:32, :812:46, :813:45, :823:46] reg [63:0] loginfo_cycles_152; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_304 = {1'h0, loginfo_cycles_152} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_305 = _loginfo_cycles_T_304[63:0]; // @[Util.scala:19:38] wire [3:0] _cur_norm_count_T = symbol[3:0]; // @[FSECompressorDicBuilder.scala:465:23] wire [3:0] _count_T = symbol[3:0]; // @[FSECompressorDicBuilder.scala:465:23] reg [63:0] loginfo_cycles_153; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_306 = {1'h0, loginfo_cycles_153} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_307 = _loginfo_cycles_T_306[63:0]; // @[Util.scala:19:38] wire [32:0] _GEN_180 = {1'h0, symbol}; // @[FSECompressorDicBuilder.scala:465:23, :835:34] wire [32:0] _symbol_T = _GEN_180 + 33'h1; // @[FSECompressorDicBuilder.scala:835:34] wire [31:0] _symbol_T_1 = _symbol_T[31:0]; // @[FSECompressorDicBuilder.scala:835:34] wire [32:0] _GEN_181 = {1'h0, start}; // @[FSECompressorDicBuilder.scala:471:22, :842:37] wire [32:0] _start_T = _GEN_181 + 33'h18; // @[FSECompressorDicBuilder.scala:842:37, :843:32] wire [31:0] _start_T_1 = _start_T[31:0]; // @[FSECompressorDicBuilder.scala:843:32] wire [142:0] _bitStream_T_2 = 143'hFFFF << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :844:64] wire [143:0] _bitStream_T_3 = {80'h0, bitStream} + {1'h0, _bitStream_T_2}; // @[FSECompressorDicBuilder.scala:468:26, :844:{40,64}] wire [142:0] _bitStream_T_4 = _bitStream_T_3[142:0]; // @[FSECompressorDicBuilder.scala:844:40] reg [63:0] loginfo_cycles_154; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_308 = {1'h0, loginfo_cycles_154} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_309 = _loginfo_cycles_T_308[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_155; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_310 = {1'h0, loginfo_cycles_155} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_311 = _loginfo_cycles_T_310[63:0]; // @[Util.scala:19:38] wire [32:0] _start_T_2 = _GEN_181 + 33'h3; // @[FSECompressorDicBuilder.scala:842:37, :852:37, :853:32] wire [31:0] _start_T_3 = _start_T_2[31:0]; // @[FSECompressorDicBuilder.scala:853:32] wire [128:0] _bitStream_T_5 = 129'h3 << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :854:47] wire [129:0] _bitStream_T_6 = {66'h0, bitStream} + {1'h0, _bitStream_T_5}; // @[FSECompressorDicBuilder.scala:468:26, :854:{40,47}] wire [128:0] _bitStream_T_7 = _bitStream_T_6[128:0]; // @[FSECompressorDicBuilder.scala:854:40] wire [7:0] _GEN_182 = _GEN_178 + 8'h2; // @[FSECompressorDicBuilder.scala:804:36, :855:38] wire [7:0] _bitCount_T_2; // @[FSECompressorDicBuilder.scala:855:38] assign _bitCount_T_2 = _GEN_182; // @[FSECompressorDicBuilder.scala:855:38] wire [7:0] _bitCount_T_4; // @[FSECompressorDicBuilder.scala:863:36] assign _bitCount_T_4 = _GEN_182; // @[FSECompressorDicBuilder.scala:855:38, :863:36] wire [6:0] _bitCount_T_3 = _bitCount_T_2[6:0]; // @[FSECompressorDicBuilder.scala:855:38] reg [63:0] loginfo_cycles_156; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_312 = {1'h0, loginfo_cycles_156} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_313 = _loginfo_cycles_T_312[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_157; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_314 = {1'h0, loginfo_cycles_157} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_315 = _loginfo_cycles_T_314[63:0]; // @[Util.scala:19:38] wire [32:0] _bitStream_T_8 = _GEN_180 - _GEN_181; // @[FSECompressorDicBuilder.scala:835:34, :842:37, :862:49] wire [31:0] _bitStream_T_9 = _bitStream_T_8[31:0]; // @[FSECompressorDicBuilder.scala:862:49] wire [158:0] _bitStream_T_10 = {127'h0, _bitStream_T_9} << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :844:64, :862:{49,58}] wire [159:0] _GEN_183 = {96'h0, bitStream}; // @[FSECompressorDicBuilder.scala:468:26, :862:38] wire [159:0] _bitStream_T_11 = _GEN_183 + {1'h0, _bitStream_T_10}; // @[FSECompressorDicBuilder.scala:862:{38,58}] wire [158:0] _bitStream_T_12 = _bitStream_T_11[158:0]; // @[FSECompressorDicBuilder.scala:862:38] wire [6:0] _bitCount_T_5 = _bitCount_T_4[6:0]; // @[FSECompressorDicBuilder.scala:863:36] reg [63:0] loginfo_cycles_158; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_316 = {1'h0, loginfo_cycles_158} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_317 = _loginfo_cycles_T_316[63:0]; // @[Util.scala:19:38] wire [32:0] _symbol_T_2 = _GEN_180 + 33'h1; // @[FSECompressorDicBuilder.scala:835:34, :878:30] wire [31:0] _symbol_T_3 = _symbol_T_2[31:0]; // @[FSECompressorDicBuilder.scala:878:30] wire [32:0] _max_T = {threshold, 1'h0}; // @[FSECompressorDicBuilder.scala:464:26, :879:35] wire [33:0] _max_T_1 = {1'h0, _max_T} - 34'h1; // @[FSECompressorDicBuilder.scala:879:{35,43}] wire [32:0] _max_T_2 = _max_T_1[32:0]; // @[FSECompressorDicBuilder.scala:879:43] wire [33:0] _max_T_3 = {1'h0, _max_T_2} - {2'h0, remaining}; // @[FSECompressorDicBuilder.scala:463:26, :879:{43,50}] wire [32:0] max = _max_T_3[32:0]; // @[FSECompressorDicBuilder.scala:879:50] wire [32:0] _nxt_remaining_T = {1'h0, remaining} - {17'h0, _GEN_85[_count_T]}; // @[FSECompressorDicBuilder.scala:416:13, :463:26, :882:43] wire [31:0] nxt_remaining = _nxt_remaining_T[31:0]; // @[FSECompressorDicBuilder.scala:882:43] wire _GEN_184 = writeBitStream | writeBitStreamPrev0 | previousIs0; // @[FSECompressorDicBuilder.scala:467:28, :470:31, :476:36, :494:31, :800:32, :813:45, :824:37, :883:23] wire [16:0] _count1_T = {1'h0, _GEN_85[_count_T]} + 17'h1; // @[FSECompressorDicBuilder.scala:416:13, :882:43, :885:32] wire [15:0] count1 = _count1_T[15:0]; // @[FSECompressorDicBuilder.scala:885:32] wire _count1_max_T = {16'h0, count1} >= threshold; // @[FSECompressorDicBuilder.scala:464:26, :885:32, :886:41] wire [33:0] _count1_max_T_1 = {18'h0, count1} + {1'h0, max}; // @[FSECompressorDicBuilder.scala:879:50, :885:32, :886:62] wire [32:0] _count1_max_T_2 = _count1_max_T_1[32:0]; // @[FSECompressorDicBuilder.scala:886:62] wire [32:0] count1_max = _count1_max_T ? _count1_max_T_2 : {17'h0, count1}; // @[FSECompressorDicBuilder.scala:882:43, :885:32, :886:{33,41,62}] wire [32:0] _GEN_185 = {1'h0, nbBits}; // @[FSECompressorDicBuilder.scala:462:23, :887:41] wire [32:0] _nxt_bitCount_T = {26'h0, bitCount} + _GEN_185; // @[FSECompressorDicBuilder.scala:469:25, :887:41] wire [31:0] _nxt_bitCount_T_1 = _nxt_bitCount_T[31:0]; // @[FSECompressorDicBuilder.scala:887:41] wire _nxt_bitCount_T_2 = count1_max < max; // @[FSECompressorDicBuilder.scala:879:50, :886:33, :887:67] wire _nxt_bitCount_T_3 = _nxt_bitCount_T_2; // @[FSECompressorDicBuilder.scala:887:{55,67}] wire [32:0] _nxt_bitCount_T_4 = {1'h0, _nxt_bitCount_T_1} - {32'h0, _nxt_bitCount_T_3}; // @[FSECompressorDicBuilder.scala:887:{41,50,55}] wire [31:0] nxt_bitCount = _nxt_bitCount_T_4[31:0]; // @[FSECompressorDicBuilder.scala:887:50] wire [159:0] _bitStream_T_13 = {127'h0, count1_max} << bitCount; // @[FSECompressorDicBuilder.scala:469:25, :844:64, :886:33, :888:50] wire [160:0] _bitStream_T_14 = {97'h0, bitStream} + {1'h0, _bitStream_T_13}; // @[FSECompressorDicBuilder.scala:468:26, :888:{36,50}] wire [159:0] _bitStream_T_15 = _bitStream_T_14[159:0]; // @[FSECompressorDicBuilder.scala:888:36] wire _writeBitStream_T = nxt_bitCount > 32'h10; // @[FSECompressorDicBuilder.scala:887:50, :890:44] wire _previousIs0_T = count1_max == 33'h1; // @[FSECompressorDicBuilder.scala:886:33, :892:40] reg [63:0] loginfo_cycles_159; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_318 = {1'h0, loginfo_cycles_159} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_319 = _loginfo_cycles_T_318[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_160; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_320 = {1'h0, loginfo_cycles_160} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_321 = _loginfo_cycles_T_320[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_161; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_322 = {1'h0, loginfo_cycles_161} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_323 = _loginfo_cycles_T_322[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_162; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_324 = {1'h0, loginfo_cycles_162} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_325 = _loginfo_cycles_T_324[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_163; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_326 = {1'h0, loginfo_cycles_163} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_327 = _loginfo_cycles_T_326[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_164; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_328 = {1'h0, loginfo_cycles_164} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_329 = _loginfo_cycles_T_328[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_165; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_330 = {1'h0, loginfo_cycles_165} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_331 = _loginfo_cycles_T_330[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_166; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_332 = {1'h0, loginfo_cycles_166} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_333 = _loginfo_cycles_T_332[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_167; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_334 = {1'h0, loginfo_cycles_167} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_335 = _loginfo_cycles_T_334[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_168; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_336 = {1'h0, loginfo_cycles_168} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_337 = _loginfo_cycles_T_336[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_169; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_338 = {1'h0, loginfo_cycles_169} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_339 = _loginfo_cycles_T_338[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_170; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_340 = {1'h0, loginfo_cycles_170} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_341 = _loginfo_cycles_T_340[63:0]; // @[Util.scala:19:38] wire _shifted_threshold_small_or_eq_remaining_0_T = nxt_remaining < shifted_thresholds_0; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_0_T_1 = _shifted_threshold_small_or_eq_remaining_0_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] wire _GEN_186 = _GEN_176 | ~_T_1522 | ~write_header_started | ~_T_1526 | _GEN_184; // @[FSECompressorDicBuilder.scala:461:37, :490:57, :494:31, :551:28, :791:36, :799:{39,61}, :800:32, :813:45, :824:37, :883:23] assign shifted_threshold_small_or_eq_remaining_0 = _GEN_186 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_0_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_1_T = nxt_remaining < shifted_thresholds_1; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_1_T_1 = _shifted_threshold_small_or_eq_remaining_1_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_1 = _GEN_186 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_1_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_2_T = nxt_remaining < shifted_thresholds_2; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_2_T_1 = _shifted_threshold_small_or_eq_remaining_2_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_2 = _GEN_186 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_2_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_3_T = nxt_remaining < shifted_thresholds_3; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_3_T_1 = _shifted_threshold_small_or_eq_remaining_3_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_3 = _GEN_186 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_3_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_4_T = nxt_remaining < shifted_thresholds_4; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_4_T_1 = _shifted_threshold_small_or_eq_remaining_4_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_4 = _GEN_186 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_4_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_5_T = nxt_remaining < shifted_thresholds_5; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_5_T_1 = _shifted_threshold_small_or_eq_remaining_5_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_5 = _GEN_186 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_5_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire _shifted_threshold_small_or_eq_remaining_6_T = nxt_remaining < shifted_thresholds_6; // @[FSECompressorDicBuilder.scala:484:36, :882:43, :908:79] wire _shifted_threshold_small_or_eq_remaining_6_T_1 = _shifted_threshold_small_or_eq_remaining_6_T; // @[FSECompressorDicBuilder.scala:908:{64,79}] assign shifted_threshold_small_or_eq_remaining_6 = _GEN_186 ? 32'h0 : {31'h0, _shifted_threshold_small_or_eq_remaining_6_T_1}; // @[FSECompressorDicBuilder.scala:490:57, :551:28, :791:36, :799:61, :800:32, :908:{58,64}] wire [2:0] _threshold_T = nxt_shifted_threshold_idx[2:0]; // @[FSECompressorDicBuilder.scala:491:84] wire [32:0] _nbBits_T = _GEN_185 - {1'h0, nxt_shifted_threshold_idx}; // @[FSECompressorDicBuilder.scala:491:84, :887:41, :911:30] wire [31:0] _nbBits_T_1 = _nbBits_T[31:0]; // @[FSECompressorDicBuilder.scala:911:30] wire _GEN_187 = ~_T_1526 | writeBitStream | writeBitStreamPrev0; // @[FSECompressorDicBuilder.scala:470:31, :476:36, :494:31, :799:{39,61}, :800:32, :810:36, :813:45, :914:34] assign io_header_writes_valid_0 = ~_GEN_176 & _T_1522 & write_header_started & _GEN_187; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :479:26, :494:31, :551:28, :791:36, :799:61, :800:32, :810:36, :813:45, :914:34] assign io_header_writes_bits_data_0 = _GEN_176 | ~(_T_1522 & write_header_started & _GEN_187) ? 256'h0 : {192'h0, bitStream}; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :468:26, :480:30, :494:31, :551:28, :791:36, :799:61, :800:32, :810:36, :811:40, :813:45, :914:34] wire [7:0] _io_header_writes_bits_validbytes_T = _GEN_178 + 8'h7; // @[FSECompressorDicBuilder.scala:804:36, :916:58] wire [6:0] _io_header_writes_bits_validbytes_T_1 = _io_header_writes_bits_validbytes_T[6:0]; // @[FSECompressorDicBuilder.scala:916:58] wire [6:0] _io_header_writes_bits_validbytes_T_2 = {3'h0, _io_header_writes_bits_validbytes_T_1[6:3]}; // @[FSECompressorDicBuilder.scala:916:{58,65}] assign io_header_writes_bits_validbytes_0 = _GEN_176 | ~(_T_1522 & write_header_started) ? 6'h0 : _T_1526 ? {4'h0, _GEN_179, 1'h0} : _io_header_writes_bits_validbytes_T_2[5:0]; // @[FSECompressorDicBuilder.scala:39:7, :461:37, :481:36, :494:31, :551:28, :791:36, :799:{39,61}, :800:32, :812:46, :813:45, :823:46, :916:{44,65}] wire _GEN_188 = ~(|dicBuilderState) | _T_384 | _T_390 | _T_611 | _T_685 | _T_1505 | _T_1512 | _T_1522; // @[FSECompressorDicBuilder.scala:156:32, :198:25, :316:25, :494:31, :551:28] reg [63:0] loginfo_cycles_171; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_342 = {1'h0, loginfo_cycles_171} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_343 = _loginfo_cycles_T_342[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_172; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_344 = {1'h0, loginfo_cycles_172} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_345 = _loginfo_cycles_T_344[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_173; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_346 = {1'h0, loginfo_cycles_173} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_347 = _loginfo_cycles_T_346[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_174; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_348 = {1'h0, loginfo_cycles_174} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_349 = _loginfo_cycles_T_348[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_175; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_350 = {1'h0, loginfo_cycles_175} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_351 = _loginfo_cycles_T_350[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_176; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_352 = {1'h0, loginfo_cycles_176} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_353 = _loginfo_cycles_T_352[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_177; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_354 = {1'h0, loginfo_cycles_177} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_355 = _loginfo_cycles_T_354[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_178; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_356 = {1'h0, loginfo_cycles_178} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_357 = _loginfo_cycles_T_356[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_179; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_358 = {1'h0, loginfo_cycles_179} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_359 = _loginfo_cycles_T_358[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_180; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_360 = {1'h0, loginfo_cycles_180} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_361 = _loginfo_cycles_T_360[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_181; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_362 = {1'h0, loginfo_cycles_181} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_363 = _loginfo_cycles_T_362[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_182; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_364 = {1'h0, loginfo_cycles_182} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_365 = _loginfo_cycles_T_364[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_183; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_366 = {1'h0, loginfo_cycles_183} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_367 = _loginfo_cycles_T_366[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_184; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_368 = {1'h0, loginfo_cycles_184} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_369 = _loginfo_cycles_T_368[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_185; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_370 = {1'h0, loginfo_cycles_185} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_371 = _loginfo_cycles_T_370[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_186; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_372 = {1'h0, loginfo_cycles_186} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_373 = _loginfo_cycles_T_372[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_187; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_374 = {1'h0, loginfo_cycles_187} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_375 = _loginfo_cycles_T_374[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_188; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_376 = {1'h0, loginfo_cycles_188} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_377 = _loginfo_cycles_T_376[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_189; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_378 = {1'h0, loginfo_cycles_189} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_379 = _loginfo_cycles_T_378[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_190; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_380 = {1'h0, loginfo_cycles_190} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_381 = _loginfo_cycles_T_380[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_191; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_382 = {1'h0, loginfo_cycles_191} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_383 = _loginfo_cycles_T_382[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_192; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_384 = {1'h0, loginfo_cycles_192} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_385 = _loginfo_cycles_T_384[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_193; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_386 = {1'h0, loginfo_cycles_193} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_387 = _loginfo_cycles_T_386[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_194; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_388 = {1'h0, loginfo_cycles_194} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_389 = _loginfo_cycles_T_388[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_195; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_390 = {1'h0, loginfo_cycles_195} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_391 = _loginfo_cycles_T_390[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_196; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_392 = {1'h0, loginfo_cycles_196} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_393 = _loginfo_cycles_T_392[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_197; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_394 = {1'h0, loginfo_cycles_197} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_395 = _loginfo_cycles_T_394[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_198; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_396 = {1'h0, loginfo_cycles_198} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_397 = _loginfo_cycles_T_396[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_199; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_398 = {1'h0, loginfo_cycles_199} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_399 = _loginfo_cycles_T_398[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_200; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_400 = {1'h0, loginfo_cycles_200} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_401 = _loginfo_cycles_T_400[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_201; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_402 = {1'h0, loginfo_cycles_201} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_403 = _loginfo_cycles_T_402[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_202; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_404 = {1'h0, loginfo_cycles_202} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_405 = _loginfo_cycles_T_404[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_203; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_406 = {1'h0, loginfo_cycles_203} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_407 = _loginfo_cycles_T_406[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_204; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_408 = {1'h0, loginfo_cycles_204} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_409 = _loginfo_cycles_T_408[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_205; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_410 = {1'h0, loginfo_cycles_205} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_411 = _loginfo_cycles_T_410[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_206; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_412 = {1'h0, loginfo_cycles_206} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_413 = _loginfo_cycles_T_412[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_207; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_414 = {1'h0, loginfo_cycles_207} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_415 = _loginfo_cycles_T_414[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_208; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_416 = {1'h0, loginfo_cycles_208} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_417 = _loginfo_cycles_T_416[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_209; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_418 = {1'h0, loginfo_cycles_209} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_419 = _loginfo_cycles_T_418[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_210; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_420 = {1'h0, loginfo_cycles_210} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_421 = _loginfo_cycles_T_420[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_211; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_422 = {1'h0, loginfo_cycles_211} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_423 = _loginfo_cycles_T_422[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_212; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_424 = {1'h0, loginfo_cycles_212} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_425 = _loginfo_cycles_T_424[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_213; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_426 = {1'h0, loginfo_cycles_213} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_427 = _loginfo_cycles_T_426[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_214; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_428 = {1'h0, loginfo_cycles_214} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_429 = _loginfo_cycles_T_428[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_215; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_430 = {1'h0, loginfo_cycles_215} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_431 = _loginfo_cycles_T_430[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_216; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_432 = {1'h0, loginfo_cycles_216} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_433 = _loginfo_cycles_T_432[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_217; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_434 = {1'h0, loginfo_cycles_217} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_435 = _loginfo_cycles_T_434[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_218; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_436 = {1'h0, loginfo_cycles_218} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_437 = _loginfo_cycles_T_436[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_219; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_438 = {1'h0, loginfo_cycles_219} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_439 = _loginfo_cycles_T_438[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_220; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_440 = {1'h0, loginfo_cycles_220} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_441 = _loginfo_cycles_T_440[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_221; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_442 = {1'h0, loginfo_cycles_221} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_443 = _loginfo_cycles_T_442[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_222; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_444 = {1'h0, loginfo_cycles_222} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_445 = _loginfo_cycles_T_444[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_223; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_446 = {1'h0, loginfo_cycles_223} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_447 = _loginfo_cycles_T_446[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_224; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_448 = {1'h0, loginfo_cycles_224} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_449 = _loginfo_cycles_T_448[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_225; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_450 = {1'h0, loginfo_cycles_225} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_451 = _loginfo_cycles_T_450[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_226; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_452 = {1'h0, loginfo_cycles_226} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_453 = _loginfo_cycles_T_452[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_227; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_454 = {1'h0, loginfo_cycles_227} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_455 = _loginfo_cycles_T_454[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_228; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_456 = {1'h0, loginfo_cycles_228} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_457 = _loginfo_cycles_T_456[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_229; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_458 = {1'h0, loginfo_cycles_229} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_459 = _loginfo_cycles_T_458[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_230; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_460 = {1'h0, loginfo_cycles_230} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_461 = _loginfo_cycles_T_460[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_231; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_462 = {1'h0, loginfo_cycles_231} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_463 = _loginfo_cycles_T_462[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_232; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_464 = {1'h0, loginfo_cycles_232} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_465 = _loginfo_cycles_T_464[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_233; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_466 = {1'h0, loginfo_cycles_233} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_467 = _loginfo_cycles_T_466[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_234; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_468 = {1'h0, loginfo_cycles_234} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_469 = _loginfo_cycles_T_468[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_235; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_470 = {1'h0, loginfo_cycles_235} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_471 = _loginfo_cycles_T_470[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_236; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_472 = {1'h0, loginfo_cycles_236} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_473 = _loginfo_cycles_T_472[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_237; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_474 = {1'h0, loginfo_cycles_237} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_475 = _loginfo_cycles_T_474[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_238; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_476 = {1'h0, loginfo_cycles_238} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_477 = _loginfo_cycles_T_476[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_239; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_478 = {1'h0, loginfo_cycles_239} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_479 = _loginfo_cycles_T_478[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_240; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_480 = {1'h0, loginfo_cycles_240} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_481 = _loginfo_cycles_T_480[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_241; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_482 = {1'h0, loginfo_cycles_241} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_483 = _loginfo_cycles_T_482[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_242; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_484 = {1'h0, loginfo_cycles_242} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_485 = _loginfo_cycles_T_484[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_243; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_486 = {1'h0, loginfo_cycles_243} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_487 = _loginfo_cycles_T_486[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_244; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_488 = {1'h0, loginfo_cycles_244} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_489 = _loginfo_cycles_T_488[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_245; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_490 = {1'h0, loginfo_cycles_245} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_491 = _loginfo_cycles_T_490[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_246; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_492 = {1'h0, loginfo_cycles_246} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_493 = _loginfo_cycles_T_492[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_247; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_494 = {1'h0, loginfo_cycles_247} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_495 = _loginfo_cycles_T_494[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_248; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_496 = {1'h0, loginfo_cycles_248} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_497 = _loginfo_cycles_T_496[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_249; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_498 = {1'h0, loginfo_cycles_249} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_499 = _loginfo_cycles_T_498[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_250; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_500 = {1'h0, loginfo_cycles_250} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_501 = _loginfo_cycles_T_500[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_251; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_502 = {1'h0, loginfo_cycles_251} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_503 = _loginfo_cycles_T_502[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_252; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_504 = {1'h0, loginfo_cycles_252} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_505 = _loginfo_cycles_T_504[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_253; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_506 = {1'h0, loginfo_cycles_253} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_507 = _loginfo_cycles_T_506[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_254; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_508 = {1'h0, loginfo_cycles_254} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_509 = _loginfo_cycles_T_508[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_255; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_510 = {1'h0, loginfo_cycles_255} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_511 = _loginfo_cycles_T_510[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_256; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_512 = {1'h0, loginfo_cycles_256} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_513 = _loginfo_cycles_T_512[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_257; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_514 = {1'h0, loginfo_cycles_257} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_515 = _loginfo_cycles_T_514[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_258; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_516 = {1'h0, loginfo_cycles_258} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_517 = _loginfo_cycles_T_516[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_259; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_518 = {1'h0, loginfo_cycles_259} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_519 = _loginfo_cycles_T_518[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_260; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_520 = {1'h0, loginfo_cycles_260} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_521 = _loginfo_cycles_T_520[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_261; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_522 = {1'h0, loginfo_cycles_261} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_523 = _loginfo_cycles_T_522[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_262; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_524 = {1'h0, loginfo_cycles_262} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_525 = _loginfo_cycles_T_524[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_263; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_526 = {1'h0, loginfo_cycles_263} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_527 = _loginfo_cycles_T_526[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_264; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_528 = {1'h0, loginfo_cycles_264} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_529 = _loginfo_cycles_T_528[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_265; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_530 = {1'h0, loginfo_cycles_265} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_531 = _loginfo_cycles_T_530[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_266; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_532 = {1'h0, loginfo_cycles_266} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_533 = _loginfo_cycles_T_532[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_267; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_534 = {1'h0, loginfo_cycles_267} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_535 = _loginfo_cycles_T_534[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_268; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_536 = {1'h0, loginfo_cycles_268} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_537 = _loginfo_cycles_T_536[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_269; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_538 = {1'h0, loginfo_cycles_269} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_539 = _loginfo_cycles_T_538[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_270; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_540 = {1'h0, loginfo_cycles_270} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_541 = _loginfo_cycles_T_540[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_271; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_542 = {1'h0, loginfo_cycles_271} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_543 = _loginfo_cycles_T_542[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_272; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_544 = {1'h0, loginfo_cycles_272} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_545 = _loginfo_cycles_T_544[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_273; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_546 = {1'h0, loginfo_cycles_273} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_547 = _loginfo_cycles_T_546[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_274; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_548 = {1'h0, loginfo_cycles_274} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_549 = _loginfo_cycles_T_548[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_275; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_550 = {1'h0, loginfo_cycles_275} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_551 = _loginfo_cycles_T_550[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_276; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_552 = {1'h0, loginfo_cycles_276} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_553 = _loginfo_cycles_T_552[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_277; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_554 = {1'h0, loginfo_cycles_277} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_555 = _loginfo_cycles_T_554[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_278; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_556 = {1'h0, loginfo_cycles_278} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_557 = _loginfo_cycles_T_556[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_279; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_558 = {1'h0, loginfo_cycles_279} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_559 = _loginfo_cycles_T_558[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_280; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_560 = {1'h0, loginfo_cycles_280} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_561 = _loginfo_cycles_T_560[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_281; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_562 = {1'h0, loginfo_cycles_281} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_563 = _loginfo_cycles_T_562[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_282; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_564 = {1'h0, loginfo_cycles_282} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_565 = _loginfo_cycles_T_564[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_283; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_566 = {1'h0, loginfo_cycles_283} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_567 = _loginfo_cycles_T_566[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_284; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_568 = {1'h0, loginfo_cycles_284} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_569 = _loginfo_cycles_T_568[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_285; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_570 = {1'h0, loginfo_cycles_285} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_571 = _loginfo_cycles_T_570[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_286; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_572 = {1'h0, loginfo_cycles_286} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_573 = _loginfo_cycles_T_572[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_287; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_574 = {1'h0, loginfo_cycles_287} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_575 = _loginfo_cycles_T_574[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_288; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_576 = {1'h0, loginfo_cycles_288} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_577 = _loginfo_cycles_T_576[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_289; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_578 = {1'h0, loginfo_cycles_289} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_579 = _loginfo_cycles_T_578[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_290; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_580 = {1'h0, loginfo_cycles_290} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_581 = _loginfo_cycles_T_580[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_291; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_582 = {1'h0, loginfo_cycles_291} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_583 = _loginfo_cycles_T_582[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_292; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_584 = {1'h0, loginfo_cycles_292} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_585 = _loginfo_cycles_T_584[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_293; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_586 = {1'h0, loginfo_cycles_293} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_587 = _loginfo_cycles_T_586[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_294; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_588 = {1'h0, loginfo_cycles_294} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_589 = _loginfo_cycles_T_588[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_295; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_590 = {1'h0, loginfo_cycles_295} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_591 = _loginfo_cycles_T_590[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_296; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_592 = {1'h0, loginfo_cycles_296} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_593 = _loginfo_cycles_T_592[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_297; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_594 = {1'h0, loginfo_cycles_297} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_595 = _loginfo_cycles_T_594[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_298; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_596 = {1'h0, loginfo_cycles_298} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_597 = _loginfo_cycles_T_596[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_299; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_598 = {1'h0, loginfo_cycles_299} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_599 = _loginfo_cycles_T_598[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_300; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_600 = {1'h0, loginfo_cycles_300} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_601 = _loginfo_cycles_T_600[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_301; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_602 = {1'h0, loginfo_cycles_301} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_603 = _loginfo_cycles_T_602[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_302; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_604 = {1'h0, loginfo_cycles_302} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_605 = _loginfo_cycles_T_604[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_303; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_606 = {1'h0, loginfo_cycles_303} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_607 = _loginfo_cycles_T_606[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_304; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_608 = {1'h0, loginfo_cycles_304} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_609 = _loginfo_cycles_T_608[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_305; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_610 = {1'h0, loginfo_cycles_305} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_611 = _loginfo_cycles_T_610[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_306; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_612 = {1'h0, loginfo_cycles_306} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_613 = _loginfo_cycles_T_612[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_307; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_614 = {1'h0, loginfo_cycles_307} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_615 = _loginfo_cycles_T_614[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_308; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_616 = {1'h0, loginfo_cycles_308} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_617 = _loginfo_cycles_T_616[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_309; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_618 = {1'h0, loginfo_cycles_309} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_619 = _loginfo_cycles_T_618[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_310; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_620 = {1'h0, loginfo_cycles_310} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_621 = _loginfo_cycles_T_620[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_311; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_622 = {1'h0, loginfo_cycles_311} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_623 = _loginfo_cycles_T_622[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_312; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_624 = {1'h0, loginfo_cycles_312} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_625 = _loginfo_cycles_T_624[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_313; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_626 = {1'h0, loginfo_cycles_313} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_627 = _loginfo_cycles_T_626[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_314; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_628 = {1'h0, loginfo_cycles_314} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_629 = _loginfo_cycles_T_628[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_315; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_630 = {1'h0, loginfo_cycles_315} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_631 = _loginfo_cycles_T_630[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_316; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_632 = {1'h0, loginfo_cycles_316} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_633 = _loginfo_cycles_T_632[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_317; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_634 = {1'h0, loginfo_cycles_317} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_635 = _loginfo_cycles_T_634[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_318; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_636 = {1'h0, loginfo_cycles_318} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_637 = _loginfo_cycles_T_636[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_319; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_638 = {1'h0, loginfo_cycles_319} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_639 = _loginfo_cycles_T_638[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_320; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_640 = {1'h0, loginfo_cycles_320} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_641 = _loginfo_cycles_T_640[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_321; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_642 = {1'h0, loginfo_cycles_321} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_643 = _loginfo_cycles_T_642[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_322; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_644 = {1'h0, loginfo_cycles_322} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_645 = _loginfo_cycles_T_644[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_323; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_646 = {1'h0, loginfo_cycles_323} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_647 = _loginfo_cycles_T_646[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_324; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_648 = {1'h0, loginfo_cycles_324} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_649 = _loginfo_cycles_T_648[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_325; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_650 = {1'h0, loginfo_cycles_325} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_651 = _loginfo_cycles_T_650[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_326; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_652 = {1'h0, loginfo_cycles_326} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_653 = _loginfo_cycles_T_652[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_327; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_654 = {1'h0, loginfo_cycles_327} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_655 = _loginfo_cycles_T_654[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_328; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_656 = {1'h0, loginfo_cycles_328} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_657 = _loginfo_cycles_T_656[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_329; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_658 = {1'h0, loginfo_cycles_329} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_659 = _loginfo_cycles_T_658[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_330; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_660 = {1'h0, loginfo_cycles_330} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_661 = _loginfo_cycles_T_660[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_331; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_662 = {1'h0, loginfo_cycles_331} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_663 = _loginfo_cycles_T_662[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_332; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_664 = {1'h0, loginfo_cycles_332} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_665 = _loginfo_cycles_T_664[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_333; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_666 = {1'h0, loginfo_cycles_333} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_667 = _loginfo_cycles_T_666[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_334; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_668 = {1'h0, loginfo_cycles_334} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_669 = _loginfo_cycles_T_668[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_335; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_670 = {1'h0, loginfo_cycles_335} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_671 = _loginfo_cycles_T_670[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_336; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_672 = {1'h0, loginfo_cycles_336} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_673 = _loginfo_cycles_T_672[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_337; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_674 = {1'h0, loginfo_cycles_337} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_675 = _loginfo_cycles_T_674[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_338; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_676 = {1'h0, loginfo_cycles_338} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_677 = _loginfo_cycles_T_676[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_339; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_678 = {1'h0, loginfo_cycles_339} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_679 = _loginfo_cycles_T_678[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_340; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_680 = {1'h0, loginfo_cycles_340} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_681 = _loginfo_cycles_T_680[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_341; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_682 = {1'h0, loginfo_cycles_341} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_683 = _loginfo_cycles_T_682[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_342; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_684 = {1'h0, loginfo_cycles_342} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_685 = _loginfo_cycles_T_684[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_343; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_686 = {1'h0, loginfo_cycles_343} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_687 = _loginfo_cycles_T_686[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_344; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_688 = {1'h0, loginfo_cycles_344} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_689 = _loginfo_cycles_T_688[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_345; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_690 = {1'h0, loginfo_cycles_345} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_691 = _loginfo_cycles_T_690[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_346; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_692 = {1'h0, loginfo_cycles_346} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_693 = _loginfo_cycles_T_692[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_347; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_694 = {1'h0, loginfo_cycles_347} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_695 = _loginfo_cycles_T_694[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_348; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_696 = {1'h0, loginfo_cycles_348} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_697 = _loginfo_cycles_T_696[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_349; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_698 = {1'h0, loginfo_cycles_349} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_699 = _loginfo_cycles_T_698[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_350; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_700 = {1'h0, loginfo_cycles_350} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_701 = _loginfo_cycles_T_700[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_351; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_702 = {1'h0, loginfo_cycles_351} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_703 = _loginfo_cycles_T_702[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_352; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_704 = {1'h0, loginfo_cycles_352} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_705 = _loginfo_cycles_T_704[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_353; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_706 = {1'h0, loginfo_cycles_353} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_707 = _loginfo_cycles_T_706[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_354; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_708 = {1'h0, loginfo_cycles_354} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_709 = _loginfo_cycles_T_708[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_355; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_710 = {1'h0, loginfo_cycles_355} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_711 = _loginfo_cycles_T_710[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_356; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_712 = {1'h0, loginfo_cycles_356} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_713 = _loginfo_cycles_T_712[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_357; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_714 = {1'h0, loginfo_cycles_357} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_715 = _loginfo_cycles_T_714[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_358; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_716 = {1'h0, loginfo_cycles_358} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_717 = _loginfo_cycles_T_716[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_359; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_718 = {1'h0, loginfo_cycles_359} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_719 = _loginfo_cycles_T_718[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_360; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_720 = {1'h0, loginfo_cycles_360} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_721 = _loginfo_cycles_T_720[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_361; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_722 = {1'h0, loginfo_cycles_361} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_723 = _loginfo_cycles_T_722[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_362; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_724 = {1'h0, loginfo_cycles_362} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_725 = _loginfo_cycles_T_724[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_363; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_726 = {1'h0, loginfo_cycles_363} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_727 = _loginfo_cycles_T_726[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_364; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_728 = {1'h0, loginfo_cycles_364} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_729 = _loginfo_cycles_T_728[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_365; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_730 = {1'h0, loginfo_cycles_365} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_731 = _loginfo_cycles_T_730[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_366; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_732 = {1'h0, loginfo_cycles_366} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_733 = _loginfo_cycles_T_732[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_367; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_734 = {1'h0, loginfo_cycles_367} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_735 = _loginfo_cycles_T_734[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_368; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_736 = {1'h0, loginfo_cycles_368} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_737 = _loginfo_cycles_T_736[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_369; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_738 = {1'h0, loginfo_cycles_369} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_739 = _loginfo_cycles_T_738[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_370; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_740 = {1'h0, loginfo_cycles_370} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_741 = _loginfo_cycles_T_740[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_371; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_742 = {1'h0, loginfo_cycles_371} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_743 = _loginfo_cycles_T_742[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_372; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_744 = {1'h0, loginfo_cycles_372} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_745 = _loginfo_cycles_T_744[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_373; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_746 = {1'h0, loginfo_cycles_373} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_747 = _loginfo_cycles_T_746[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_374; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_748 = {1'h0, loginfo_cycles_374} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_749 = _loginfo_cycles_T_748[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_375; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_750 = {1'h0, loginfo_cycles_375} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_751 = _loginfo_cycles_T_750[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_376; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_752 = {1'h0, loginfo_cycles_376} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_753 = _loginfo_cycles_T_752[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_377; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_754 = {1'h0, loginfo_cycles_377} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_755 = _loginfo_cycles_T_754[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_378; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_756 = {1'h0, loginfo_cycles_378} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_757 = _loginfo_cycles_T_756[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_379; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_758 = {1'h0, loginfo_cycles_379} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_759 = _loginfo_cycles_T_758[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_380; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_760 = {1'h0, loginfo_cycles_380} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_761 = _loginfo_cycles_T_760[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_381; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_762 = {1'h0, loginfo_cycles_381} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_763 = _loginfo_cycles_T_762[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_382; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_764 = {1'h0, loginfo_cycles_382} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_765 = _loginfo_cycles_T_764[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_383; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_766 = {1'h0, loginfo_cycles_383} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_767 = _loginfo_cycles_T_766[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_384; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_768 = {1'h0, loginfo_cycles_384} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_769 = _loginfo_cycles_T_768[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_385; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_770 = {1'h0, loginfo_cycles_385} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_771 = _loginfo_cycles_T_770[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_386; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_772 = {1'h0, loginfo_cycles_386} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_773 = _loginfo_cycles_T_772[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_387; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_774 = {1'h0, loginfo_cycles_387} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_775 = _loginfo_cycles_T_774[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_388; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_776 = {1'h0, loginfo_cycles_388} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_777 = _loginfo_cycles_T_776[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_389; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_778 = {1'h0, loginfo_cycles_389} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_779 = _loginfo_cycles_T_778[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_390; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_780 = {1'h0, loginfo_cycles_390} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_781 = _loginfo_cycles_T_780[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_391; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_782 = {1'h0, loginfo_cycles_391} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_783 = _loginfo_cycles_T_782[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_392; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_784 = {1'h0, loginfo_cycles_392} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_785 = _loginfo_cycles_T_784[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_393; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_786 = {1'h0, loginfo_cycles_393} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_787 = _loginfo_cycles_T_786[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_394; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_788 = {1'h0, loginfo_cycles_394} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_789 = _loginfo_cycles_T_788[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_395; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_790 = {1'h0, loginfo_cycles_395} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_791 = _loginfo_cycles_T_790[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_396; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_792 = {1'h0, loginfo_cycles_396} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_793 = _loginfo_cycles_T_792[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_397; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_794 = {1'h0, loginfo_cycles_397} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_795 = _loginfo_cycles_T_794[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_398; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_796 = {1'h0, loginfo_cycles_398} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_797 = _loginfo_cycles_T_796[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_399; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_798 = {1'h0, loginfo_cycles_399} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_799 = _loginfo_cycles_T_798[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating || enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode :*= clockNamePrefixer :*= aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File ResetSynchronizer.scala: // See LICENSE for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.ResetCatchAndSync /** * Synchronizes the reset of a diplomatic clock-reset pair to its accompanying clock. */ class ResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, _), (i, _)) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } object ResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ResetSynchronizer()).node } /** * Instantiates a reset synchronizer on all clock-reset pairs in a clock group. */ class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockGroupAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((oG, _), (iG, _)) => (oG.member.data zip iG.member.data).foreach { case (o, i) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } } object ClockGroupResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module ChipyardPRCICtrlClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _fragmenter_1_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34] wire [9:0] _fragmenter_1_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_1_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [13:0] _fragmenter_1_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_1_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_1_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_tl_in_a_ready; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_tl_in_d_valid; // @[HasChipyardPRCI.scala:78:34] wire [2:0] _reset_setter_auto_tl_in_d_bits_opcode; // @[HasChipyardPRCI.scala:78:34] wire [1:0] _reset_setter_auto_tl_in_d_bits_size; // @[HasChipyardPRCI.scala:78:34] wire [13:0] _reset_setter_auto_tl_in_d_bits_source; // @[HasChipyardPRCI.scala:78:34] wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34] wire [9:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [13:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _clock_gater_auto_clock_gater_in_1_a_ready; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_in_1_d_valid; // @[HasChipyardPRCI.scala:73:33] wire [2:0] _clock_gater_auto_clock_gater_in_1_d_bits_opcode; // @[HasChipyardPRCI.scala:73:33] wire [1:0] _clock_gater_auto_clock_gater_in_1_d_bits_size; // @[HasChipyardPRCI.scala:73:33] wire [13:0] _clock_gater_auto_clock_gater_in_1_d_bits_source; // @[HasChipyardPRCI.scala:73:33] wire [63:0] _clock_gater_auto_clock_gater_in_1_d_bits_data; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:73:33] wire _xbar_auto_anon_out_1_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_size; // @[Xbar.scala:346:26] wire [9:0] _xbar_auto_anon_out_1_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_1_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_1_a_bits_mask; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_d_ready; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_size; // @[Xbar.scala:346:26] wire [9:0] _xbar_auto_anon_out_0_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_0_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_0_a_bits_mask; // @[Xbar.scala:346:26] wire [63:0] _xbar_auto_anon_out_0_a_bits_data; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_d_ready; // @[Xbar.scala:346:26] TLXbar_prcibus_i1_o2_a21d64s10k1z3u xbar ( // @[Xbar.scala:346:26] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_anon_in_a_ready (auto_xbar_anon_in_a_ready), .auto_anon_in_a_valid (auto_xbar_anon_in_a_valid), .auto_anon_in_a_bits_opcode (auto_xbar_anon_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_xbar_anon_in_a_bits_param), .auto_anon_in_a_bits_size (auto_xbar_anon_in_a_bits_size), .auto_anon_in_a_bits_source (auto_xbar_anon_in_a_bits_source), .auto_anon_in_a_bits_address (auto_xbar_anon_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_xbar_anon_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_xbar_anon_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_xbar_anon_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_xbar_anon_in_d_ready), .auto_anon_in_d_valid (auto_xbar_anon_in_d_valid), .auto_anon_in_d_bits_opcode (auto_xbar_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_xbar_anon_in_d_bits_size), .auto_anon_in_d_bits_source (auto_xbar_anon_in_d_bits_source), .auto_anon_in_d_bits_data (auto_xbar_anon_in_d_bits_data), .auto_anon_out_1_a_ready (_fragmenter_1_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34] .auto_anon_out_1_a_valid (_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_fragmenter_1_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34] .auto_anon_out_1_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34] .auto_anon_out_1_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34] .auto_anon_out_1_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34] .auto_anon_out_0_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34] .auto_anon_out_0_a_valid (_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34] ); // @[Xbar.scala:346:26] ClockGroupResetSynchronizer resetSynchronizer ( // @[ResetSynchronizer.scala:46:69] .auto_in_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:73:33] .auto_in_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:73:33] .auto_out_member_allClocks_uncore_clock (auto_resetSynchronizer_out_member_allClocks_uncore_clock), .auto_out_member_allClocks_uncore_reset (auto_resetSynchronizer_out_member_allClocks_uncore_reset) ); // @[ResetSynchronizer.scala:46:69] TileClockGater clock_gater ( // @[HasChipyardPRCI.scala:73:33] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_clock_gater_in_1_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), .auto_clock_gater_in_1_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), .auto_clock_gater_in_1_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), .auto_clock_gater_in_1_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), .auto_clock_gater_in_1_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), .auto_clock_gater_in_1_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data), .auto_clock_gater_in_0_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_in_0_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_out_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), .auto_clock_gater_out_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset) ); // @[HasChipyardPRCI.scala:73:33] TLFragmenter_TileClockGater fragmenter ( // @[Fragmenter.scala:345:34] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready), .auto_anon_in_a_valid (_xbar_auto_anon_out_0_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_0_d_ready), // @[Xbar.scala:346:26] .auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), .auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data), .auto_anon_out_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready), .auto_anon_out_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data) // @[HasChipyardPRCI.scala:73:33] ); // @[Fragmenter.scala:345:34] TileResetSetter reset_setter ( // @[HasChipyardPRCI.scala:78:34] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_clock_in_member_allClocks_uncore_clock (auto_reset_setter_clock_in_member_allClocks_uncore_clock), .auto_clock_in_member_allClocks_uncore_reset (auto_reset_setter_clock_in_member_allClocks_uncore_reset), .auto_clock_out_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), .auto_clock_out_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), .auto_tl_in_a_ready (_reset_setter_auto_tl_in_a_ready), .auto_tl_in_a_valid (_fragmenter_1_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_tl_in_d_ready (_fragmenter_1_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_tl_in_d_valid (_reset_setter_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_reset_setter_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_reset_setter_auto_tl_in_d_bits_source) ); // @[HasChipyardPRCI.scala:78:34] TLFragmenter_TileResetSetter fragmenter_1 ( // @[Fragmenter.scala:345:34] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_anon_in_a_ready (_fragmenter_1_auto_anon_in_a_ready), .auto_anon_in_a_valid (_xbar_auto_anon_out_1_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_1_d_ready), // @[Xbar.scala:346:26] .auto_anon_in_d_valid (_fragmenter_1_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source), .auto_anon_out_a_ready (_reset_setter_auto_tl_in_a_ready), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_a_valid (_fragmenter_1_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_1_auto_anon_out_d_ready), .auto_anon_out_d_valid (_reset_setter_auto_tl_in_d_valid), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_d_bits_size (_reset_setter_auto_tl_in_d_bits_size), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_d_bits_source (_reset_setter_auto_tl_in_d_bits_source) // @[HasChipyardPRCI.scala:78:34] ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready || !io.in.bits.head || at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready || !io.in.bits.head || at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) && (vcalloc_q.io.enq.ready || !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }
module IngressUnit_34( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_10, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_11, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_12, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_13, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_14, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_15, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_16, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_17, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_18, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_19, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_20, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_10, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_11, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_14, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_15, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_18, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_19, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_20, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_21, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_10; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_11; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_12; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_13; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_14; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_15; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_16; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_17; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_18; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_19; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_20; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_21; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 6'h26; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h2C; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h2F; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 6'h23; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 6'h29; // @[IngressUnit.scala:30:72] wire [2:0] _GEN_0 = (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 3'h6 : 3'h0) | {_route_buffer_io_enq_bits_flow_egress_node_id_T_3, 2'h0}; // @[Mux.scala:30:73] wire [1:0] _GEN_1 = _GEN_0[1:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_4, 1'h0}; // @[Mux.scala:30:73] wire [3:0] _GEN_2 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_1, _GEN_0[2], _GEN_1}; // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_2 == 4'hA; // @[Decoupled.scala:51:35] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_2 != 4'hA; // @[Decoupled.scala:51:35] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_155( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_275 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_62 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File decode.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import freechips.rocketchip.tile.FPConstants import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket.Instructions32 import freechips.rocketchip.rocket.CustomInstructions._ import freechips.rocketchip.rocket.RVCExpander import freechips.rocketchip.rocket.ALU._ import freechips.rocketchip.rocket.{CSR, Causes, DecodeLogic} import freechips.rocketchip.util._ import boom.v4.common._ import boom.v4.util._ // scalastyle:off /** * Abstract trait giving defaults and other relevant values to different Decode constants/ */ object DecodeTables extends freechips.rocketchip.rocket.constants.ScalarOpConstants with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.tile.HasFPUParameters { lazy val fLen = 64 lazy val minFLen = 32 def xLen = 64 def xpr64 = Y // TODO inform this from xLen def DC(i: Int) = BitPat.dontCare(i) def fc2oh(fc: Int): UInt = (1 << fc).U(FC_SZ.W) // FP stores generate data through FP F2I, and generate address through MemAddrCalc def FCOH_F2IMEM = ((1 << FC_AGEN) | (1 << FC_F2I )).U(FC_SZ.W) def FCOH_STORE = ((1 << FC_AGEN) | (1 << FC_DGEN)).U(FC_SZ.W) def FN_00 = BitPat("b???00") def FN_01 = BitPat("b???01") def FN_10 = BitPat("b???10") def FN_11 = BitPat("b???11") def decode_default: List[BitPat] = // frs3_en // is val inst? | imm sel // | is fp inst? | | uses_ldq // | | rs1 regtype | | | uses_stq is unique? (clear pipeline for it) // | | | rs2 type| | | | is_amo | flush on commit // | | func unit | | | | | | | | | csr cmd // | | | | | | | | | | | | | fcn_dw swap12 fma // | | | dst | | | | | | | mem | | | | fcn_op | swap32 | div // | | | regtype | | | | | | | cmd | | | | | | | typeTagIn | | sqrt // | | | | | | | | | | | | | | | | | ldst | | | typeTagOut | | wflags // | | | | | | | | | | | | | | | | | | wen | | | | from_int | | | // | | | | | | | | | | | | | | | | | | | ren1 | | | | | to_int | | | // | | | | | | | | | | | | | | | | | | | | ren2 | | | | | | fast | | | // | | | | | | | | | | | | | | | | | | | | | ren3 | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List(N, N, DC(FC_SZ) , RT_X , DC(2) , DC(2) , X, IS_N, X, X, X, M_X, N, X, CSR.X, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) def X32_table: Seq[(BitPat, List[BitPat])] = { import Instructions32._; Seq( SLLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) } def X64_table: Seq[(BitPat, List[BitPat])] = Seq( LD -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LWU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SD -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SUBW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRAW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) def X_table: Seq[(BitPat, List[BitPat])] = Seq( LW -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LH -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LHU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LB -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LBU -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SW -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SB -> List(Y, N, FCOH_STORE , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LUI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADDI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ANDI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_AND , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTIU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SUB -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLT -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLTU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AND -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_AND , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), OR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XOR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRA -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SRA , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MUL -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MUL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULH -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULH, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULHU -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULHU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULHSU -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MULHSU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MULW -> List(Y, N, fc2oh(FC_MUL) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_MUL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIV -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_DIV , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVU -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_DIVU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REM -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_REM , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMU -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_REMU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_DIV , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DIVUW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_DIVU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_REM , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REMUW -> List(Y, N, fc2oh(FC_DIV) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_32 , FN_REMU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AUIPC -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // use BRU for the PC read JAL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), JALR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEQ -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BNE -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SUB , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BGE -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BGEU -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BLT -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLT , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BLTU -> List(Y, N, fc2oh(FC_ALU) , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_SLTU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // I-type, the immedia2 holds the CSR regi ster. CSRRW -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.W, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRS -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.S, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRC -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.C, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRWI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.W, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRSI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.S, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CSRRCI -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.C, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SFENCE_VMA ->List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N,M_SFENCE , Y, Y, CSR.R, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ECALL -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), EBREAK -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), DRET -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), WFI -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_I, N, N, N, M_X , Y, Y, CSR.I, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FENCE_I -> List(Y, N, 0.U(FC_SZ.W) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , Y, Y, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FENCE -> List(Y, N, 0.U(FC_SZ.W) , RT_X , RT_X , RT_X , N, IS_N, N, Y, N, M_X , Y, Y, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // TODO PERF make fence higher performance // currently serializes pipeline // A-type AMOADD_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_ADD, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // TODO make AMOs higherperformance AMOXOR_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_XOR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOSWAP_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_SWAP,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOAND_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_AND, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOOR_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_OR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMIN_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MIN, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMINU_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MINU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAX_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAX, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAXU_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAXU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOADD_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_ADD, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOXOR_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_XOR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOSWAP_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_SWAP,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOAND_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_AND, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOOR_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_OR, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMIN_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MIN, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMINU_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MINU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAX_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAX, Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), AMOMAXU_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XA_MAXU,Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LR_W -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_N, Y, N, N, M_XLR , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), LR_D -> List(Y, N, fc2oh(FC_AGEN), RT_FIX, RT_FIX, RT_X , N, IS_N, Y, N, N, M_XLR , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SC_W -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XSC , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SC_D -> List(Y, N, FCOH_STORE , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, Y, Y, M_XSC , Y, Y, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) def F_table: Seq[(BitPat, List[BitPat])] = Seq( FLW -> List(Y, Y, fc2oh(FC_AGEN), RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FLD -> List(Y, Y, fc2oh(FC_AGEN), RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, M_XRD , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FSW -> List(Y, Y, FCOH_F2IMEM , RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), // sort of a lie; broken into two micro-ops FSD -> List(Y, Y, FCOH_F2IMEM , RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, M_XWR , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), FCLASS_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N), FCLASS_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), FMV_W_X -> List(Y, Y, fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N), FMV_D_X -> List(Y, Y, fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N), FMV_X_W -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N), FMV_X_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), FSGNJ_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJ_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), FSGNJX_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJX_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), FSGNJN_S -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), FSGNJN_D -> List(Y, Y, fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), // FP to FP FCVT_S_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y), FCVT_D_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y), // Int to FP FCVT_S_W -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_WU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_L -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_S_LU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), FCVT_D_W -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_WU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_L -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), FCVT_D_LU -> List(Y, Y,fc2oh(FC_I2F) , RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), // FP to Int FCVT_W_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_WU_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_L_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_LU_S -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), FCVT_W_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_WU_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_L_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FCVT_LU_D -> List(Y, Y,fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), FEQ_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FLT_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FLE_S -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), FEQ_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FLT_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FLE_D -> List(Y, Y, fc2oh(FC_F2I) , RT_FIX, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), FMIN_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), FMAX_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), FMIN_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), FMAX_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), FADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), FSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), FMUL_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y), FADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), FSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), FMUL_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y), FMADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FMSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FNMADD_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_11 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FNMSUB_S -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_10 ,X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), FMADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_00 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FMSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_01 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FNMADD_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_11 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), FNMSUB_D -> List(Y, Y,fc2oh(FC_FPU) , RT_FLT, RT_FLT, RT_FLT, Y, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_10 ,X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y) ) def FDivSqrt_table: Seq[(BitPat, List[BitPat])] = Seq( FDIV_S -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,X, X,X,S,S,X,X,X, X,Y,N,Y), FDIV_D -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_FLT, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,Y,X, X,X,D,D,X,X,X, X,Y,N,Y), FSQRT_S -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,X, X,X,S,S,X,X,X, X,N,Y,Y), FSQRT_D -> List(Y, Y, fc2oh(FC_FDV) , RT_FLT, RT_FLT, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X ,X,X,Y,N,X, X,X,D,D,X,X,X, X,N,Y,Y), ) def B_table: Seq[(BitPat, List[BitPat])] = Seq( SH1ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH2ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH3ADD -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH1ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH2ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SH3ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ADD_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_F3,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ADD , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SLLI_UW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_SL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ANDN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ORN , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), XNOR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XNOR, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MAX -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MAX , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MAXU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MAXU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MIN -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MIN , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), MINU -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_MINU, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROL -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CLZ -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CTZ -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CPOP -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ORC_B -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SEXT_B -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), SEXT_H -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ZEXT_H -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), REV8 -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ROLW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROL , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), RORIW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 , FN_ROR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CLZW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CTZW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CPOPW -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_32 ,FN_UNARY, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BCLR -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BCLRI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_ANDN, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BINV -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BINVI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_XOR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BSET -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BSETI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_OR , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEXT -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_FIX, N, IS_N ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_BEXT, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), BEXTI -> List(Y, N, fc2oh(FC_ALU) , RT_FIX, RT_FIX, RT_X , N, IS_I ,N, N, N, M_X , N, N, CSR.N, DW_XPR, FN_BEXT, X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), ) def RoCC_table: Seq[(BitPat, List[BitPat])] = Seq( // Note: We use fc2oh(FC_CSR) since CSR instructions cannot co-execute with RoCC instructions CUSTOM0 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM0_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM1_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM2_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_X , RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_X , RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD_RS1 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_X , N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X), CUSTOM3_RD_RS1_RS2 -> List(Y, N, fc2oh(FC_CSR) , RT_FIX, RT_FIX, RT_FIX, N, IS_N, N, N, N, M_X , N, N, CSR.N, DW_X , FN_X , X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) ) } // scalastyle:on /** * Decoded control signals */ class CtrlSigs(implicit p: Parameters) extends Bundle { val legal = Bool() val fp_val = Bool() val fu_code = UInt(FC_SZ.W) val dst_type = UInt(2.W) val rs1_type = UInt(2.W) val rs2_type = UInt(2.W) val frs3_en = Bool() val imm_sel = UInt(IS_N.getWidth.W) val uses_ldq = Bool() val uses_stq = Bool() val is_amo = Bool() val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W) val inst_unique = Bool() val flush_on_commit = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val fcn_dw = Bool() val fcn_op = UInt(SZ_ALU_FN.W) val fp = new freechips.rocketchip.tile.FPUCtrlSigs() def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, DecodeTables.decode_default, table) val sigs = Seq( legal, fp_val, fu_code, dst_type, rs1_type, rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo, mem_cmd, inst_unique, flush_on_commit, csr_cmd, fcn_dw, fcn_op, fp.ldst, fp.wen, fp.ren1, fp.ren2, fp.ren3, fp.swap12, fp.swap23, fp.typeTagIn, fp.typeTagOut, fp.fromint, fp.toint, fp.fastpipe, fp.fma, fp.div, fp.sqrt, fp.wflags ) sigs zip decoder map {case(s,d) => s := d} fp.vec := false.B this } } /** * IO bundle for the Decode unit */ class DecodeUnitIo(implicit p: Parameters) extends BoomBundle { val enq = new Bundle { val uop = Input(new MicroOp()) } val deq = new Bundle { val uop = Output(new MicroOp()) } // from CSRFile val status = Input(new freechips.rocketchip.rocket.MStatus()) val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO) val fcsr_rm = Input(UInt(FPConstants.RM_SZ.W)) val interrupt = Input(Bool()) val interrupt_cause = Input(UInt(xLen.W)) } /** * Decode unit that takes in a single instruction and generates a MicroOp. */ class DecodeUnit(implicit p: Parameters) extends BoomModule with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val io = IO(new DecodeUnitIo) val uop = Wire(new MicroOp()) uop := io.enq.uop val decode_table = ( DecodeTables.X_table ++ DecodeTables.F_table ++ DecodeTables.FDivSqrt_table ++ DecodeTables.X64_table ++ DecodeTables.B_table ++ (if (usingRoCC) DecodeTables.RoCC_table else Nil) ) val inst = uop.inst val LDST = inst(RD_MSB,RD_LSB) val LRS1 = inst(RS1_MSB,RS1_LSB) val LRS2 = inst(RS2_MSB,RS2_LSB) val LRS3 = inst(RS3_MSB,RS3_LSB) val cs = Wire(new CtrlSigs()).decode(inst, decode_table) // Exception Handling io.csr_decode.inst := inst val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W) val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U val system_insn = cs.csr_cmd === CSR.I val sfence = inst === SFENCE_VMA val cs_legal = cs.legal // dontTouch(cs_legal) require (fLen >= 64) val illegal_rm = inst(14,12).isOneOf(5.U,6.U) || (inst(14,12) === 7.U && io.fcsr_rm >= 5.U) val id_illegal_insn = (!cs_legal || (cs.fp_val && (io.csr_decode.fp_illegal || illegal_rm)) || (uop.is_rocc && io.csr_decode.rocc_illegal) || (cs.is_amo && !io.status.isa('a'-'a')) || (csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal)) || ((sfence || system_insn) && io.csr_decode.system_illegal)) // cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) val (xcpt_valid, xcpt_cause) = checkExceptions(List( (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB (uop.bp_debug_if, (CSR.debugTriggerCause).U), (uop.bp_xcpt_if, (Causes.breakpoint).U), (uop.xcpt_pf_if, (Causes.fetch_page_fault).U), (uop.xcpt_ae_if, (Causes.fetch_access).U), (id_illegal_insn, (Causes.illegal_instruction).U))) uop.exception := xcpt_valid uop.exc_cause := xcpt_cause //------------------------------------------------------------- uop.is_mov := inst === ADD && LRS1 === 0.U uop.iq_type(IQ_UNQ) := Seq(FC_MUL , FC_DIV, FC_CSR, FC_I2F).map { c => cs.fu_code(c) }.reduce(_||_) uop.iq_type(IQ_ALU) := Seq(FC_ALU ).map { c => cs.fu_code(c) }.reduce(_||_) uop.iq_type(IQ_MEM) := Seq(FC_AGEN, FC_DGEN ).map { c => cs.fu_code(c) }.reduce(_||_) uop.iq_type(IQ_FP ) := Seq(FC_FPU , FC_FDV, FC_F2I ).map { c => cs.fu_code(c) }.reduce(_||_) uop.fu_code := cs.fu_code.asBools uop.ldst := LDST uop.lrs1 := LRS1 uop.lrs2 := LRS2 uop.lrs3 := LRS3 uop.dst_rtype := cs.dst_type uop.lrs1_rtype := Mux(cs.rs1_type === RT_FIX && LRS1 === 0.U, RT_ZERO, cs.rs1_type) uop.lrs2_rtype := Mux(cs.rs2_type === RT_FIX && LRS2 === 0.U, RT_ZERO, cs.rs2_type) uop.frs3_en := cs.frs3_en uop.ldst_is_rs1 := uop.is_sfb_shadow // SFB optimization when (uop.is_sfb_shadow && cs.rs2_type === RT_X) { uop.lrs2_rtype := Mux(LDST === 0.U, RT_ZERO, RT_FIX) uop.lrs2 := LDST uop.ldst_is_rs1 := false.B } .elsewhen (uop.is_sfb_shadow && uop.is_mov) { uop.lrs1 := LDST uop.lrs1_rtype := Mux(LDST === 0.U, RT_ZERO, RT_FIX) uop.ldst_is_rs1 := true.B } uop.fp_val := cs.fp_val uop.fp_ctrl := cs.fp uop.mem_cmd := cs.mem_cmd uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(LRS2 =/= 0.U, LRS1 =/= 0.U), inst(13,12)) uop.mem_signed := !inst(14) uop.uses_ldq := cs.uses_ldq uop.uses_stq := cs.uses_stq uop.is_amo := cs.is_amo uop.is_fence := inst === FENCE uop.is_fencei := inst === FENCE_I uop.is_sfence := inst === SFENCE_VMA uop.is_sys_pc2epc := inst === EBREAK || inst === ECALL uop.is_eret := inst === ECALL || inst === EBREAK || inst === SRET || inst === MRET || inst === DRET uop.is_unique := cs.inst_unique uop.is_rocc := inst(6,0).isOneOf("b0001011".U, "b0101011".U, "b1111011".U) && inst(14,12).isOneOf(0.U, 2.U, 3.U, 4.U, 6.U, 7.U) uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush) //------------------------------------------------------------- // immediates // repackage the immediate, and then pass the fewest number of bits around val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20)) val imm_packed = Cat(inst(31,25), di24_20, inst(19,12)) val imm = ImmGen(imm_packed, cs.imm_sel) val imm_hi = imm >> (immPregSz-1) val imm_lo = imm(immPregSz-1, 0) val short_imm = imm_hi === 0.U || ~imm_hi === 0.U || cs.imm_sel === IS_F3 uop.imm_rename := cs.imm_sel =/= IS_N && cs.imm_sel =/= IS_F3 uop.imm_packed := imm_packed uop.imm_sel := cs.imm_sel when (short_imm) { uop.imm_rename := false.B uop.imm_sel := IS_SH uop.pimm := Mux(cs.imm_sel === IS_F3, inst(14,12), imm_lo) } uop.fp_rm := Mux(inst(14,12) === 7.U, io.fcsr_rm, inst(14,12)) uop.fp_typ := inst(21,20) //------------------------------------------------------------- uop.csr_cmd := cs.csr_cmd when ((cs.csr_cmd === CSR.S || cs.csr_cmd === CSR.C) && LRS1 === 0.U) { uop.csr_cmd := CSR.R } uop.fcn_dw := cs.fcn_dw uop.fcn_op := cs.fcn_op uop.op1_sel := OP1_RS1 when (inst === LUI || inst === CSRRWI || inst === CSRRSI || inst === CSRRCI || inst === WFI || inst === SRET || inst === MRET || inst === DRET) { uop.op1_sel := OP1_ZERO } .elsewhen (inst === JAL || inst === JALR || inst === AUIPC) { uop.op1_sel := OP1_PC } .elsewhen (Seq(SH1ADD, SH2ADD, SH3ADD, SH1ADD_UW, SH2ADD_UW, SH3ADD_UW, ADD_UW, SLLI_UW).map(_ === inst).orR) { uop.op1_sel := OP1_RS1SHL } uop.op2_sel := OP2_RS2 when (cs.is_amo || inst === CSRRW || inst === CSRRS || inst === CSRRC) { uop.op2_sel := OP2_ZERO } .elsewhen (inst === CSRRWI || inst === CSRRSI || inst === CSRRCI || inst === WFI || inst === SRET || inst === DRET || inst === MRET) { uop.op2_sel := OP2_IMMC } .elsewhen (inst === JAL || inst === JALR) { uop.op2_sel := OP2_NEXT } .elsewhen (Seq(BCLR, BCLRI, BINV, BINVI, BSET, BSETI).map(_ === inst).orR) { uop.op2_sel := Mux(uop.lrs2_rtype === RT_FIX, OP2_RS2OH, OP2_IMMOH) } .elsewhen (cs.imm_sel === IS_U || cs.imm_sel === IS_I || cs.imm_sel === IS_S) { uop.op2_sel := OP2_IMM } uop.br_type := Seq( (BEQ , B_EQ ), (BNE , B_NE ), (BGE , B_GE ), (BGEU , B_GEU), (BLT , B_LT ), (BLTU , B_LTU), (JAL , B_J ), (JALR , B_JR ) ) .map { case (c, b) => Mux(inst === c, b, 0.U) } .reduce(_|_) io.deq.uop := uop } /** * Smaller Decode unit for the Frontend to decode different * branches. * Accepts EXPANDED RVC instructions */ class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle { val is_ret = Bool() val is_call = Bool() val target = UInt(vaddrBitsExtended.W) val cfi_type = UInt(CFI_SZ.W) // Is this branch a short forwards jump? val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W)) // Is this instruction allowed to be inside a sfb? val shadowable = Bool() } class BranchDecode(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val inst = Input(UInt(32.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val out = Output(new BranchDecodeSignals) }) val bpd_csignals = freechips.rocketchip.rocket.DecodeLogic(io.inst, List[BitPat](N, N, N, N, X), //// is br? //// | is jal? //// | | is jalr? //// | | | //// | | | shadowable //// | | | | has_rs2 //// | | | | | Seq[(BitPat, List[BitPat])]( JAL -> List(N, Y, N, N, X), JALR -> List(N, N, Y, N, X), BEQ -> List(Y, N, N, N, X), BNE -> List(Y, N, N, N, X), BGE -> List(Y, N, N, N, X), BGEU -> List(Y, N, N, N, X), BLT -> List(Y, N, N, N, X), BLTU -> List(Y, N, N, N, X), SLLI -> List(N, N, N, Y, N), SRLI -> List(N, N, N, Y, N), SRAI -> List(N, N, N, Y, N), ADDIW -> List(N, N, N, Y, N), SLLIW -> List(N, N, N, Y, N), SRAIW -> List(N, N, N, Y, N), SRLIW -> List(N, N, N, Y, N), ADDW -> List(N, N, N, Y, Y), SUBW -> List(N, N, N, Y, Y), SLLW -> List(N, N, N, Y, Y), SRAW -> List(N, N, N, Y, Y), SRLW -> List(N, N, N, Y, Y), LUI -> List(N, N, N, Y, N), ADDI -> List(N, N, N, Y, N), ANDI -> List(N, N, N, Y, N), ORI -> List(N, N, N, Y, N), XORI -> List(N, N, N, Y, N), SLTI -> List(N, N, N, Y, N), SLTIU -> List(N, N, N, Y, N), SLL -> List(N, N, N, Y, Y), ADD -> List(N, N, N, Y, Y), SUB -> List(N, N, N, Y, Y), SLT -> List(N, N, N, Y, Y), SLTU -> List(N, N, N, Y, Y), AND -> List(N, N, N, Y, Y), OR -> List(N, N, N, Y, Y), XOR -> List(N, N, N, Y, Y), SRA -> List(N, N, N, Y, Y), SRL -> List(N, N, N, Y, Y) )) val cs_is_br = bpd_csignals(0)(0) val cs_is_jal = bpd_csignals(1)(0) val cs_is_jalr = bpd_csignals(2)(0) val cs_is_shadowable = bpd_csignals(3)(0) val cs_has_rs2 = bpd_csignals(4)(0) io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0 io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen), ComputeJALTarget(io.pc, io.inst, xLen)) io.out.cfi_type := Mux(cs_is_jalr, CFI_JALR, Mux(cs_is_jal, CFI_JAL, Mux(cs_is_br, CFI_BR, CFI_X))) val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W)) // Is a sfb if it points forwards (offset is positive) io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U io.out.sfb_offset.bits := br_offset io.out.shadowable := cs_is_shadowable && ( !cs_has_rs2 || (GetRs1(io.inst) === GetRd(io.inst)) || (io.inst === ADD && GetRs1(io.inst) === X0) ) } /** * Track the current "branch mask", and give out the branch mask to each micro-op in Decode * (each micro-op in the machine has a branch mask which says which branches it * is being speculated under). * * @param pl_width pipeline width for the processor */ class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { // guess if the uop is a branch (we'll catch this later) val is_branch = Input(Vec(pl_width, Bool())) // lock in that it's actually a branch and will fire, so we update // the branch_masks. val will_fire = Input(Vec(pl_width, Bool())) // give out tag immediately (needed in rename) // mask can come later in the cycle val br_tag = Output(Vec(pl_width, UInt(brTagSz.W))) val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W))) // tell decoders the branch mask has filled up, but on the granularity // of an individual micro-op (so some micro-ops can go through) val is_full = Output(Vec(pl_width, Bool())) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val debug_branch_mask = Output(UInt(maxBrCount.W)) }) val branch_mask = RegInit(0.U(maxBrCount.W)) //------------------------------------------------------------- // Give out the branch tag to each branch micro-op var allocate_mask = branch_mask val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W))) for (w <- 0 until pl_width) { // TODO this is a loss of performance as we're blocking branches based on potentially fake branches io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w) // find br_tag and compute next br_mask val new_br_tag = Wire(UInt(brTagSz.W)) new_br_tag := 0.U tag_masks(w) := 0.U for (i <- maxBrCount-1 to 0 by -1) { when (~allocate_mask(i)) { new_br_tag := i.U tag_masks(w) := (1.U << i.U) } } io.br_tag(w) := new_br_tag allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask) } //------------------------------------------------------------- // Give out the branch mask to each micro-op // (kill off the bits that corresponded to branches that aren't going to fire) var curr_mask = branch_mask for (w <- 0 until pl_width) { io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask) curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask) } //------------------------------------------------------------- // Update the current branch_mask when (io.flush_pipeline) { branch_mask := 0.U } .otherwise { val mask = Mux(io.brupdate.b2.mispredict, io.brupdate.b2.uop.br_mask, ~(0.U(maxBrCount.W))) branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask } io.debug_branch_mask := branch_mask }
module DecodeUnit_1( // @[decode.scala:422:7] input clock, // @[decode.scala:422:7] input reset, // @[decode.scala:422:7] input [31:0] io_enq_uop_inst, // @[decode.scala:426:14] input [31:0] io_enq_uop_debug_inst, // @[decode.scala:426:14] input io_enq_uop_is_rvc, // @[decode.scala:426:14] input [39:0] io_enq_uop_debug_pc, // @[decode.scala:426:14] input io_enq_uop_is_sfb, // @[decode.scala:426:14] input [4:0] io_enq_uop_ftq_idx, // @[decode.scala:426:14] input io_enq_uop_edge_inst, // @[decode.scala:426:14] input [5:0] io_enq_uop_pc_lob, // @[decode.scala:426:14] input io_enq_uop_taken, // @[decode.scala:426:14] input io_enq_uop_xcpt_pf_if, // @[decode.scala:426:14] input io_enq_uop_xcpt_ae_if, // @[decode.scala:426:14] input io_enq_uop_bp_debug_if, // @[decode.scala:426:14] input io_enq_uop_bp_xcpt_if, // @[decode.scala:426:14] input [2:0] io_enq_uop_debug_fsrc, // @[decode.scala:426:14] output [31:0] io_deq_uop_inst, // @[decode.scala:426:14] output [31:0] io_deq_uop_debug_inst, // @[decode.scala:426:14] output io_deq_uop_is_rvc, // @[decode.scala:426:14] output [39:0] io_deq_uop_debug_pc, // @[decode.scala:426:14] output io_deq_uop_iq_type_0, // @[decode.scala:426:14] output io_deq_uop_iq_type_1, // @[decode.scala:426:14] output io_deq_uop_iq_type_2, // @[decode.scala:426:14] output io_deq_uop_iq_type_3, // @[decode.scala:426:14] output io_deq_uop_fu_code_0, // @[decode.scala:426:14] output io_deq_uop_fu_code_1, // @[decode.scala:426:14] output io_deq_uop_fu_code_2, // @[decode.scala:426:14] output io_deq_uop_fu_code_3, // @[decode.scala:426:14] output io_deq_uop_fu_code_4, // @[decode.scala:426:14] output io_deq_uop_fu_code_5, // @[decode.scala:426:14] output io_deq_uop_fu_code_6, // @[decode.scala:426:14] output io_deq_uop_fu_code_7, // @[decode.scala:426:14] output io_deq_uop_fu_code_8, // @[decode.scala:426:14] output io_deq_uop_fu_code_9, // @[decode.scala:426:14] output [3:0] io_deq_uop_br_type, // @[decode.scala:426:14] output io_deq_uop_is_sfb, // @[decode.scala:426:14] output io_deq_uop_is_fence, // @[decode.scala:426:14] output io_deq_uop_is_fencei, // @[decode.scala:426:14] output io_deq_uop_is_sfence, // @[decode.scala:426:14] output io_deq_uop_is_amo, // @[decode.scala:426:14] output io_deq_uop_is_eret, // @[decode.scala:426:14] output io_deq_uop_is_sys_pc2epc, // @[decode.scala:426:14] output io_deq_uop_is_rocc, // @[decode.scala:426:14] output io_deq_uop_is_mov, // @[decode.scala:426:14] output [4:0] io_deq_uop_ftq_idx, // @[decode.scala:426:14] output io_deq_uop_edge_inst, // @[decode.scala:426:14] output [5:0] io_deq_uop_pc_lob, // @[decode.scala:426:14] output io_deq_uop_taken, // @[decode.scala:426:14] output io_deq_uop_imm_rename, // @[decode.scala:426:14] output [2:0] io_deq_uop_imm_sel, // @[decode.scala:426:14] output [4:0] io_deq_uop_pimm, // @[decode.scala:426:14] output [19:0] io_deq_uop_imm_packed, // @[decode.scala:426:14] output [1:0] io_deq_uop_op1_sel, // @[decode.scala:426:14] output [2:0] io_deq_uop_op2_sel, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ldst, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_wen, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren1, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren2, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren3, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_swap12, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_swap23, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_ctrl_typeTagIn, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_ctrl_typeTagOut, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fromint, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_toint, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fastpipe, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fma, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_div, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_sqrt, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_wflags, // @[decode.scala:426:14] output io_deq_uop_exception, // @[decode.scala:426:14] output [63:0] io_deq_uop_exc_cause, // @[decode.scala:426:14] output [4:0] io_deq_uop_mem_cmd, // @[decode.scala:426:14] output [1:0] io_deq_uop_mem_size, // @[decode.scala:426:14] output io_deq_uop_mem_signed, // @[decode.scala:426:14] output io_deq_uop_uses_ldq, // @[decode.scala:426:14] output io_deq_uop_uses_stq, // @[decode.scala:426:14] output io_deq_uop_is_unique, // @[decode.scala:426:14] output io_deq_uop_flush_on_commit, // @[decode.scala:426:14] output [2:0] io_deq_uop_csr_cmd, // @[decode.scala:426:14] output io_deq_uop_ldst_is_rs1, // @[decode.scala:426:14] output [5:0] io_deq_uop_ldst, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs1, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs2, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs3, // @[decode.scala:426:14] output [1:0] io_deq_uop_dst_rtype, // @[decode.scala:426:14] output [1:0] io_deq_uop_lrs1_rtype, // @[decode.scala:426:14] output [1:0] io_deq_uop_lrs2_rtype, // @[decode.scala:426:14] output io_deq_uop_frs3_en, // @[decode.scala:426:14] output io_deq_uop_fcn_dw, // @[decode.scala:426:14] output [4:0] io_deq_uop_fcn_op, // @[decode.scala:426:14] output io_deq_uop_fp_val, // @[decode.scala:426:14] output [2:0] io_deq_uop_fp_rm, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_typ, // @[decode.scala:426:14] output io_deq_uop_xcpt_pf_if, // @[decode.scala:426:14] output io_deq_uop_xcpt_ae_if, // @[decode.scala:426:14] output io_deq_uop_bp_debug_if, // @[decode.scala:426:14] output io_deq_uop_bp_xcpt_if, // @[decode.scala:426:14] output [2:0] io_deq_uop_debug_fsrc, // @[decode.scala:426:14] input io_status_debug, // @[decode.scala:426:14] input io_status_cease, // @[decode.scala:426:14] input io_status_wfi, // @[decode.scala:426:14] input [1:0] io_status_dprv, // @[decode.scala:426:14] input io_status_dv, // @[decode.scala:426:14] input [1:0] io_status_prv, // @[decode.scala:426:14] input io_status_v, // @[decode.scala:426:14] input io_status_sd, // @[decode.scala:426:14] input io_status_mpv, // @[decode.scala:426:14] input io_status_gva, // @[decode.scala:426:14] input io_status_tsr, // @[decode.scala:426:14] input io_status_tw, // @[decode.scala:426:14] input io_status_tvm, // @[decode.scala:426:14] input io_status_mxr, // @[decode.scala:426:14] input io_status_sum, // @[decode.scala:426:14] input io_status_mprv, // @[decode.scala:426:14] input [1:0] io_status_fs, // @[decode.scala:426:14] input [1:0] io_status_mpp, // @[decode.scala:426:14] input io_status_spp, // @[decode.scala:426:14] input io_status_mpie, // @[decode.scala:426:14] input io_status_spie, // @[decode.scala:426:14] input io_status_mie, // @[decode.scala:426:14] input io_status_sie, // @[decode.scala:426:14] output [31:0] io_csr_decode_inst, // @[decode.scala:426:14] input io_csr_decode_fp_illegal, // @[decode.scala:426:14] input io_csr_decode_fp_csr, // @[decode.scala:426:14] input io_csr_decode_read_illegal, // @[decode.scala:426:14] input io_csr_decode_write_illegal, // @[decode.scala:426:14] input io_csr_decode_write_flush, // @[decode.scala:426:14] input io_csr_decode_system_illegal, // @[decode.scala:426:14] input io_csr_decode_virtual_access_illegal, // @[decode.scala:426:14] input io_csr_decode_virtual_system_illegal, // @[decode.scala:426:14] input [2:0] io_fcsr_rm, // @[decode.scala:426:14] input io_interrupt, // @[decode.scala:426:14] input [63:0] io_interrupt_cause // @[decode.scala:426:14] ); wire [31:0] io_enq_uop_inst_0 = io_enq_uop_inst; // @[decode.scala:422:7] wire [31:0] io_enq_uop_debug_inst_0 = io_enq_uop_debug_inst; // @[decode.scala:422:7] wire io_enq_uop_is_rvc_0 = io_enq_uop_is_rvc; // @[decode.scala:422:7] wire [39:0] io_enq_uop_debug_pc_0 = io_enq_uop_debug_pc; // @[decode.scala:422:7] wire io_enq_uop_is_sfb_0 = io_enq_uop_is_sfb; // @[decode.scala:422:7] wire [4:0] io_enq_uop_ftq_idx_0 = io_enq_uop_ftq_idx; // @[decode.scala:422:7] wire io_enq_uop_edge_inst_0 = io_enq_uop_edge_inst; // @[decode.scala:422:7] wire [5:0] io_enq_uop_pc_lob_0 = io_enq_uop_pc_lob; // @[decode.scala:422:7] wire io_enq_uop_taken_0 = io_enq_uop_taken; // @[decode.scala:422:7] wire io_enq_uop_xcpt_pf_if_0 = io_enq_uop_xcpt_pf_if; // @[decode.scala:422:7] wire io_enq_uop_xcpt_ae_if_0 = io_enq_uop_xcpt_ae_if; // @[decode.scala:422:7] wire io_enq_uop_bp_debug_if_0 = io_enq_uop_bp_debug_if; // @[decode.scala:422:7] wire io_enq_uop_bp_xcpt_if_0 = io_enq_uop_bp_xcpt_if; // @[decode.scala:422:7] wire [2:0] io_enq_uop_debug_fsrc_0 = io_enq_uop_debug_fsrc; // @[decode.scala:422:7] wire io_status_debug_0 = io_status_debug; // @[decode.scala:422:7] wire io_status_cease_0 = io_status_cease; // @[decode.scala:422:7] wire io_status_wfi_0 = io_status_wfi; // @[decode.scala:422:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[decode.scala:422:7] wire io_status_dv_0 = io_status_dv; // @[decode.scala:422:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[decode.scala:422:7] wire io_status_v_0 = io_status_v; // @[decode.scala:422:7] wire io_status_sd_0 = io_status_sd; // @[decode.scala:422:7] wire io_status_mpv_0 = io_status_mpv; // @[decode.scala:422:7] wire io_status_gva_0 = io_status_gva; // @[decode.scala:422:7] wire io_status_tsr_0 = io_status_tsr; // @[decode.scala:422:7] wire io_status_tw_0 = io_status_tw; // @[decode.scala:422:7] wire io_status_tvm_0 = io_status_tvm; // @[decode.scala:422:7] wire io_status_mxr_0 = io_status_mxr; // @[decode.scala:422:7] wire io_status_sum_0 = io_status_sum; // @[decode.scala:422:7] wire io_status_mprv_0 = io_status_mprv; // @[decode.scala:422:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[decode.scala:422:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[decode.scala:422:7] wire io_status_spp_0 = io_status_spp; // @[decode.scala:422:7] wire io_status_mpie_0 = io_status_mpie; // @[decode.scala:422:7] wire io_status_spie_0 = io_status_spie; // @[decode.scala:422:7] wire io_status_mie_0 = io_status_mie; // @[decode.scala:422:7] wire io_status_sie_0 = io_status_sie; // @[decode.scala:422:7] wire io_csr_decode_fp_illegal_0 = io_csr_decode_fp_illegal; // @[decode.scala:422:7] wire io_csr_decode_fp_csr_0 = io_csr_decode_fp_csr; // @[decode.scala:422:7] wire io_csr_decode_read_illegal_0 = io_csr_decode_read_illegal; // @[decode.scala:422:7] wire io_csr_decode_write_illegal_0 = io_csr_decode_write_illegal; // @[decode.scala:422:7] wire io_csr_decode_write_flush_0 = io_csr_decode_write_flush; // @[decode.scala:422:7] wire io_csr_decode_system_illegal_0 = io_csr_decode_system_illegal; // @[decode.scala:422:7] wire io_csr_decode_virtual_access_illegal_0 = io_csr_decode_virtual_access_illegal; // @[decode.scala:422:7] wire io_csr_decode_virtual_system_illegal_0 = io_csr_decode_virtual_system_illegal; // @[decode.scala:422:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[decode.scala:422:7] wire io_interrupt_0 = io_interrupt; // @[decode.scala:422:7] wire [63:0] io_interrupt_cause_0 = io_interrupt_cause; // @[decode.scala:422:7] wire [1:0] io_status_sxl = 2'h2; // @[decode.scala:422:7] wire [1:0] io_status_uxl = 2'h2; // @[decode.scala:422:7] wire io_csr_decode_vector_illegal = 1'h1; // @[decode.scala:422:7] wire io_csr_decode_rocc_illegal = 1'h1; // @[decode.scala:422:7] wire _id_illegal_insn_T_6 = 1'h1; // @[decode.scala:464:33] wire [7:0] io_status_zero1 = 8'h0; // @[decode.scala:422:7, :426:14] wire [22:0] io_status_zero2 = 23'h0; // @[decode.scala:422:7, :426:14] wire [31:0] io_status_isa = 32'h14112D; // @[decode.scala:422:7, :426:14] wire [5:0] io_enq_uop_ldst = 6'h0; // @[decode.scala:422:7, :426:14] wire [5:0] io_enq_uop_lrs1 = 6'h0; // @[decode.scala:422:7, :426:14] wire [5:0] io_enq_uop_lrs2 = 6'h0; // @[decode.scala:422:7, :426:14] wire [5:0] io_enq_uop_lrs3 = 6'h0; // @[decode.scala:422:7, :426:14] wire [63:0] io_enq_uop_exc_cause = 64'h0; // @[decode.scala:422:7, :426:14] wire [6:0] io_enq_uop_rob_idx = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_rob_idx = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_rob_idx = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [1:0] io_enq_uop_op1_sel = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_ctrl_typeTagIn = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_ctrl_typeTagOut = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_rxq_idx = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_mem_size = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_dst_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_lrs1_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_lrs2_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_typ = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_rxq_idx = 2'h0; // @[decode.scala:422:7] wire [1:0] io_status_xs = 2'h0; // @[decode.scala:422:7] wire [1:0] io_status_vs = 2'h0; // @[decode.scala:422:7] wire [1:0] uop_rxq_idx = 2'h0; // @[decode.scala:428:17] wire [19:0] io_enq_uop_imm_packed = 20'h0; // @[decode.scala:422:7] wire [4:0] io_enq_uop_pimm = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_ldq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_stq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_mem_cmd = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_fcn_op = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_deq_uop_ldq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_deq_uop_stq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_deq_uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] uop_ldq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] uop_stq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [3:0] io_enq_uop_br_tag = 4'h0; // @[decode.scala:422:7] wire [3:0] io_enq_uop_br_type = 4'h0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_br_tag = 4'h0; // @[decode.scala:422:7] wire [3:0] uop_br_tag = 4'h0; // @[decode.scala:428:17] wire [15:0] io_enq_uop_br_mask = 16'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [15:0] io_deq_uop_br_mask = 16'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [15:0] uop_br_mask = 16'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [2:0] io_enq_uop_iw_p1_speculative_child = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_iw_p2_speculative_child = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_dis_col_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_imm_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_op2_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_csr_cmd = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_fp_rm = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_debug_tsrc = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_iw_p1_speculative_child = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_iw_p2_speculative_child = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_dis_col_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_debug_tsrc = 3'h0; // @[decode.scala:422:7] wire [2:0] uop_iw_p1_speculative_child = 3'h0; // @[decode.scala:428:17] wire [2:0] uop_iw_p2_speculative_child = 3'h0; // @[decode.scala:428:17] wire [2:0] uop_dis_col_sel = 3'h0; // @[decode.scala:428:17] wire [2:0] uop_debug_tsrc = 3'h0; // @[decode.scala:428:17] wire io_enq_uop_iq_type_0 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_0 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_4 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_5 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_6 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_7 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_8 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_9 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_fence = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_fencei = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_sfence = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_amo = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_eret = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_sys_pc2epc = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_rocc = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_mov = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_imm_rename = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ldst = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_wen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_swap12 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_swap23 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fromint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_toint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fastpipe = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fma = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_div = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_sqrt = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_wflags = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_vec = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs1_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs2_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs3_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_ppred_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_exception = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_mem_signed = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_uses_ldq = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_uses_stq = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_unique = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_flush_on_commit = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_frs3_en = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fcn_dw = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_val = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_vec = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs1_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs2_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs3_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_ppred_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:422:7] wire io_status_mbe = 1'h0; // @[decode.scala:422:7] wire io_status_sbe = 1'h0; // @[decode.scala:422:7] wire io_status_sd_rv32 = 1'h0; // @[decode.scala:422:7] wire io_status_ube = 1'h0; // @[decode.scala:422:7] wire io_status_upie = 1'h0; // @[decode.scala:422:7] wire io_status_hie = 1'h0; // @[decode.scala:422:7] wire io_status_uie = 1'h0; // @[decode.scala:422:7] wire io_csr_decode_vector_csr = 1'h0; // @[decode.scala:422:7] wire uop_iw_issued = 1'h0; // @[decode.scala:428:17] wire uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:428:17] wire uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:428:17] wire uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_fp_ctrl_vec = 1'h0; // @[decode.scala:428:17] wire uop_prs1_busy = 1'h0; // @[decode.scala:428:17] wire uop_prs2_busy = 1'h0; // @[decode.scala:428:17] wire uop_prs3_busy = 1'h0; // @[decode.scala:428:17] wire uop_ppred_busy = 1'h0; // @[decode.scala:428:17] wire uop_xcpt_ma_if = 1'h0; // @[decode.scala:428:17] wire cs_fp_vec = 1'h0; // @[decode.scala:447:16] wire _id_illegal_insn_T_7 = 1'h0; // @[decode.scala:464:19] wire _id_illegal_insn_T_8 = 1'h0; // @[decode.scala:464:16] wire [31:0] uop_inst = io_enq_uop_inst_0; // @[decode.scala:422:7, :428:17] wire [31:0] uop_debug_inst = io_enq_uop_debug_inst_0; // @[decode.scala:422:7, :428:17] wire uop_is_rvc = io_enq_uop_is_rvc_0; // @[decode.scala:422:7, :428:17] wire [39:0] uop_debug_pc = io_enq_uop_debug_pc_0; // @[decode.scala:422:7, :428:17] wire uop_is_sfb = io_enq_uop_is_sfb_0; // @[decode.scala:422:7, :428:17] wire [4:0] uop_ftq_idx = io_enq_uop_ftq_idx_0; // @[decode.scala:422:7, :428:17] wire uop_edge_inst = io_enq_uop_edge_inst_0; // @[decode.scala:422:7, :428:17] wire [5:0] uop_pc_lob = io_enq_uop_pc_lob_0; // @[decode.scala:422:7, :428:17] wire uop_taken = io_enq_uop_taken_0; // @[decode.scala:422:7, :428:17] wire uop_xcpt_pf_if = io_enq_uop_xcpt_pf_if_0; // @[decode.scala:422:7, :428:17] wire uop_xcpt_ae_if = io_enq_uop_xcpt_ae_if_0; // @[decode.scala:422:7, :428:17] wire uop_bp_debug_if = io_enq_uop_bp_debug_if_0; // @[decode.scala:422:7, :428:17] wire uop_bp_xcpt_if = io_enq_uop_bp_xcpt_if_0; // @[decode.scala:422:7, :428:17] wire [2:0] uop_debug_fsrc = io_enq_uop_debug_fsrc_0; // @[decode.scala:422:7, :428:17] wire uop_iq_type_0; // @[decode.scala:428:17] wire uop_iq_type_1; // @[decode.scala:428:17] wire uop_iq_type_2; // @[decode.scala:428:17] wire uop_iq_type_3; // @[decode.scala:428:17] wire uop_fu_code_0; // @[decode.scala:428:17] wire uop_fu_code_1; // @[decode.scala:428:17] wire uop_fu_code_2; // @[decode.scala:428:17] wire uop_fu_code_3; // @[decode.scala:428:17] wire uop_fu_code_4; // @[decode.scala:428:17] wire uop_fu_code_5; // @[decode.scala:428:17] wire uop_fu_code_6; // @[decode.scala:428:17] wire uop_fu_code_7; // @[decode.scala:428:17] wire uop_fu_code_8; // @[decode.scala:428:17] wire uop_fu_code_9; // @[decode.scala:428:17] wire [3:0] uop_br_type; // @[decode.scala:428:17] wire uop_is_fence; // @[decode.scala:428:17] wire uop_is_fencei; // @[decode.scala:428:17] wire uop_is_sfence; // @[decode.scala:428:17] wire uop_is_amo; // @[decode.scala:428:17] wire uop_is_eret; // @[decode.scala:428:17] wire uop_is_sys_pc2epc; // @[decode.scala:428:17] wire uop_is_rocc; // @[decode.scala:428:17] wire uop_is_mov; // @[decode.scala:428:17] wire uop_imm_rename; // @[decode.scala:428:17] wire [2:0] uop_imm_sel; // @[decode.scala:428:17] wire [4:0] uop_pimm; // @[decode.scala:428:17] wire [19:0] uop_imm_packed; // @[decode.scala:428:17] wire [1:0] uop_op1_sel; // @[decode.scala:428:17] wire [2:0] uop_op2_sel; // @[decode.scala:428:17] wire uop_fp_ctrl_ldst; // @[decode.scala:428:17] wire uop_fp_ctrl_wen; // @[decode.scala:428:17] wire uop_fp_ctrl_ren1; // @[decode.scala:428:17] wire uop_fp_ctrl_ren2; // @[decode.scala:428:17] wire uop_fp_ctrl_ren3; // @[decode.scala:428:17] wire uop_fp_ctrl_swap12; // @[decode.scala:428:17] wire uop_fp_ctrl_swap23; // @[decode.scala:428:17] wire [1:0] uop_fp_ctrl_typeTagIn; // @[decode.scala:428:17] wire [1:0] uop_fp_ctrl_typeTagOut; // @[decode.scala:428:17] wire uop_fp_ctrl_fromint; // @[decode.scala:428:17] wire uop_fp_ctrl_toint; // @[decode.scala:428:17] wire uop_fp_ctrl_fastpipe; // @[decode.scala:428:17] wire uop_fp_ctrl_fma; // @[decode.scala:428:17] wire uop_fp_ctrl_div; // @[decode.scala:428:17] wire uop_fp_ctrl_sqrt; // @[decode.scala:428:17] wire uop_fp_ctrl_wflags; // @[decode.scala:428:17] wire uop_exception; // @[decode.scala:428:17] wire [63:0] uop_exc_cause; // @[decode.scala:428:17] wire [4:0] uop_mem_cmd; // @[decode.scala:428:17] wire [1:0] uop_mem_size; // @[decode.scala:428:17] wire uop_mem_signed; // @[decode.scala:428:17] wire uop_uses_ldq; // @[decode.scala:428:17] wire uop_uses_stq; // @[decode.scala:428:17] wire uop_is_unique; // @[decode.scala:428:17] wire uop_flush_on_commit; // @[decode.scala:428:17] wire [2:0] uop_csr_cmd; // @[decode.scala:428:17] wire uop_ldst_is_rs1; // @[decode.scala:428:17] wire [5:0] uop_ldst; // @[decode.scala:428:17] wire [5:0] uop_lrs1; // @[decode.scala:428:17] wire [5:0] uop_lrs2; // @[decode.scala:428:17] wire [5:0] uop_lrs3; // @[decode.scala:428:17] wire [1:0] uop_dst_rtype; // @[decode.scala:428:17] wire [1:0] uop_lrs1_rtype; // @[decode.scala:428:17] wire [1:0] uop_lrs2_rtype; // @[decode.scala:428:17] wire uop_frs3_en; // @[decode.scala:428:17] wire uop_fcn_dw; // @[decode.scala:428:17] wire [4:0] uop_fcn_op; // @[decode.scala:428:17] wire uop_fp_val; // @[decode.scala:428:17] wire [2:0] uop_fp_rm; // @[decode.scala:428:17] wire [1:0] uop_fp_typ; // @[decode.scala:428:17] wire io_deq_uop_iq_type_0_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_1_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_2_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_3_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_0_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_1_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_2_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_3_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_4_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_5_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_6_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_7_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_8_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_9_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ldst_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_wen_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren1_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren2_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren3_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_swap12_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_swap23_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_ctrl_typeTagIn_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_ctrl_typeTagOut_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fromint_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_toint_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fastpipe_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fma_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_div_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_sqrt_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_wflags_0; // @[decode.scala:422:7] wire [31:0] io_deq_uop_inst_0; // @[decode.scala:422:7] wire [31:0] io_deq_uop_debug_inst_0; // @[decode.scala:422:7] wire io_deq_uop_is_rvc_0; // @[decode.scala:422:7] wire [39:0] io_deq_uop_debug_pc_0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_br_type_0; // @[decode.scala:422:7] wire io_deq_uop_is_sfb_0; // @[decode.scala:422:7] wire io_deq_uop_is_fence_0; // @[decode.scala:422:7] wire io_deq_uop_is_fencei_0; // @[decode.scala:422:7] wire io_deq_uop_is_sfence_0; // @[decode.scala:422:7] wire io_deq_uop_is_amo_0; // @[decode.scala:422:7] wire io_deq_uop_is_eret_0; // @[decode.scala:422:7] wire io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:422:7] wire io_deq_uop_is_rocc_0; // @[decode.scala:422:7] wire io_deq_uop_is_mov_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_ftq_idx_0; // @[decode.scala:422:7] wire io_deq_uop_edge_inst_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_pc_lob_0; // @[decode.scala:422:7] wire io_deq_uop_taken_0; // @[decode.scala:422:7] wire io_deq_uop_imm_rename_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_imm_sel_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_pimm_0; // @[decode.scala:422:7] wire [19:0] io_deq_uop_imm_packed_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_op1_sel_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_op2_sel_0; // @[decode.scala:422:7] wire io_deq_uop_exception_0; // @[decode.scala:422:7] wire [63:0] io_deq_uop_exc_cause_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_mem_cmd_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_mem_size_0; // @[decode.scala:422:7] wire io_deq_uop_mem_signed_0; // @[decode.scala:422:7] wire io_deq_uop_uses_ldq_0; // @[decode.scala:422:7] wire io_deq_uop_uses_stq_0; // @[decode.scala:422:7] wire io_deq_uop_is_unique_0; // @[decode.scala:422:7] wire io_deq_uop_flush_on_commit_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_csr_cmd_0; // @[decode.scala:422:7] wire io_deq_uop_ldst_is_rs1_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_ldst_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs1_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs2_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs3_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_dst_rtype_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_lrs1_rtype_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_lrs2_rtype_0; // @[decode.scala:422:7] wire io_deq_uop_frs3_en_0; // @[decode.scala:422:7] wire io_deq_uop_fcn_dw_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_fcn_op_0; // @[decode.scala:422:7] wire io_deq_uop_fp_val_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_fp_rm_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_typ_0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_pf_if_0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_ae_if_0; // @[decode.scala:422:7] wire io_deq_uop_bp_debug_if_0; // @[decode.scala:422:7] wire io_deq_uop_bp_xcpt_if_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_debug_fsrc_0; // @[decode.scala:422:7] wire [31:0] io_csr_decode_inst_0; // @[decode.scala:422:7] assign io_deq_uop_inst_0 = uop_inst; // @[decode.scala:422:7, :428:17] assign io_csr_decode_inst_0 = uop_inst; // @[decode.scala:422:7, :428:17] wire [31:0] cs_decoder_decoded_plaInput = uop_inst; // @[pla.scala:77:22] wire [31:0] _uop_is_sys_pc2epc_T = uop_inst; // @[decode.scala:428:17, :529:29] wire [31:0] _uop_is_sys_pc2epc_T_2 = uop_inst; // @[decode.scala:428:17, :529:48] wire [31:0] _uop_is_eret_T = uop_inst; // @[decode.scala:428:17, :530:26] wire [31:0] _uop_is_eret_T_2 = uop_inst; // @[decode.scala:428:17, :530:44] wire [31:0] _uop_is_eret_T_5 = uop_inst; // @[decode.scala:428:17, :530:63] wire [31:0] _uop_is_eret_T_8 = uop_inst; // @[decode.scala:428:17, :530:80] wire [31:0] _uop_is_eret_T_11 = uop_inst; // @[decode.scala:428:17, :530:97] assign io_deq_uop_debug_inst_0 = uop_debug_inst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_is_rvc_0 = uop_is_rvc; // @[decode.scala:422:7, :428:17] assign io_deq_uop_debug_pc_0 = uop_debug_pc; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_0_T_2; // @[decode.scala:489:98] assign io_deq_uop_iq_type_0_0 = uop_iq_type_0; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_1_T_6; // @[decode.scala:487:98] assign io_deq_uop_iq_type_1_0 = uop_iq_type_1; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_2_T; // @[decode.scala:488:84] assign io_deq_uop_iq_type_2_0 = uop_iq_type_2; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_3_T_4; // @[decode.scala:490:98] assign io_deq_uop_iq_type_3_0 = uop_iq_type_3; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_0_0 = uop_fu_code_0; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_1_0 = uop_fu_code_1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_2_0 = uop_fu_code_2; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_3_0 = uop_fu_code_3; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_4_0 = uop_fu_code_4; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_5_0 = uop_fu_code_5; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_6_0 = uop_fu_code_6; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_7_0 = uop_fu_code_7; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_8_0 = uop_fu_code_8; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_9_0 = uop_fu_code_9; // @[decode.scala:422:7, :428:17] wire [3:0] _uop_br_type_T_30; // @[decode.scala:604:62] assign io_deq_uop_br_type_0 = uop_br_type; // @[decode.scala:422:7, :428:17] assign io_deq_uop_is_sfb_0 = uop_is_sfb; // @[decode.scala:422:7, :428:17] wire _uop_is_fence_T_1; // @[decode.scala:526:26] assign io_deq_uop_is_fence_0 = uop_is_fence; // @[decode.scala:422:7, :428:17] wire _uop_is_fencei_T_1; // @[decode.scala:527:26] assign io_deq_uop_is_fencei_0 = uop_is_fencei; // @[decode.scala:422:7, :428:17] wire _uop_is_sfence_T_1; // @[decode.scala:528:26] assign io_deq_uop_is_sfence_0 = uop_is_sfence; // @[decode.scala:422:7, :428:17] wire cs_is_amo; // @[decode.scala:447:16] assign io_deq_uop_is_amo_0 = uop_is_amo; // @[decode.scala:422:7, :428:17] wire _uop_is_eret_T_13; // @[decode.scala:530:89] assign io_deq_uop_is_eret_0 = uop_is_eret; // @[decode.scala:422:7, :428:17] wire _uop_is_sys_pc2epc_T_4; // @[decode.scala:529:40] assign io_deq_uop_is_sys_pc2epc_0 = uop_is_sys_pc2epc; // @[decode.scala:422:7, :428:17] wire _uop_is_rocc_T_18; // @[decode.scala:532:81] assign io_deq_uop_is_rocc_0 = uop_is_rocc; // @[decode.scala:422:7, :428:17] wire _id_illegal_insn_T_4 = uop_is_rocc; // @[decode.scala:428:17, :463:18] wire _uop_is_mov_T_3; // @[decode.scala:485:34] assign io_deq_uop_is_mov_0 = uop_is_mov; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ftq_idx_0 = uop_ftq_idx; // @[decode.scala:422:7, :428:17] assign io_deq_uop_edge_inst_0 = uop_edge_inst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_pc_lob_0 = uop_pc_lob; // @[decode.scala:422:7, :428:17] assign io_deq_uop_taken_0 = uop_taken; // @[decode.scala:422:7, :428:17] assign io_deq_uop_imm_rename_0 = uop_imm_rename; // @[decode.scala:422:7, :428:17] assign io_deq_uop_imm_sel_0 = uop_imm_sel; // @[decode.scala:422:7, :428:17] assign io_deq_uop_pimm_0 = uop_pimm; // @[decode.scala:422:7, :428:17] wire [19:0] imm_packed; // @[decode.scala:541:23] assign io_deq_uop_imm_packed_0 = uop_imm_packed; // @[decode.scala:422:7, :428:17] assign io_deq_uop_op1_sel_0 = uop_op1_sel; // @[decode.scala:422:7, :428:17] assign io_deq_uop_op2_sel_0 = uop_op2_sel; // @[decode.scala:422:7, :428:17] wire cs_fp_ldst; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ldst_0 = uop_fp_ctrl_ldst; // @[decode.scala:422:7, :428:17] wire cs_fp_wen; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_wen_0 = uop_fp_ctrl_wen; // @[decode.scala:422:7, :428:17] wire cs_fp_ren1; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren1_0 = uop_fp_ctrl_ren1; // @[decode.scala:422:7, :428:17] wire cs_fp_ren2; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren2_0 = uop_fp_ctrl_ren2; // @[decode.scala:422:7, :428:17] wire cs_fp_ren3; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren3_0 = uop_fp_ctrl_ren3; // @[decode.scala:422:7, :428:17] wire cs_fp_swap12; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_swap12_0 = uop_fp_ctrl_swap12; // @[decode.scala:422:7, :428:17] wire cs_fp_swap23; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_swap23_0 = uop_fp_ctrl_swap23; // @[decode.scala:422:7, :428:17] wire [1:0] cs_fp_typeTagIn; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_typeTagIn_0 = uop_fp_ctrl_typeTagIn; // @[decode.scala:422:7, :428:17] wire [1:0] cs_fp_typeTagOut; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_typeTagOut_0 = uop_fp_ctrl_typeTagOut; // @[decode.scala:422:7, :428:17] wire cs_fp_fromint; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fromint_0 = uop_fp_ctrl_fromint; // @[decode.scala:422:7, :428:17] wire cs_fp_toint; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_toint_0 = uop_fp_ctrl_toint; // @[decode.scala:422:7, :428:17] wire cs_fp_fastpipe; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fastpipe_0 = uop_fp_ctrl_fastpipe; // @[decode.scala:422:7, :428:17] wire cs_fp_fma; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fma_0 = uop_fp_ctrl_fma; // @[decode.scala:422:7, :428:17] wire cs_fp_div; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_div_0 = uop_fp_ctrl_div; // @[decode.scala:422:7, :428:17] wire cs_fp_sqrt; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_sqrt_0 = uop_fp_ctrl_sqrt; // @[decode.scala:422:7, :428:17] wire cs_fp_wflags; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_wflags_0 = uop_fp_ctrl_wflags; // @[decode.scala:422:7, :428:17] wire xcpt_valid; // @[decode.scala:470:26] assign io_deq_uop_exception_0 = uop_exception; // @[decode.scala:422:7, :428:17] wire [63:0] xcpt_cause; // @[Mux.scala:50:70] assign io_deq_uop_exc_cause_0 = uop_exc_cause; // @[decode.scala:422:7, :428:17] wire [4:0] cs_mem_cmd; // @[decode.scala:447:16] assign io_deq_uop_mem_cmd_0 = uop_mem_cmd; // @[decode.scala:422:7, :428:17] wire [1:0] _uop_mem_size_T_7; // @[decode.scala:521:24] assign io_deq_uop_mem_size_0 = uop_mem_size; // @[decode.scala:422:7, :428:17] wire _uop_mem_signed_T_1; // @[decode.scala:522:21] assign io_deq_uop_mem_signed_0 = uop_mem_signed; // @[decode.scala:422:7, :428:17] wire cs_uses_ldq; // @[decode.scala:447:16] assign io_deq_uop_uses_ldq_0 = uop_uses_ldq; // @[decode.scala:422:7, :428:17] wire cs_uses_stq; // @[decode.scala:447:16] assign io_deq_uop_uses_stq_0 = uop_uses_stq; // @[decode.scala:422:7, :428:17] wire cs_inst_unique; // @[decode.scala:447:16] assign io_deq_uop_is_unique_0 = uop_is_unique; // @[decode.scala:422:7, :428:17] wire _uop_flush_on_commit_T_3; // @[decode.scala:533:45] assign io_deq_uop_flush_on_commit_0 = uop_flush_on_commit; // @[decode.scala:422:7, :428:17] assign io_deq_uop_csr_cmd_0 = uop_csr_cmd; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ldst_is_rs1_0 = uop_ldst_is_rs1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ldst_0 = uop_ldst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs1_0 = uop_lrs1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs2_0 = uop_lrs2; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs3_0 = uop_lrs3; // @[decode.scala:422:7, :428:17] wire [1:0] cs_dst_type; // @[decode.scala:447:16] assign io_deq_uop_dst_rtype_0 = uop_dst_rtype; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs1_rtype_0 = uop_lrs1_rtype; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs2_rtype_0 = uop_lrs2_rtype; // @[decode.scala:422:7, :428:17] wire cs_frs3_en; // @[decode.scala:447:16] assign io_deq_uop_frs3_en_0 = uop_frs3_en; // @[decode.scala:422:7, :428:17] wire cs_fcn_dw; // @[decode.scala:447:16] assign io_deq_uop_fcn_dw_0 = uop_fcn_dw; // @[decode.scala:422:7, :428:17] wire [4:0] cs_fcn_op; // @[decode.scala:447:16] assign io_deq_uop_fcn_op_0 = uop_fcn_op; // @[decode.scala:422:7, :428:17] wire cs_fp_val; // @[decode.scala:447:16] assign io_deq_uop_fp_val_0 = uop_fp_val; // @[decode.scala:422:7, :428:17] wire [2:0] _uop_fp_rm_T_3; // @[decode.scala:556:21] assign io_deq_uop_fp_rm_0 = uop_fp_rm; // @[decode.scala:422:7, :428:17] wire [1:0] _uop_fp_typ_T; // @[decode.scala:557:22] assign io_deq_uop_fp_typ_0 = uop_fp_typ; // @[decode.scala:422:7, :428:17] assign io_deq_uop_xcpt_pf_if_0 = uop_xcpt_pf_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_xcpt_ae_if_0 = uop_xcpt_ae_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_bp_debug_if_0 = uop_bp_debug_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_bp_xcpt_if_0 = uop_bp_xcpt_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_debug_fsrc_0 = uop_debug_fsrc; // @[decode.scala:422:7, :428:17] wire [4:0] LDST = uop_inst[11:7]; // @[decode.scala:428:17, :441:18] wire [4:0] _di24_20_T_3 = uop_inst[11:7]; // @[decode.scala:428:17, :441:18, :540:69] wire [4:0] LRS1 = uop_inst[19:15]; // @[decode.scala:428:17, :442:18] wire [4:0] LRS2 = uop_inst[24:20]; // @[decode.scala:428:17, :443:18] wire [4:0] _di24_20_T_4 = uop_inst[24:20]; // @[decode.scala:428:17, :443:18, :540:81] wire [4:0] LRS3 = uop_inst[31:27]; // @[decode.scala:428:17, :444:18] wire cs_decoder_0; // @[Decode.scala:50:77] wire cs_decoder_1; // @[Decode.scala:50:77] assign uop_fp_val = cs_fp_val; // @[decode.scala:428:17, :447:16] wire [9:0] cs_decoder_2; // @[Decode.scala:50:77] wire [1:0] cs_decoder_3; // @[Decode.scala:50:77] assign uop_dst_rtype = cs_dst_type; // @[decode.scala:428:17, :447:16] wire [1:0] cs_decoder_4; // @[Decode.scala:50:77] wire [1:0] cs_decoder_5; // @[Decode.scala:50:77] wire cs_decoder_6; // @[Decode.scala:50:77] assign uop_frs3_en = cs_frs3_en; // @[decode.scala:428:17, :447:16] wire [2:0] cs_decoder_7; // @[Decode.scala:50:77] wire cs_decoder_8; // @[Decode.scala:50:77] assign uop_uses_ldq = cs_uses_ldq; // @[decode.scala:428:17, :447:16] wire cs_decoder_9; // @[Decode.scala:50:77] assign uop_uses_stq = cs_uses_stq; // @[decode.scala:428:17, :447:16] wire cs_decoder_10; // @[Decode.scala:50:77] assign uop_is_amo = cs_is_amo; // @[decode.scala:428:17, :447:16] wire [4:0] cs_decoder_11; // @[Decode.scala:50:77] assign uop_mem_cmd = cs_mem_cmd; // @[decode.scala:428:17, :447:16] wire cs_decoder_12; // @[Decode.scala:50:77] assign uop_is_unique = cs_inst_unique; // @[decode.scala:428:17, :447:16] wire cs_decoder_13; // @[Decode.scala:50:77] wire [2:0] cs_decoder_14; // @[Decode.scala:50:77] wire cs_decoder_15; // @[Decode.scala:50:77] assign uop_fcn_dw = cs_fcn_dw; // @[decode.scala:428:17, :447:16] wire [4:0] cs_decoder_16; // @[Decode.scala:50:77] assign uop_fcn_op = cs_fcn_op; // @[decode.scala:428:17, :447:16] wire cs_decoder_17; // @[Decode.scala:50:77] assign uop_fp_ctrl_ldst = cs_fp_ldst; // @[decode.scala:428:17, :447:16] wire cs_decoder_18; // @[Decode.scala:50:77] assign uop_fp_ctrl_wen = cs_fp_wen; // @[decode.scala:428:17, :447:16] wire cs_decoder_19; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren1 = cs_fp_ren1; // @[decode.scala:428:17, :447:16] wire cs_decoder_20; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren2 = cs_fp_ren2; // @[decode.scala:428:17, :447:16] wire cs_decoder_21; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren3 = cs_fp_ren3; // @[decode.scala:428:17, :447:16] wire cs_decoder_22; // @[Decode.scala:50:77] assign uop_fp_ctrl_swap12 = cs_fp_swap12; // @[decode.scala:428:17, :447:16] wire cs_decoder_23; // @[Decode.scala:50:77] assign uop_fp_ctrl_swap23 = cs_fp_swap23; // @[decode.scala:428:17, :447:16] assign uop_fp_ctrl_typeTagIn = cs_fp_typeTagIn; // @[decode.scala:428:17, :447:16] assign uop_fp_ctrl_typeTagOut = cs_fp_typeTagOut; // @[decode.scala:428:17, :447:16] wire cs_decoder_26; // @[Decode.scala:50:77] assign uop_fp_ctrl_fromint = cs_fp_fromint; // @[decode.scala:428:17, :447:16] wire cs_decoder_27; // @[Decode.scala:50:77] assign uop_fp_ctrl_toint = cs_fp_toint; // @[decode.scala:428:17, :447:16] wire cs_decoder_28; // @[Decode.scala:50:77] assign uop_fp_ctrl_fastpipe = cs_fp_fastpipe; // @[decode.scala:428:17, :447:16] wire cs_decoder_29; // @[Decode.scala:50:77] assign uop_fp_ctrl_fma = cs_fp_fma; // @[decode.scala:428:17, :447:16] wire cs_decoder_30; // @[Decode.scala:50:77] assign uop_fp_ctrl_div = cs_fp_div; // @[decode.scala:428:17, :447:16] wire cs_decoder_31; // @[Decode.scala:50:77] assign uop_fp_ctrl_sqrt = cs_fp_sqrt; // @[decode.scala:428:17, :447:16] wire cs_decoder_32; // @[Decode.scala:50:77] assign uop_fp_ctrl_wflags = cs_fp_wflags; // @[decode.scala:428:17, :447:16] wire cs_legal; // @[decode.scala:447:16] wire [9:0] cs_fu_code; // @[decode.scala:447:16] wire [1:0] cs_rs1_type; // @[decode.scala:447:16] wire [1:0] cs_rs2_type; // @[decode.scala:447:16] wire [2:0] cs_imm_sel; // @[decode.scala:447:16] wire cs_flush_on_commit; // @[decode.scala:447:16] wire [2:0] cs_csr_cmd; // @[decode.scala:447:16] wire [31:0] cs_decoder_decoded_invInputs = ~cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [56:0] cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [56:0] cs_decoder_decoded; // @[pla.scala:81:23] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo = {cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi = {cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T = {cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_81_2 = &_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_1 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_1 = {cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_85_2 = &_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_2 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_2 = {cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_10_2 = &_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_3 = {cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_26_2 = &_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_4 = {cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_100_2 = &_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_5 = {cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_88_2 = &_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_6 = {cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_62_2 = &_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_7 = {cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_77_2 = &_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:90:45, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_8 = {cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_29_2 = &_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_110_2 = &_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_10 = {cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_61_2 = &_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_11 = {cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_166_2 = &_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_12 = {cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_8_2 = &_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_13 = {cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_80_2 = &_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_14 = {cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_14_2 = &_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_15 = {cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_56_2 = &_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_16 = {cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_43_2 = &_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _cs_decoder_decoded_andMatrixOutputs_T_17 = {cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_157_2 = &_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_17 = cs_decoder_decoded_andMatrixOutputs_157_2; // @[pla.scala:98:70, :114:36] wire _cs_decoder_decoded_orMatrixOutputs_T_63 = cs_decoder_decoded_andMatrixOutputs_157_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_18 = {cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_123_2 = &_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_19 = {cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_102_2 = &_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_20 = {cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_140_2 = &_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_21 = {cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_21_2 = &_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_22 = {cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_145_2 = &_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_23 = {cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_161_2 = &_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_16 = cs_decoder_decoded_andMatrixOutputs_161_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_24 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_24 = {cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_79_2 = &_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_25 = {cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_33_2 = &_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_26 = {cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_112_2 = &_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_27 = {cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_168_2 = &_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_28 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_28 = {cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_138_2 = &_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_29 = {cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_47_2 = &_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_30 = {cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_71_2 = &_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_31 = {cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_105_2 = &_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_32 = {cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_52_2 = &_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_33 = {cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_86_2 = &_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_34 = {cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_0_2 = &_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_76_2 = &_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_36 = {cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_160_2 = &_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_34 = cs_decoder_decoded_andMatrixOutputs_160_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_37 = {cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_120_2 = &_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_38 = {cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_45_2 = &_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_39 = {cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_162_2 = &_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_40 = {cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_73_2 = &_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_41 = {cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_18_2 = &_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_42 = {cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_111_2 = &_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_43 = {cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_153_2 = &_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_44 = {cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_107_2 = &_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_45 = {cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_17_2 = &_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_49 = cs_decoder_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_46 = {cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_167_2 = &_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_47 = {cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_113_2 = &_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_48 = {cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_42_2 = &_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_49 = {cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_131_2 = &_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_50 = {cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_1_2 = &_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_51 = {cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_136_2 = &_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_52 = {cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_39_2 = &_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_53 = {cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_108_2 = &_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_54 = {cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_165_2 = &_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_55 = {cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_127_2 = &_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_56 = {cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_135_2 = &_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_114_2 = &_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_58 = {cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_155_2 = &_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_59 = {cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_6_2 = &_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_60 = {cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_75_2 = &_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_61 = {cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_72_2 = &_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_62 = {cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_96_2 = &_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_63 = {cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_149_2 = &_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_64 = {cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_144_2 = &_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_65 = {cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_3_2 = &_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_66 = {cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_13_2 = &_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_67 = {cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_141_2 = &_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_68 = {cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_93_2 = &_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_69 = {cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_60_2 = &_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_70 = {cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_69_2 = &_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_71 = {cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_124_2 = &_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_72 = {cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_30_2 = &_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_73 = {cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_35_2 = &_cs_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_74 = {cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_9_2 = &_cs_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_84 = cs_decoder_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_75 = {cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_89_2 = &_cs_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_76 = {cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_57_2 = &_cs_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_77 = {cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_164_2 = &_cs_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_78 = {cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_121_2 = &_cs_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_79 = {cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_25_2 = &_cs_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_80 = {cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_99_2 = &_cs_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_81 = {cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_51_2 = &_cs_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_37_2 = &_cs_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_83 = {cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_143_2 = &_cs_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_84 = {cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_137_2 = &_cs_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_85 = {cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_118_2 = &_cs_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_86 = {cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_58_2 = &_cs_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_87 = {cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_146_2 = &_cs_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_88 = {cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_50_2 = &_cs_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_129_2 = &_cs_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_90 = {cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_66_2 = &_cs_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_91 = {cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_134_2 = &_cs_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_92 = {cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_97_2 = &_cs_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_93 = {cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_65_2 = &_cs_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_50 = cs_decoder_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_94 = {cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_16_2 = &_cs_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_95 = {cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_95_2 = &_cs_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_96 = {cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_82_2 = &_cs_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_3 = cs_decoder_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_97 = {cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_54_2 = &_cs_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_98 = {cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_7_2 = &_cs_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_99 = {cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_115_2 = &_cs_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_100 = {cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_92_2 = &_cs_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_101 = {cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_40_2 = &_cs_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_102 = {cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_63_2 = &_cs_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_103 = {cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_133_2 = &_cs_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_104 = {cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_28_2 = &_cs_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_105 = {cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_68_2 = &_cs_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_106 = {cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_11_2 = &_cs_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_107 = {cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_74_2 = &_cs_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_108 = {cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_139_2 = &_cs_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_109 = {cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_156_2 = &_cs_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_110 = {cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_38_2 = &_cs_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_111 = {cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_116_2 = &_cs_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_112 = {cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_4_2 = &_cs_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_113 = {cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_163_2 = &_cs_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_114 = {cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_5_2 = &_cs_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_115 = {cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_22_2 = &_cs_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_116 = {cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_48_2 = &_cs_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_117 = {cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_125_2 = &_cs_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_118 = {cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_24_2 = &_cs_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_119 = {cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_44_2 = &_cs_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_120 = {cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_119_2 = &_cs_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_121 = {cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_154_2 = &_cs_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_122 = {cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_151_2 = &_cs_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_123 = {cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_104_2 = &_cs_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_124 = {cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_20_2 = &_cs_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_125 = {cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_49_2 = &_cs_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_126 = {cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_122_2 = &_cs_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_127 = {cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_12_2 = &_cs_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_128 = {cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_41_2 = &_cs_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_129 = {cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_152_2 = &_cs_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_130 = {cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_23_2 = &_cs_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_131 = {cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_98_2 = &_cs_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_132 = {cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_15_2 = &_cs_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_133 = {cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_36_2 = &_cs_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_134 = {cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_46_2 = &_cs_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_135 = {cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_55_2 = &_cs_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_136 = {cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_159_2 = &_cs_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_137 = {cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_117_2 = &_cs_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_2 = cs_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_138 = {cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_109_2 = &_cs_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_139 = {cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_128_2 = &_cs_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_140 = {cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_2_2 = &_cs_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_141 = {cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_83_2 = &_cs_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_142 = {cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_87_2 = &_cs_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_143 = {cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_158_2 = &_cs_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_144 = {cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_19_2 = &_cs_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_145 = {cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_91_2 = &_cs_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_146 = {cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_70_2 = &_cs_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_147 = {cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_53_2 = &_cs_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_148 = {cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_126_2 = &_cs_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_149 = {cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_150_2 = &_cs_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_150 = {cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_31_2 = &_cs_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = cs_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_151 = {cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_106_2 = &_cs_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_152 = {cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_78_2 = &_cs_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_153 = {cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_64_2 = &_cs_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_154 = {cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_103_2 = &_cs_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_155 = {cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_147_2 = &_cs_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_156 = {cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_142_2 = &_cs_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_157 = {cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_130_2 = &_cs_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_158 = {cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_32_2 = &_cs_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_159 = {cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_94_2 = &_cs_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_160 = {cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_84_2 = &_cs_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_161 = {cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_101_2 = &_cs_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_162 = {cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_132_2 = &_cs_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_163 = {cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_90_2 = &_cs_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_164 = {cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_27_2 = &_cs_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_165 = {cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_148_2 = &_cs_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_166 = {cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_67_2 = &_cs_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_167 = {cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_34_2 = &_cs_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_168 = {cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_59_2 = &_cs_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo = {cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN = {cs_decoder_decoded_andMatrixOutputs_152_2, cs_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] _GEN_0 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = _GEN_0; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T = {cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_1 = |_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_1 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_1 = _GEN_1; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_27; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = _GEN_1; // @[pla.scala:114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_4 = {cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_5 = |_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_2 = {cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = _GEN_2; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = _GEN_3; // @[pla.scala:114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_6 = {cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_7 = |_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_4 = {cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_2 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_33; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_33 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_8 = {cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_9 = |_cs_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_5 = {cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_10 = _GEN_5; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = _GEN_5; // @[pla.scala:114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_91; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_91 = _GEN_5; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_11 = |_cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_6 = {cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = _GEN_6; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = _GEN_7; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_7; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_12 = {cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_13 = |_cs_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_67_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_109_2, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_148_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_14 = {cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_15 = |_cs_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_8 = {cs_decoder_decoded_andMatrixOutputs_115_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = _GEN_8; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_18 = {cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_19 = |_cs_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_20 = {cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_21 = |_cs_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_122_2, cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_143_2, cs_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_75_2, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [14:0] _cs_decoder_decoded_orMatrixOutputs_T_22 = {cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_23 = |_cs_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_49_2, cs_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_119_2, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_38_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_57_2, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_149_2, cs_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _cs_decoder_decoded_orMatrixOutputs_T_24 = {cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_25 = |_cs_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {cs_decoder_decoded_andMatrixOutputs_156_2, cs_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_6; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_127_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_113_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_26 = {cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_27 = |_cs_decoder_decoded_orMatrixOutputs_T_26; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_135_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_28 = {cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_29 = |_cs_decoder_decoded_orMatrixOutputs_T_28; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_150_2, cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_10 = {cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_87_2, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [13:0] _cs_decoder_decoded_orMatrixOutputs_T_30 = {cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_31 = |_cs_decoder_decoded_orMatrixOutputs_T_30; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_19_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_11 = {cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_108_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_12 = {cs_decoder_decoded_andMatrixOutputs_112_2, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [31:0] _cs_decoder_decoded_orMatrixOutputs_T_32 = {cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_33 = |_cs_decoder_decoded_orMatrixOutputs_T_32; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_36 = |_cs_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_11; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_26; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = _GEN_13; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_37 = {cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_38 = |_cs_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_14 = {cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_14; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = _GEN_14; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] _GEN_15 = {cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = _GEN_15; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_39 = {cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_40 = |_cs_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_129_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = _GEN_16; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = _GEN_16; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_41 = {cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_42 = |_cs_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_43 = {cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_44 = |_cs_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_45 = {cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_46 = |_cs_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_47 = {cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_48 = |_cs_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_17 = {cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_51 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_18 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_23; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = _GEN_17; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_52 = |_cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_53 = {cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_54 = |_cs_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_21; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_21 = _GEN_18; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_25; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = _GEN_18; // @[pla.scala:114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_55 = {cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_56 = |_cs_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_164_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_57 = {cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_58 = |_cs_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_19 = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_19; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_20 = {cs_decoder_decoded_andMatrixOutputs_158_2, cs_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = _GEN_23; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = _GEN_23; // @[pla.scala:114:19] wire [1:0] _GEN_24 = {cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_129_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = _GEN_24; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = _GEN_25; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_26 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_77_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = _GEN_26; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {cs_decoder_decoded_andMatrixOutputs_81_2, cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [27:0] _cs_decoder_decoded_orMatrixOutputs_T_59 = {cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_60 = |_cs_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_71_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [28:0] _cs_decoder_decoded_orMatrixOutputs_T_61 = {cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_62 = |_cs_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_28 = {cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_16; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_64 = {cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_65 = |_cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_32_2, cs_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] _GEN_29 = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_104_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = _GEN_30; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = _GEN_30; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_30; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_66 = {cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_67 = |_cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_68 = {cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_69 = |_cs_decoder_decoded_orMatrixOutputs_T_68; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_3_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_72_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_70 = {cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_71 = |_cs_decoder_decoded_orMatrixOutputs_T_70; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = _GEN_31; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = _GEN_31; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = _GEN_31; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_72 = {cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_27}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_73 = |_cs_decoder_decoded_orMatrixOutputs_T_72; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_32 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = _GEN_32; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = _GEN_32; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = _GEN_33; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_33; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = _GEN_34; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_34; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [23:0] cs_decoder_decoded_orMatrixOutputs_lo_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] _GEN_35 = {cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = _GEN_35; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1 = _GEN_35; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_36 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_36; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_36; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_37 = {cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_37; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_37; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [24:0] cs_decoder_decoded_orMatrixOutputs_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [48:0] _cs_decoder_decoded_orMatrixOutputs_T_74 = {cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_28}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_75 = |_cs_decoder_decoded_orMatrixOutputs_T_74; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_128_2, cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_38 = {cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_38; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_38; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_lo_29 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_39 = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = _GEN_39; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_39; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_14_2, cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_77_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [30:0] _cs_decoder_decoded_orMatrixOutputs_T_76 = {cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_29}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_77 = |_cs_decoder_decoded_orMatrixOutputs_T_76; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_30 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_32 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_78 = {cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_30}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_79 = |_cs_decoder_decoded_orMatrixOutputs_T_78; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_80 = {cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_81 = |_cs_decoder_decoded_orMatrixOutputs_T_80; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_141_2, cs_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_83 = |_cs_decoder_decoded_orMatrixOutputs_T_82; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_31 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_34 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_85 = {cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_31}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_86 = |_cs_decoder_decoded_orMatrixOutputs_T_85; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_32 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_161_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_35 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_87 = {cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_32}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_88 = |_cs_decoder_decoded_orMatrixOutputs_T_87; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_90 = |_cs_decoder_decoded_orMatrixOutputs_T_89; // @[pla.scala:114:{19,36}] wire _cs_decoder_decoded_orMatrixOutputs_T_92 = |_cs_decoder_decoded_orMatrixOutputs_T_91; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_36 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_93 = {cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_33}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_94 = |_cs_decoder_decoded_orMatrixOutputs_T_93; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_34 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_37 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_23}; // @[pla.scala:114:19] wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_95 = {cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_34}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_96 = |_cs_decoder_decoded_orMatrixOutputs_T_95; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_133_2, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [27:0] cs_decoder_decoded_orMatrixOutputs_lo_35 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_21}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [28:0] cs_decoder_decoded_orMatrixOutputs_hi_38 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_24}; // @[pla.scala:114:19] wire [56:0] _cs_decoder_decoded_orMatrixOutputs_T_97 = {cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_35}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_98 = |_cs_decoder_decoded_orMatrixOutputs_T_97; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_7, _cs_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_11, _cs_decoder_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_16, _cs_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_17, 1'h0}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_21, _cs_decoder_decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_23, 1'h0}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2, 1'h0}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_27, _cs_decoder_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_31, _cs_decoder_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_33}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_40, _cs_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_44, _cs_decoder_decoded_orMatrixOutputs_T_42}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:102:36] wire [27:0] cs_decoder_decoded_orMatrixOutputs_lo_36 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_22}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_49, _cs_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_52, _cs_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_56, _cs_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_62, _cs_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_65, _cs_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_69, _cs_decoder_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_75, _cs_decoder_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_79, _cs_decoder_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_83, _cs_decoder_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_86, _cs_decoder_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_90, _cs_decoder_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2 = {_cs_decoder_decoded_orMatrixOutputs_T_94, _cs_decoder_decoded_orMatrixOutputs_T_92}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = {_cs_decoder_decoded_orMatrixOutputs_T_98, _cs_decoder_decoded_orMatrixOutputs_T_96}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2}; // @[pla.scala:102:36] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:102:36] wire [28:0] cs_decoder_decoded_orMatrixOutputs_hi_39 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_31, cs_decoder_decoded_orMatrixOutputs_hi_lo_25}; // @[pla.scala:102:36] wire [56:0] cs_decoder_decoded_orMatrixOutputs = {cs_decoder_decoded_orMatrixOutputs_hi_39, cs_decoder_decoded_orMatrixOutputs_lo_36}; // @[pla.scala:102:36] wire _cs_decoder_decoded_invMatrixOutputs_T = cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_1 = cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_2 = cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_3 = cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_4 = cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_5 = cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_6 = cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_7 = cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_8 = cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_9 = cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_10 = cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_11 = cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_12 = cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_13 = cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_14 = cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_15 = cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_16 = cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_17 = cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_18 = cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_19 = cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_20 = cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_21 = cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_22 = cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_23 = cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_24 = cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_25 = cs_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_26 = cs_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_27 = cs_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_28 = cs_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_29 = cs_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_30 = cs_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_31 = cs_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_32 = cs_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_33 = cs_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_34 = cs_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_35 = cs_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_36 = cs_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_37 = ~_cs_decoder_decoded_invMatrixOutputs_T_36; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_38 = cs_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_39 = ~_cs_decoder_decoded_invMatrixOutputs_T_38; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_40 = cs_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_41 = cs_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_42 = cs_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_43 = cs_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_44 = cs_decoder_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_45 = cs_decoder_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_46 = cs_decoder_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_47 = ~_cs_decoder_decoded_invMatrixOutputs_T_46; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_48 = cs_decoder_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_49 = cs_decoder_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_50 = cs_decoder_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_51 = cs_decoder_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_52 = cs_decoder_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_53 = cs_decoder_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_54 = cs_decoder_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_55 = cs_decoder_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_56 = cs_decoder_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_57 = cs_decoder_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_58 = cs_decoder_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_59 = cs_decoder_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_4, _cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_6, _cs_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_9, _cs_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_11, _cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_13, _cs_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_16, _cs_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_20, _cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_27, _cs_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [27:0] cs_decoder_decoded_invMatrixOutputs_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_30, _cs_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_34, _cs_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :123:40] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_41, _cs_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_45}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_49, _cs_decoder_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_51, _cs_decoder_decoded_invMatrixOutputs_T_50}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {_cs_decoder_decoded_invMatrixOutputs_T_53, _cs_decoder_decoded_invMatrixOutputs_T_52}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_55, _cs_decoder_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_57, _cs_decoder_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_59, _cs_decoder_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [7:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [14:0] cs_decoder_decoded_invMatrixOutputs_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [28:0] cs_decoder_decoded_invMatrixOutputs_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded_invMatrixOutputs = {cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded = cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign cs_decoder_0 = cs_decoder_decoded[56]; // @[pla.scala:81:23] assign cs_legal = cs_decoder_0; // @[Decode.scala:50:77] assign cs_decoder_1 = cs_decoder_decoded[55]; // @[pla.scala:81:23] assign cs_fp_val = cs_decoder_1; // @[Decode.scala:50:77] assign cs_decoder_2 = cs_decoder_decoded[54:45]; // @[pla.scala:81:23] assign cs_fu_code = cs_decoder_2; // @[Decode.scala:50:77] assign cs_decoder_3 = cs_decoder_decoded[44:43]; // @[pla.scala:81:23] assign cs_dst_type = cs_decoder_3; // @[Decode.scala:50:77] assign cs_decoder_4 = cs_decoder_decoded[42:41]; // @[pla.scala:81:23] assign cs_rs1_type = cs_decoder_4; // @[Decode.scala:50:77] assign cs_decoder_5 = cs_decoder_decoded[40:39]; // @[pla.scala:81:23] assign cs_rs2_type = cs_decoder_5; // @[Decode.scala:50:77] assign cs_decoder_6 = cs_decoder_decoded[38]; // @[pla.scala:81:23] assign cs_frs3_en = cs_decoder_6; // @[Decode.scala:50:77] assign cs_decoder_7 = cs_decoder_decoded[37:35]; // @[pla.scala:81:23] assign cs_imm_sel = cs_decoder_7; // @[Decode.scala:50:77] assign cs_decoder_8 = cs_decoder_decoded[34]; // @[pla.scala:81:23] assign cs_uses_ldq = cs_decoder_8; // @[Decode.scala:50:77] assign cs_decoder_9 = cs_decoder_decoded[33]; // @[pla.scala:81:23] assign cs_uses_stq = cs_decoder_9; // @[Decode.scala:50:77] assign cs_decoder_10 = cs_decoder_decoded[32]; // @[pla.scala:81:23] assign cs_is_amo = cs_decoder_10; // @[Decode.scala:50:77] assign cs_decoder_11 = cs_decoder_decoded[31:27]; // @[pla.scala:81:23] assign cs_mem_cmd = cs_decoder_11; // @[Decode.scala:50:77] assign cs_decoder_12 = cs_decoder_decoded[26]; // @[pla.scala:81:23] assign cs_inst_unique = cs_decoder_12; // @[Decode.scala:50:77] assign cs_decoder_13 = cs_decoder_decoded[25]; // @[pla.scala:81:23] assign cs_flush_on_commit = cs_decoder_13; // @[Decode.scala:50:77] assign cs_decoder_14 = cs_decoder_decoded[24:22]; // @[pla.scala:81:23] assign cs_csr_cmd = cs_decoder_14; // @[Decode.scala:50:77] assign cs_decoder_15 = cs_decoder_decoded[21]; // @[pla.scala:81:23] assign cs_fcn_dw = cs_decoder_15; // @[Decode.scala:50:77] assign cs_decoder_16 = cs_decoder_decoded[20:16]; // @[pla.scala:81:23] assign cs_fcn_op = cs_decoder_16; // @[Decode.scala:50:77] assign cs_decoder_17 = cs_decoder_decoded[15]; // @[pla.scala:81:23] assign cs_fp_ldst = cs_decoder_17; // @[Decode.scala:50:77] assign cs_decoder_18 = cs_decoder_decoded[14]; // @[pla.scala:81:23] assign cs_fp_wen = cs_decoder_18; // @[Decode.scala:50:77] assign cs_decoder_19 = cs_decoder_decoded[13]; // @[pla.scala:81:23] assign cs_fp_ren1 = cs_decoder_19; // @[Decode.scala:50:77] assign cs_decoder_20 = cs_decoder_decoded[12]; // @[pla.scala:81:23] assign cs_fp_ren2 = cs_decoder_20; // @[Decode.scala:50:77] assign cs_decoder_21 = cs_decoder_decoded[11]; // @[pla.scala:81:23] assign cs_fp_ren3 = cs_decoder_21; // @[Decode.scala:50:77] assign cs_decoder_22 = cs_decoder_decoded[10]; // @[pla.scala:81:23] assign cs_fp_swap12 = cs_decoder_22; // @[Decode.scala:50:77] assign cs_decoder_23 = cs_decoder_decoded[9]; // @[pla.scala:81:23] assign cs_fp_swap23 = cs_decoder_23; // @[Decode.scala:50:77] wire cs_decoder_24 = cs_decoder_decoded[8]; // @[pla.scala:81:23] wire cs_decoder_25 = cs_decoder_decoded[7]; // @[pla.scala:81:23] assign cs_decoder_26 = cs_decoder_decoded[6]; // @[pla.scala:81:23] assign cs_fp_fromint = cs_decoder_26; // @[Decode.scala:50:77] assign cs_decoder_27 = cs_decoder_decoded[5]; // @[pla.scala:81:23] assign cs_fp_toint = cs_decoder_27; // @[Decode.scala:50:77] assign cs_decoder_28 = cs_decoder_decoded[4]; // @[pla.scala:81:23] assign cs_fp_fastpipe = cs_decoder_28; // @[Decode.scala:50:77] assign cs_decoder_29 = cs_decoder_decoded[3]; // @[pla.scala:81:23] assign cs_fp_fma = cs_decoder_29; // @[Decode.scala:50:77] assign cs_decoder_30 = cs_decoder_decoded[2]; // @[pla.scala:81:23] assign cs_fp_div = cs_decoder_30; // @[Decode.scala:50:77] assign cs_decoder_31 = cs_decoder_decoded[1]; // @[pla.scala:81:23] assign cs_fp_sqrt = cs_decoder_31; // @[Decode.scala:50:77] assign cs_decoder_32 = cs_decoder_decoded[0]; // @[pla.scala:81:23] assign cs_fp_wflags = cs_decoder_32; // @[Decode.scala:50:77] assign cs_fp_typeTagIn = {1'h0, cs_decoder_24}; // @[Decode.scala:50:77] assign cs_fp_typeTagOut = {1'h0, cs_decoder_25}; // @[Decode.scala:50:77] wire _T_29 = cs_csr_cmd == 3'h6; // @[package.scala:16:47] wire _csr_en_T; // @[package.scala:16:47] assign _csr_en_T = _T_29; // @[package.scala:16:47] wire _csr_ren_T; // @[package.scala:16:47] assign _csr_ren_T = _T_29; // @[package.scala:16:47] wire _csr_en_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_en_T_2 = cs_csr_cmd == 3'h5; // @[package.scala:16:47] wire _csr_en_T_3 = _csr_en_T | _csr_en_T_1; // @[package.scala:16:47, :81:59] wire csr_en = _csr_en_T_3 | _csr_en_T_2; // @[package.scala:16:47, :81:59] wire _csr_ren_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _csr_ren_T_3 = uop_lrs1 == 6'h0; // @[decode.scala:422:7, :426:14, :428:17, :452:62] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[package.scala:81:59] wire system_insn = cs_csr_cmd == 3'h4; // @[decode.scala:447:16, :453:32] wire [31:0] _GEN_40 = uop_inst & 32'hFE007FFF; // @[decode.scala:428:17, :454:21] wire [31:0] _sfence_T; // @[decode.scala:454:21] assign _sfence_T = _GEN_40; // @[decode.scala:454:21] wire [31:0] _uop_is_sfence_T; // @[decode.scala:528:26] assign _uop_is_sfence_T = _GEN_40; // @[decode.scala:454:21, :528:26] wire sfence = _sfence_T == 32'h12000073; // @[decode.scala:454:21] wire [2:0] _illegal_rm_T = uop_inst[14:12]; // @[decode.scala:428:17, :460:24] wire [2:0] _illegal_rm_T_4 = uop_inst[14:12]; // @[decode.scala:428:17, :460:{24,57}] wire [2:0] _uop_is_rocc_T_6 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :532:88] wire [2:0] _uop_pimm_T_1 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :553:47] wire [2:0] _uop_fp_rm_T = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :556:26] wire [2:0] _uop_fp_rm_T_2 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :556:59] wire _illegal_rm_T_1 = _illegal_rm_T == 3'h5; // @[package.scala:16:47] wire _illegal_rm_T_2 = _illegal_rm_T == 3'h6; // @[package.scala:16:47] wire _illegal_rm_T_3 = _illegal_rm_T_1 | _illegal_rm_T_2; // @[package.scala:16:47, :81:59] wire _illegal_rm_T_5 = &_illegal_rm_T_4; // @[decode.scala:460:{57,65}] wire _illegal_rm_T_6 = io_fcsr_rm_0 > 3'h4; // @[decode.scala:422:7, :460:87] wire _illegal_rm_T_7 = _illegal_rm_T_5 & _illegal_rm_T_6; // @[decode.scala:460:{65,73,87}] wire illegal_rm = _illegal_rm_T_3 | _illegal_rm_T_7; // @[package.scala:81:59] wire _id_illegal_insn_T = ~cs_legal; // @[decode.scala:447:16, :461:26] wire _id_illegal_insn_T_1 = io_csr_decode_fp_illegal_0 | illegal_rm; // @[decode.scala:422:7, :460:49, :462:45] wire _id_illegal_insn_T_2 = cs_fp_val & _id_illegal_insn_T_1; // @[decode.scala:447:16, :462:{16,45}] wire _id_illegal_insn_T_3 = _id_illegal_insn_T | _id_illegal_insn_T_2; // @[decode.scala:461:{26,36}, :462:16] wire _id_illegal_insn_T_5 = _id_illegal_insn_T_3 | _id_illegal_insn_T_4; // @[decode.scala:461:36, :462:61, :463:18] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5; // @[decode.scala:462:61, :463:49] wire _id_illegal_insn_T_10 = ~csr_ren; // @[decode.scala:452:50, :465:47] wire _id_illegal_insn_T_11 = _id_illegal_insn_T_10 & io_csr_decode_write_illegal_0; // @[decode.scala:422:7, :465:{47,56}] wire _id_illegal_insn_T_12 = io_csr_decode_read_illegal_0 | _id_illegal_insn_T_11; // @[decode.scala:422:7, :465:{44,56}] wire _id_illegal_insn_T_13 = csr_en & _id_illegal_insn_T_12; // @[package.scala:81:59] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 | _id_illegal_insn_T_13; // @[decode.scala:463:49, :464:45, :465:13] wire _id_illegal_insn_T_15 = sfence | system_insn; // @[decode.scala:453:32, :454:21, :466:14] wire _id_illegal_insn_T_16 = _id_illegal_insn_T_15 & io_csr_decode_system_illegal_0; // @[decode.scala:422:7, :466:{14,30}] wire id_illegal_insn = _id_illegal_insn_T_14 | _id_illegal_insn_T_16; // @[decode.scala:464:45, :465:89, :466:30] wire _T_1 = io_interrupt_0 & ~io_enq_uop_is_sfb_0; // @[decode.scala:422:7, :473:{19,22}] assign xcpt_valid = _T_1 | uop_bp_debug_if | uop_bp_xcpt_if | uop_xcpt_pf_if | uop_xcpt_ae_if | id_illegal_insn; // @[decode.scala:428:17, :465:89, :470:26, :473:19] assign uop_exception = xcpt_valid; // @[decode.scala:428:17, :470:26] assign xcpt_cause = _T_1 ? io_interrupt_cause_0 : {60'h0, uop_bp_debug_if ? 4'hE : uop_bp_xcpt_if ? 4'h3 : uop_xcpt_pf_if ? 4'hC : {2'h0, uop_xcpt_ae_if ? 2'h1 : 2'h2}}; // @[Mux.scala:50:70] assign uop_exc_cause = xcpt_cause; // @[Mux.scala:50:70] wire [31:0] _uop_is_mov_T = uop_inst & 32'hFE00707F; // @[decode.scala:428:17, :485:26] wire _uop_is_mov_T_1 = _uop_is_mov_T == 32'h33; // @[decode.scala:485:26] wire _uop_is_mov_T_2 = ~(|LRS1); // @[decode.scala:442:18, :485:42] assign _uop_is_mov_T_3 = _uop_is_mov_T_1 & _uop_is_mov_T_2; // @[decode.scala:485:{26,34,42}] assign uop_is_mov = _uop_is_mov_T_3; // @[decode.scala:428:17, :485:34] assign uop_fu_code_3 = cs_fu_code[3]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T = cs_fu_code[3]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_4 = cs_fu_code[4]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_1 = cs_fu_code[4]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_5 = cs_fu_code[5]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_2 = cs_fu_code[5]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_8 = cs_fu_code[8]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_3 = cs_fu_code[8]; // @[decode.scala:447:16, :487:84] wire _uop_iq_type_1_T_4 = _uop_iq_type_1_T | _uop_iq_type_1_T_1; // @[decode.scala:487:{84,98}] wire _uop_iq_type_1_T_5 = _uop_iq_type_1_T_4 | _uop_iq_type_1_T_2; // @[decode.scala:487:{84,98}] assign _uop_iq_type_1_T_6 = _uop_iq_type_1_T_5 | _uop_iq_type_1_T_3; // @[decode.scala:487:{84,98}] assign uop_iq_type_1 = _uop_iq_type_1_T_6; // @[decode.scala:428:17, :487:98] assign uop_fu_code_0 = cs_fu_code[0]; // @[decode.scala:428:17, :447:16, :488:84] assign _uop_iq_type_2_T = cs_fu_code[0]; // @[decode.scala:447:16, :488:84] assign uop_iq_type_2 = _uop_iq_type_2_T; // @[decode.scala:428:17, :488:84] assign uop_fu_code_1 = cs_fu_code[1]; // @[decode.scala:428:17, :447:16, :489:84] wire _uop_iq_type_0_T = cs_fu_code[1]; // @[decode.scala:447:16, :489:84] assign uop_fu_code_2 = cs_fu_code[2]; // @[decode.scala:428:17, :447:16, :489:84] wire _uop_iq_type_0_T_1 = cs_fu_code[2]; // @[decode.scala:447:16, :489:84] assign _uop_iq_type_0_T_2 = _uop_iq_type_0_T | _uop_iq_type_0_T_1; // @[decode.scala:489:{84,98}] assign uop_iq_type_0 = _uop_iq_type_0_T_2; // @[decode.scala:428:17, :489:98] assign uop_fu_code_6 = cs_fu_code[6]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T = cs_fu_code[6]; // @[decode.scala:447:16, :490:84] assign uop_fu_code_7 = cs_fu_code[7]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T_1 = cs_fu_code[7]; // @[decode.scala:447:16, :490:84] assign uop_fu_code_9 = cs_fu_code[9]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T_2 = cs_fu_code[9]; // @[decode.scala:447:16, :490:84] wire _uop_iq_type_3_T_3 = _uop_iq_type_3_T | _uop_iq_type_3_T_1; // @[decode.scala:490:{84,98}] assign _uop_iq_type_3_T_4 = _uop_iq_type_3_T_3 | _uop_iq_type_3_T_2; // @[decode.scala:490:{84,98}] assign uop_iq_type_3 = _uop_iq_type_3_T_4; // @[decode.scala:428:17, :490:98] assign uop_ldst = {1'h0, LDST}; // @[decode.scala:428:17, :441:18, :494:18] assign uop_lrs3 = {1'h0, LRS3}; // @[decode.scala:428:17, :444:18, :497:18] wire _uop_lrs1_rtype_T = cs_rs1_type == 2'h0; // @[decode.scala:447:16, :500:37] wire _uop_lrs1_rtype_T_1 = ~(|LRS1); // @[decode.scala:442:18, :485:42, :500:56] wire _uop_lrs1_rtype_T_2 = _uop_lrs1_rtype_T & _uop_lrs1_rtype_T_1; // @[decode.scala:500:{37,48,56}] wire [1:0] _uop_lrs1_rtype_T_3 = _uop_lrs1_rtype_T_2 ? 2'h3 : cs_rs1_type; // @[decode.scala:447:16, :500:{24,48}] wire _uop_lrs2_rtype_T = cs_rs2_type == 2'h0; // @[decode.scala:447:16, :501:37] wire _uop_lrs2_rtype_T_1 = ~(|LRS2); // @[decode.scala:443:18, :501:56] wire _uop_lrs2_rtype_T_2 = _uop_lrs2_rtype_T & _uop_lrs2_rtype_T_1; // @[decode.scala:501:{37,48,56}] wire [1:0] _uop_lrs2_rtype_T_3 = _uop_lrs2_rtype_T_2 ? 2'h3 : cs_rs2_type; // @[decode.scala:447:16, :501:{24,48}] wire _uop_ldst_is_rs1_T = uop_br_type == 4'h0; // @[decode.scala:428:17] wire _uop_ldst_is_rs1_T_1 = _uop_ldst_is_rs1_T & uop_is_sfb; // @[decode.scala:428:17] wire _uop_ldst_is_rs1_T_2 = _uop_ldst_is_rs1_T_1; // @[micro-op.scala:121:{42,52}] wire _T_24 = _uop_ldst_is_rs1_T & uop_is_sfb & cs_rs2_type == 2'h2; // @[decode.scala:428:17, :447:16, :506:{27,42}] wire _GEN_41 = LDST == 5'h0; // @[decode.scala:422:7, :426:14, :428:17, :441:18, :507:33] wire _uop_lrs2_rtype_T_4; // @[decode.scala:507:33] assign _uop_lrs2_rtype_T_4 = _GEN_41; // @[decode.scala:507:33] wire _uop_lrs1_rtype_T_4; // @[decode.scala:512:33] assign _uop_lrs1_rtype_T_4 = _GEN_41; // @[decode.scala:507:33, :512:33] wire [1:0] _uop_lrs2_rtype_T_5 = {2{_uop_lrs2_rtype_T_4}}; // @[decode.scala:507:{27,33}] assign uop_lrs2_rtype = _T_24 ? _uop_lrs2_rtype_T_5 : _uop_lrs2_rtype_T_3; // @[decode.scala:428:17, :501:{18,24}, :506:{27,52}, :507:{21,27}] assign uop_lrs2 = {1'h0, _T_24 ? LDST : LRS2}; // @[decode.scala:428:17, :441:18, :443:18, :496:18, :506:{27,52}, :508:21] wire _T_28 = _uop_ldst_is_rs1_T & uop_is_sfb & uop_is_mov; // @[decode.scala:428:17, :510:34] wire _GEN_42 = _T_24 | ~_T_28; // @[decode.scala:495:18, :506:{27,52}, :510:{34,49}] assign uop_lrs1 = {1'h0, _GEN_42 ? LRS1 : LDST}; // @[decode.scala:428:17, :441:18, :442:18, :495:18, :506:52, :510:49] wire [1:0] _uop_lrs1_rtype_T_5 = {2{_uop_lrs1_rtype_T_4}}; // @[decode.scala:512:{27,33}] assign uop_lrs1_rtype = _GEN_42 ? _uop_lrs1_rtype_T_3 : _uop_lrs1_rtype_T_5; // @[decode.scala:428:17, :495:18, :500:{18,24}, :506:52, :510:49, :512:27] assign uop_ldst_is_rs1 = ~_T_24 & (_T_28 | _uop_ldst_is_rs1_T_2); // @[decode.scala:428:17, :504:19, :506:{27,52}, :509:21, :510:{34,49}, :513:21] wire _uop_mem_size_T = cs_mem_cmd == 5'h14; // @[package.scala:16:47] wire _uop_mem_size_T_1 = cs_mem_cmd == 5'h5; // @[package.scala:16:47] wire _uop_mem_size_T_2 = _uop_mem_size_T | _uop_mem_size_T_1; // @[package.scala:16:47, :81:59] wire _uop_mem_size_T_3 = |LRS2; // @[decode.scala:443:18, :501:56, :521:77] wire _uop_mem_size_T_4 = |LRS1; // @[decode.scala:442:18, :485:42, :521:91] wire [1:0] _uop_mem_size_T_5 = {_uop_mem_size_T_3, _uop_mem_size_T_4}; // @[decode.scala:521:{71,77,91}] wire [1:0] _uop_mem_size_T_6 = uop_inst[13:12]; // @[decode.scala:428:17, :521:105] assign _uop_mem_size_T_7 = _uop_mem_size_T_2 ? _uop_mem_size_T_5 : _uop_mem_size_T_6; // @[package.scala:81:59] assign uop_mem_size = _uop_mem_size_T_7; // @[decode.scala:428:17, :521:24] wire _uop_mem_signed_T = uop_inst[14]; // @[decode.scala:428:17, :522:26] assign _uop_mem_signed_T_1 = ~_uop_mem_signed_T; // @[decode.scala:522:{21,26}] assign uop_mem_signed = _uop_mem_signed_T_1; // @[decode.scala:428:17, :522:21] wire [31:0] _GEN_43 = {17'h0, uop_inst[14:0] & 15'h707F}; // @[decode.scala:428:17, :526:26] wire [31:0] _uop_is_fence_T; // @[decode.scala:526:26] assign _uop_is_fence_T = _GEN_43; // @[decode.scala:526:26] wire [31:0] _uop_is_fencei_T; // @[decode.scala:527:26] assign _uop_is_fencei_T = _GEN_43; // @[decode.scala:526:26, :527:26] wire [31:0] _uop_br_type_T; // @[decode.scala:604:36] assign _uop_br_type_T = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_3; // @[decode.scala:604:36] assign _uop_br_type_T_3 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_6; // @[decode.scala:604:36] assign _uop_br_type_T_6 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_9; // @[decode.scala:604:36] assign _uop_br_type_T_9 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_12; // @[decode.scala:604:36] assign _uop_br_type_T_12 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_15; // @[decode.scala:604:36] assign _uop_br_type_T_15 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_21; // @[decode.scala:604:36] assign _uop_br_type_T_21 = _GEN_43; // @[decode.scala:526:26, :604:36] assign _uop_is_fence_T_1 = _uop_is_fence_T == 32'hF; // @[decode.scala:526:26] assign uop_is_fence = _uop_is_fence_T_1; // @[decode.scala:428:17, :526:26] assign _uop_is_fencei_T_1 = _uop_is_fencei_T == 32'h100F; // @[decode.scala:527:26] assign uop_is_fencei = _uop_is_fencei_T_1; // @[decode.scala:428:17, :527:26] assign _uop_is_sfence_T_1 = _uop_is_sfence_T == 32'h12000073; // @[decode.scala:528:26] assign uop_is_sfence = _uop_is_sfence_T_1; // @[decode.scala:428:17, :528:26] wire _uop_is_sys_pc2epc_T_1 = _uop_is_sys_pc2epc_T == 32'h100073; // @[decode.scala:529:29] wire _uop_is_sys_pc2epc_T_3 = _uop_is_sys_pc2epc_T_2 == 32'h73; // @[decode.scala:529:48] assign _uop_is_sys_pc2epc_T_4 = _uop_is_sys_pc2epc_T_1 | _uop_is_sys_pc2epc_T_3; // @[decode.scala:529:{29,40,48}] assign uop_is_sys_pc2epc = _uop_is_sys_pc2epc_T_4; // @[decode.scala:428:17, :529:40] wire _uop_is_eret_T_1 = _uop_is_eret_T == 32'h73; // @[decode.scala:530:26] wire _uop_is_eret_T_3 = _uop_is_eret_T_2 == 32'h100073; // @[decode.scala:530:44] wire _uop_is_eret_T_4 = _uop_is_eret_T_1 | _uop_is_eret_T_3; // @[decode.scala:530:{26,36,44}] wire _uop_is_eret_T_6 = _uop_is_eret_T_5 == 32'h10200073; // @[decode.scala:530:63] wire _uop_is_eret_T_7 = _uop_is_eret_T_4 | _uop_is_eret_T_6; // @[decode.scala:530:{36,55,63}] wire _uop_is_eret_T_9 = _uop_is_eret_T_8 == 32'h30200073; // @[decode.scala:530:80] wire _uop_is_eret_T_10 = _uop_is_eret_T_7 | _uop_is_eret_T_9; // @[decode.scala:530:{55,72,80}] wire _uop_is_eret_T_12 = _uop_is_eret_T_11 == 32'h7B200073; // @[decode.scala:530:97] assign _uop_is_eret_T_13 = _uop_is_eret_T_10 | _uop_is_eret_T_12; // @[decode.scala:530:{72,89,97}] assign uop_is_eret = _uop_is_eret_T_13; // @[decode.scala:428:17, :530:89] wire [6:0] _uop_is_rocc_T = uop_inst[6:0]; // @[decode.scala:428:17, :532:25] wire _uop_is_rocc_T_1 = _uop_is_rocc_T == 7'hB; // @[package.scala:16:47] wire _uop_is_rocc_T_2 = _uop_is_rocc_T == 7'h2B; // @[package.scala:16:47] wire _uop_is_rocc_T_3 = _uop_is_rocc_T == 7'h7B; // @[package.scala:16:47] wire _uop_is_rocc_T_4 = _uop_is_rocc_T_1 | _uop_is_rocc_T_2; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_5 = _uop_is_rocc_T_4 | _uop_is_rocc_T_3; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_7 = _uop_is_rocc_T_6 == 3'h0; // @[package.scala:16:47] wire _uop_is_rocc_T_8 = _uop_is_rocc_T_6 == 3'h2; // @[package.scala:16:47] wire _uop_is_rocc_T_9 = _uop_is_rocc_T_6 == 3'h3; // @[package.scala:16:47] wire _uop_is_rocc_T_10 = _uop_is_rocc_T_6 == 3'h4; // @[package.scala:16:47] wire _uop_is_rocc_T_11 = _uop_is_rocc_T_6 == 3'h6; // @[package.scala:16:47] wire _uop_is_rocc_T_12 = &_uop_is_rocc_T_6; // @[package.scala:16:47] wire _uop_is_rocc_T_13 = _uop_is_rocc_T_7 | _uop_is_rocc_T_8; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_14 = _uop_is_rocc_T_13 | _uop_is_rocc_T_9; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_15 = _uop_is_rocc_T_14 | _uop_is_rocc_T_10; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_16 = _uop_is_rocc_T_15 | _uop_is_rocc_T_11; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_17 = _uop_is_rocc_T_16 | _uop_is_rocc_T_12; // @[package.scala:16:47, :81:59] assign _uop_is_rocc_T_18 = _uop_is_rocc_T_5 & _uop_is_rocc_T_17; // @[package.scala:81:59] assign uop_is_rocc = _uop_is_rocc_T_18; // @[decode.scala:428:17, :532:81] wire _uop_flush_on_commit_T = ~csr_ren; // @[decode.scala:452:50, :465:47, :533:59] wire _uop_flush_on_commit_T_1 = csr_en & _uop_flush_on_commit_T; // @[package.scala:81:59] wire _uop_flush_on_commit_T_2 = _uop_flush_on_commit_T_1 & io_csr_decode_write_flush_0; // @[decode.scala:422:7, :533:{56,68}] assign _uop_flush_on_commit_T_3 = cs_flush_on_commit | _uop_flush_on_commit_T_2; // @[decode.scala:447:16, :533:{45,68}] assign uop_flush_on_commit = _uop_flush_on_commit_T_3; // @[decode.scala:428:17, :533:45] wire _GEN_44 = cs_imm_sel == 3'h2; // @[package.scala:16:47] wire _di24_20_T; // @[decode.scala:540:32] assign _di24_20_T = _GEN_44; // @[decode.scala:540:32] wire _imm_i11_T_2; // @[util.scala:288:44] assign _imm_i11_T_2 = _GEN_44; // @[util.scala:288:44] wire _T_142 = cs_imm_sel == 3'h1; // @[decode.scala:447:16, :540:55] wire _di24_20_T_1; // @[decode.scala:540:55] assign _di24_20_T_1 = _T_142; // @[decode.scala:540:55] wire _imm_i0_T; // @[util.scala:291:27] assign _imm_i0_T = _T_142; // @[util.scala:291:27] wire _di24_20_T_2 = _di24_20_T | _di24_20_T_1; // @[decode.scala:540:{32,41,55}] wire [4:0] di24_20 = _di24_20_T_2 ? _di24_20_T_3 : _di24_20_T_4; // @[decode.scala:540:{20,41,69,81}] wire [6:0] _imm_packed_T = uop_inst[31:25]; // @[decode.scala:428:17, :541:28] wire [7:0] _imm_packed_T_1 = uop_inst[19:12]; // @[decode.scala:428:17, :541:50] wire [11:0] imm_packed_hi = {_imm_packed_T, di24_20}; // @[decode.scala:540:20, :541:{23,28}] assign imm_packed = {imm_packed_hi, _imm_packed_T_1}; // @[decode.scala:541:{23,50}] assign uop_imm_packed = imm_packed; // @[decode.scala:428:17, :541:23] wire _imm_ip_T = cs_imm_sel == 3'h6; // @[util.scala:282:23] wire [19:0] imm_ip = _imm_ip_T ? 20'h0 : imm_packed; // @[util.scala:282:{17,23}] wire _imm_sign_T = imm_ip[19]; // @[util.scala:282:17, :284:18] wire imm_sign = _imm_sign_T; // @[util.scala:284:{18,37}] wire imm_hi_hi_hi = imm_sign; // @[util.scala:284:37, :294:15] wire _T_139 = cs_imm_sel == 3'h3; // @[package.scala:16:47] wire _imm_i30_20_T; // @[util.scala:285:27] assign _imm_i30_20_T = _T_139; // @[util.scala:285:27] wire _imm_i19_12_T; // @[util.scala:286:27] assign _imm_i19_12_T = _T_139; // @[util.scala:285:27, :286:27] wire _imm_i11_T; // @[util.scala:287:27] assign _imm_i11_T = _T_139; // @[util.scala:285:27, :287:27] wire _imm_i10_5_T; // @[util.scala:289:27] assign _imm_i10_5_T = _T_139; // @[util.scala:285:27, :289:27] wire _imm_i4_1_T; // @[util.scala:290:27] assign _imm_i4_1_T = _T_139; // @[util.scala:285:27, :290:27] wire [10:0] _imm_i30_20_T_1 = imm_ip[18:8]; // @[util.scala:282:17, :285:39] wire [10:0] _imm_i30_20_T_2 = _imm_i30_20_T_1; // @[util.scala:285:{39,46}] wire [10:0] imm_i30_20 = _imm_i30_20_T ? _imm_i30_20_T_2 : {11{imm_sign}}; // @[util.scala:284:37, :285:{21,27,46}] wire [10:0] imm_hi_hi_lo = imm_i30_20; // @[util.scala:285:21, :294:15] wire _GEN_45 = cs_imm_sel == 3'h4; // @[util.scala:286:44] wire _imm_i19_12_T_1; // @[util.scala:286:44] assign _imm_i19_12_T_1 = _GEN_45; // @[util.scala:286:44] wire _imm_i11_T_1; // @[util.scala:288:27] assign _imm_i11_T_1 = _GEN_45; // @[util.scala:286:44, :288:27] wire _imm_i19_12_T_2 = _imm_i19_12_T | _imm_i19_12_T_1; // @[util.scala:286:{27,36,44}] wire [7:0] _imm_i19_12_T_3 = imm_ip[7:0]; // @[util.scala:282:17, :286:56] wire [7:0] _imm_i19_12_T_4 = _imm_i19_12_T_3; // @[util.scala:286:{56,62}] wire [7:0] imm_i19_12 = _imm_i19_12_T_2 ? _imm_i19_12_T_4 : {8{imm_sign}}; // @[util.scala:284:37, :286:{21,36,62}] wire [7:0] imm_hi_lo_hi = imm_i19_12; // @[util.scala:286:21, :294:15] wire _imm_i11_T_3 = _imm_i11_T_1 | _imm_i11_T_2; // @[util.scala:288:{27,36,44}] wire _imm_i11_T_4 = imm_ip[8]; // @[util.scala:282:17, :288:56] wire _imm_i0_T_3 = imm_ip[8]; // @[util.scala:282:17, :288:56, :291:56] wire _imm_i11_T_5 = _imm_i11_T_4; // @[util.scala:288:{56,60}] wire _imm_i11_T_6 = _imm_i11_T_3 ? _imm_i11_T_5 : imm_sign; // @[util.scala:284:37, :288:{21,36,60}] wire imm_i11 = ~_imm_i11_T & _imm_i11_T_6; // @[util.scala:287:{21,27}, :288:21] wire imm_hi_lo_lo = imm_i11; // @[util.scala:287:21, :294:15] wire [4:0] _imm_i10_5_T_1 = imm_ip[18:14]; // @[util.scala:282:17, :289:44] wire [4:0] _imm_i10_5_T_2 = _imm_i10_5_T_1; // @[util.scala:289:{44,52}] wire [4:0] imm_i10_5 = _imm_i10_5_T ? 5'h0 : _imm_i10_5_T_2; // @[util.scala:289:{21,27,52}] wire [4:0] imm_lo_hi_hi = imm_i10_5; // @[util.scala:289:21, :294:15] wire [4:0] _imm_i4_1_T_1 = imm_ip[13:9]; // @[util.scala:282:17, :290:44] wire [4:0] _imm_i4_1_T_2 = _imm_i4_1_T_1; // @[util.scala:290:{44,51}] wire [4:0] imm_i4_1 = _imm_i4_1_T ? 5'h0 : _imm_i4_1_T_2; // @[util.scala:290:{21,27,51}] wire [4:0] imm_lo_hi_lo = imm_i4_1; // @[util.scala:290:21, :294:15] wire _imm_i0_T_1 = cs_imm_sel == 3'h0; // @[util.scala:291:44] wire _imm_i0_T_2 = _imm_i0_T | _imm_i0_T_1; // @[util.scala:291:{27,36,44}] wire _imm_i0_T_4 = _imm_i0_T_3; // @[util.scala:291:{56,60}] wire imm_i0 = _imm_i0_T_2 & _imm_i0_T_4; // @[util.scala:291:{21,36,60}] wire imm_lo_lo = imm_i0; // @[util.scala:291:21, :294:15] wire [9:0] imm_lo_hi = {imm_lo_hi_hi, imm_lo_hi_lo}; // @[util.scala:294:15] wire [10:0] imm_lo = {imm_lo_hi, imm_lo_lo}; // @[util.scala:294:15] wire [8:0] imm_hi_lo = {imm_hi_lo_hi, imm_hi_lo_lo}; // @[util.scala:294:15] wire [11:0] imm_hi_hi = {imm_hi_hi_hi, imm_hi_hi_lo}; // @[util.scala:294:15] wire [20:0] imm_hi = {imm_hi_hi, imm_hi_lo}; // @[util.scala:294:15] wire [31:0] imm = {imm_hi, imm_lo}; // @[util.scala:294:15] wire [27:0] imm_hi_1 = imm[31:4]; // @[util.scala:294:15] wire [4:0] imm_lo_1 = imm[4:0]; // @[util.scala:294:15] wire _short_imm_T = imm_hi_1 == 28'h0; // @[pla.scala:114:36] wire [27:0] _short_imm_T_1 = ~imm_hi_1; // @[decode.scala:543:20, :545:37] wire _short_imm_T_2 = _short_imm_T_1 == 28'h0; // @[pla.scala:114:36] wire _short_imm_T_3 = _short_imm_T | _short_imm_T_2; // @[decode.scala:545:{26,34,45}] wire _short_imm_T_4 = &cs_imm_sel; // @[decode.scala:447:16, :545:67] wire short_imm = _short_imm_T_3 | _short_imm_T_4; // @[decode.scala:545:{34,53,67}] wire _uop_imm_rename_T = cs_imm_sel != 3'h6; // @[decode.scala:447:16, :547:32] wire _uop_imm_rename_T_1 = ~(&cs_imm_sel); // @[decode.scala:447:16, :545:67, :547:55] wire _uop_imm_rename_T_2 = _uop_imm_rename_T & _uop_imm_rename_T_1; // @[decode.scala:547:{32,41,55}] assign uop_imm_rename = ~short_imm & _uop_imm_rename_T_2; // @[decode.scala:428:17, :545:53, :547:{18,41}, :550:20, :551:20] assign uop_imm_sel = short_imm ? 3'h5 : cs_imm_sel; // @[decode.scala:428:17, :447:16, :545:53, :549:18, :550:20, :552:17] wire _uop_pimm_T = &cs_imm_sel; // @[decode.scala:447:16, :545:67, :553:32] wire [4:0] _uop_pimm_T_2 = _uop_pimm_T ? {2'h0, _uop_pimm_T_1} : imm_lo_1; // @[decode.scala:544:19, :553:{20,32,47}] assign uop_pimm = short_imm ? _uop_pimm_T_2 : 5'h0; // @[decode.scala:422:7, :426:14, :428:17, :429:7, :545:53, :550:20, :553:{14,20}] wire _uop_fp_rm_T_1 = &_uop_fp_rm_T; // @[decode.scala:556:{26,34}] assign _uop_fp_rm_T_3 = _uop_fp_rm_T_1 ? io_fcsr_rm_0 : _uop_fp_rm_T_2; // @[decode.scala:422:7, :556:{21,34,59}] assign uop_fp_rm = _uop_fp_rm_T_3; // @[decode.scala:428:17, :556:21] assign _uop_fp_typ_T = uop_inst[21:20]; // @[decode.scala:428:17, :557:22] assign uop_fp_typ = _uop_fp_typ_T; // @[decode.scala:428:17, :557:22] assign uop_csr_cmd = (_T_29 | (&cs_csr_cmd)) & ~(|LRS1) ? 3'h2 : cs_csr_cmd; // @[package.scala:16:47] wire [31:0] _uop_br_type_T_18 = {25'h0, _uop_is_rocc_T}; // @[decode.scala:529:48, :532:25, :572:14, :604:36] wire [9:0] _GEN_46 = {uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :526:26, :532:25] wire [16:0] _GEN_47 = {_imm_packed_T, uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :485:26, :532:25, :541:28] assign uop_op1_sel = _uop_is_rocc_T == 7'h37 | _GEN_46 == 10'h2F3 | _GEN_46 == 10'h373 | _GEN_46 == 10'h3F3 | uop_inst == 32'h10500073 | uop_inst == 32'h10200073 | uop_inst == 32'h30200073 | uop_inst == 32'h7B200073 ? 2'h1 : _uop_is_rocc_T == 7'h6F | _GEN_46 == 10'h67 | _uop_is_rocc_T == 7'h17 ? 2'h2 : {2{_GEN_47 == 17'h4133 | _GEN_47 == 17'h4233 | _GEN_47 == 17'h4333 | _GEN_47 == 17'h413B | _GEN_47 == 17'h423B | _GEN_47 == 17'h433B | _GEN_47 == 17'h103B | {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T} == 16'h89B}}; // @[package.scala:81:59] wire [15:0] _GEN_48 = {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :532:25, :589:65] wire _uop_op2_sel_T = uop_lrs2_rtype == 2'h0; // @[decode.scala:428:17, :590:39] wire [2:0] _uop_op2_sel_T_1 = _uop_op2_sel_T ? 3'h5 : 3'h6; // @[decode.scala:590:{23,39}] assign uop_op2_sel = cs_is_amo | _GEN_46 == 10'hF3 | _GEN_46 == 10'h173 | _GEN_46 == 10'h1F3 ? 3'h2 : _GEN_46 == 10'h2F3 | _GEN_46 == 10'h373 | _GEN_46 == 10'h3F3 | uop_inst == 32'h10500073 | uop_inst == 32'h10200073 | uop_inst == 32'h7B200073 | uop_inst == 32'h30200073 ? 3'h4 : _uop_is_rocc_T == 7'h6F | _GEN_46 == 10'h67 ? 3'h3 : _GEN_47 == 17'h90B3 | _GEN_48 == 16'h4893 | _GEN_47 == 17'hD0B3 | _GEN_48 == 16'h6893 | _GEN_47 == 17'h50B3 | {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T} == 16'h2893 ? _uop_op2_sel_T_1 : {2'h0, _T_139 | _imm_i0_T_1 | _T_142}; // @[package.scala:16:47, :81:59] wire _uop_br_type_T_1 = _uop_br_type_T == 32'h63; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_2 = {2'h0, _uop_br_type_T_1, 1'h0}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_4 = _uop_br_type_T_3 == 32'h1063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_5 = {3'h0, _uop_br_type_T_4}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_7 = _uop_br_type_T_6 == 32'h5063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_8 = _uop_br_type_T_7 ? 4'h3 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_10 = _uop_br_type_T_9 == 32'h7063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_11 = {1'h0, _uop_br_type_T_10, 2'h0}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_13 = _uop_br_type_T_12 == 32'h4063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_14 = _uop_br_type_T_13 ? 4'h5 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_16 = _uop_br_type_T_15 == 32'h6063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_17 = _uop_br_type_T_16 ? 4'h6 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_19 = _uop_br_type_T_18 == 32'h6F; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_20 = _uop_br_type_T_19 ? 4'h7 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_22 = _uop_br_type_T_21 == 32'h67; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_23 = {_uop_br_type_T_22, 3'h0}; // @[decode.scala:604:{30,36}] wire [3:0] _uop_br_type_T_24 = _uop_br_type_T_2 | _uop_br_type_T_5; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_25 = _uop_br_type_T_24 | _uop_br_type_T_8; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_26 = _uop_br_type_T_25 | _uop_br_type_T_11; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_27 = _uop_br_type_T_26 | _uop_br_type_T_14; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_28 = _uop_br_type_T_27 | _uop_br_type_T_17; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_29 = _uop_br_type_T_28 | _uop_br_type_T_20; // @[decode.scala:604:{30,62}] assign _uop_br_type_T_30 = _uop_br_type_T_29 | _uop_br_type_T_23; // @[decode.scala:604:{30,62}] assign uop_br_type = _uop_br_type_T_30; // @[decode.scala:428:17, :604:62] assign io_deq_uop_inst = io_deq_uop_inst_0; // @[decode.scala:422:7] assign io_deq_uop_debug_inst = io_deq_uop_debug_inst_0; // @[decode.scala:422:7] assign io_deq_uop_is_rvc = io_deq_uop_is_rvc_0; // @[decode.scala:422:7] assign io_deq_uop_debug_pc = io_deq_uop_debug_pc_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_0 = io_deq_uop_iq_type_0_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_1 = io_deq_uop_iq_type_1_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_2 = io_deq_uop_iq_type_2_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_3 = io_deq_uop_iq_type_3_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_0 = io_deq_uop_fu_code_0_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_1 = io_deq_uop_fu_code_1_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_2 = io_deq_uop_fu_code_2_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_3 = io_deq_uop_fu_code_3_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_4 = io_deq_uop_fu_code_4_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_5 = io_deq_uop_fu_code_5_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_6 = io_deq_uop_fu_code_6_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_7 = io_deq_uop_fu_code_7_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_8 = io_deq_uop_fu_code_8_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_9 = io_deq_uop_fu_code_9_0; // @[decode.scala:422:7] assign io_deq_uop_br_type = io_deq_uop_br_type_0; // @[decode.scala:422:7] assign io_deq_uop_is_sfb = io_deq_uop_is_sfb_0; // @[decode.scala:422:7] assign io_deq_uop_is_fence = io_deq_uop_is_fence_0; // @[decode.scala:422:7] assign io_deq_uop_is_fencei = io_deq_uop_is_fencei_0; // @[decode.scala:422:7] assign io_deq_uop_is_sfence = io_deq_uop_is_sfence_0; // @[decode.scala:422:7] assign io_deq_uop_is_amo = io_deq_uop_is_amo_0; // @[decode.scala:422:7] assign io_deq_uop_is_eret = io_deq_uop_is_eret_0; // @[decode.scala:422:7] assign io_deq_uop_is_sys_pc2epc = io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:422:7] assign io_deq_uop_is_rocc = io_deq_uop_is_rocc_0; // @[decode.scala:422:7] assign io_deq_uop_is_mov = io_deq_uop_is_mov_0; // @[decode.scala:422:7] assign io_deq_uop_ftq_idx = io_deq_uop_ftq_idx_0; // @[decode.scala:422:7] assign io_deq_uop_edge_inst = io_deq_uop_edge_inst_0; // @[decode.scala:422:7] assign io_deq_uop_pc_lob = io_deq_uop_pc_lob_0; // @[decode.scala:422:7] assign io_deq_uop_taken = io_deq_uop_taken_0; // @[decode.scala:422:7] assign io_deq_uop_imm_rename = io_deq_uop_imm_rename_0; // @[decode.scala:422:7] assign io_deq_uop_imm_sel = io_deq_uop_imm_sel_0; // @[decode.scala:422:7] assign io_deq_uop_pimm = io_deq_uop_pimm_0; // @[decode.scala:422:7] assign io_deq_uop_imm_packed = io_deq_uop_imm_packed_0; // @[decode.scala:422:7] assign io_deq_uop_op1_sel = io_deq_uop_op1_sel_0; // @[decode.scala:422:7] assign io_deq_uop_op2_sel = io_deq_uop_op2_sel_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ldst = io_deq_uop_fp_ctrl_ldst_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_wen = io_deq_uop_fp_ctrl_wen_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren1 = io_deq_uop_fp_ctrl_ren1_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren2 = io_deq_uop_fp_ctrl_ren2_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren3 = io_deq_uop_fp_ctrl_ren3_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_swap12 = io_deq_uop_fp_ctrl_swap12_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_swap23 = io_deq_uop_fp_ctrl_swap23_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_typeTagIn = io_deq_uop_fp_ctrl_typeTagIn_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_typeTagOut = io_deq_uop_fp_ctrl_typeTagOut_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fromint = io_deq_uop_fp_ctrl_fromint_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_toint = io_deq_uop_fp_ctrl_toint_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fastpipe = io_deq_uop_fp_ctrl_fastpipe_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fma = io_deq_uop_fp_ctrl_fma_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_div = io_deq_uop_fp_ctrl_div_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_sqrt = io_deq_uop_fp_ctrl_sqrt_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_wflags = io_deq_uop_fp_ctrl_wflags_0; // @[decode.scala:422:7] assign io_deq_uop_exception = io_deq_uop_exception_0; // @[decode.scala:422:7] assign io_deq_uop_exc_cause = io_deq_uop_exc_cause_0; // @[decode.scala:422:7] assign io_deq_uop_mem_cmd = io_deq_uop_mem_cmd_0; // @[decode.scala:422:7] assign io_deq_uop_mem_size = io_deq_uop_mem_size_0; // @[decode.scala:422:7] assign io_deq_uop_mem_signed = io_deq_uop_mem_signed_0; // @[decode.scala:422:7] assign io_deq_uop_uses_ldq = io_deq_uop_uses_ldq_0; // @[decode.scala:422:7] assign io_deq_uop_uses_stq = io_deq_uop_uses_stq_0; // @[decode.scala:422:7] assign io_deq_uop_is_unique = io_deq_uop_is_unique_0; // @[decode.scala:422:7] assign io_deq_uop_flush_on_commit = io_deq_uop_flush_on_commit_0; // @[decode.scala:422:7] assign io_deq_uop_csr_cmd = io_deq_uop_csr_cmd_0; // @[decode.scala:422:7] assign io_deq_uop_ldst_is_rs1 = io_deq_uop_ldst_is_rs1_0; // @[decode.scala:422:7] assign io_deq_uop_ldst = io_deq_uop_ldst_0; // @[decode.scala:422:7] assign io_deq_uop_lrs1 = io_deq_uop_lrs1_0; // @[decode.scala:422:7] assign io_deq_uop_lrs2 = io_deq_uop_lrs2_0; // @[decode.scala:422:7] assign io_deq_uop_lrs3 = io_deq_uop_lrs3_0; // @[decode.scala:422:7] assign io_deq_uop_dst_rtype = io_deq_uop_dst_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_lrs1_rtype = io_deq_uop_lrs1_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_lrs2_rtype = io_deq_uop_lrs2_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_frs3_en = io_deq_uop_frs3_en_0; // @[decode.scala:422:7] assign io_deq_uop_fcn_dw = io_deq_uop_fcn_dw_0; // @[decode.scala:422:7] assign io_deq_uop_fcn_op = io_deq_uop_fcn_op_0; // @[decode.scala:422:7] assign io_deq_uop_fp_val = io_deq_uop_fp_val_0; // @[decode.scala:422:7] assign io_deq_uop_fp_rm = io_deq_uop_fp_rm_0; // @[decode.scala:422:7] assign io_deq_uop_fp_typ = io_deq_uop_fp_typ_0; // @[decode.scala:422:7] assign io_deq_uop_xcpt_pf_if = io_deq_uop_xcpt_pf_if_0; // @[decode.scala:422:7] assign io_deq_uop_xcpt_ae_if = io_deq_uop_xcpt_ae_if_0; // @[decode.scala:422:7] assign io_deq_uop_bp_debug_if = io_deq_uop_bp_debug_if_0; // @[decode.scala:422:7] assign io_deq_uop_bp_xcpt_if = io_deq_uop_bp_xcpt_if_0; // @[decode.scala:422:7] assign io_deq_uop_debug_fsrc = io_deq_uop_debug_fsrc_0; // @[decode.scala:422:7] assign io_csr_decode_inst = io_csr_decode_inst_0; // @[decode.scala:422:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_32( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_15( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_126( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_66( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_6( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_4 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [17:0] _GEN_2 = io_in_b_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:18], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:18], io_in_b_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [17:0] _GEN_3 = io_in_b_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:18], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [20:0] _GEN_4 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:21], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [25:0] _GEN_5 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_55 = {io_in_b_bits_address_0[31:26], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire [25:0] _GEN_6 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_60 = {io_in_b_bits_address_0[31:26], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_61 = {1'h0, _address_ok_T_60}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_62 = _address_ok_T_61 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_63 = _address_ok_T_62; // @[Parameters.scala:137:46] wire _address_ok_T_64 = _address_ok_T_63 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_12 = _address_ok_T_64; // @[Parameters.scala:612:40] wire [27:0] _GEN_7 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_65 = {io_in_b_bits_address_0[31:28], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_66 = {1'h0, _address_ok_T_65}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_67 = _address_ok_T_66 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_68 = _address_ok_T_67; // @[Parameters.scala:137:46] wire _address_ok_T_69 = _address_ok_T_68 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_13 = _address_ok_T_69; // @[Parameters.scala:612:40] wire [27:0] _GEN_8 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = {io_in_b_bits_address_0[31:28], _GEN_8}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_14 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [28:0] _GEN_9 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_75 = {io_in_b_bits_address_0[31:29], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_15 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_80 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_16 = _address_ok_T_84; // @[Parameters.scala:612:40] wire _address_ok_T_85 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_86 = _address_ok_T_85 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_87 = _address_ok_T_86 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_88 = _address_ok_T_87 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_89 = _address_ok_T_88 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_90 = _address_ok_T_89 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_91 = _address_ok_T_90 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_92 = _address_ok_T_91 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_93 = _address_ok_T_92 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_94 = _address_ok_T_93 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_95 = _address_ok_T_94 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_96 = _address_ok_T_95 | _address_ok_WIRE_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_97 = _address_ok_T_96 | _address_ok_WIRE_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_98 = _address_ok_T_97 | _address_ok_WIRE_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_99 = _address_ok_T_98 | _address_ok_WIRE_15; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_99 | _address_ok_WIRE_16; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_5 = _legal_source_WIRE_2; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_3 = {_legal_source_WIRE_0, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_6 = _legal_source_T_3; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {_legal_source_T_6[1], _legal_source_T_6[0] | _legal_source_T_5}; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_10 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_10; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_10; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_10; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [13:0] _GEN_11 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:14], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [16:0] _GEN_12 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:17], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [17:0] _GEN_13 = io_in_c_bits_address_0[17:0] ^ 18'h20000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:18], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h21000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_129; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_130 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h22000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_131 = {1'h0, _address_ok_T_130}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_132 = _address_ok_T_131 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_133 = _address_ok_T_132; // @[Parameters.scala:137:46] wire _address_ok_T_134 = _address_ok_T_133 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_134; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_135 = {io_in_c_bits_address_0[31:18], io_in_c_bits_address_0[17:0] ^ 18'h23000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_136 = {1'h0, _address_ok_T_135}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_137 = _address_ok_T_136 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_138 = _address_ok_T_137; // @[Parameters.scala:137:46] wire _address_ok_T_139 = _address_ok_T_138 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_139; // @[Parameters.scala:612:40] wire [17:0] _GEN_14 = io_in_c_bits_address_0[17:0] ^ 18'h24000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_140 = {io_in_c_bits_address_0[31:18], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_141 = {1'h0, _address_ok_T_140}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_142 = _address_ok_T_141 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_143 = _address_ok_T_142; // @[Parameters.scala:137:46] wire _address_ok_T_144 = _address_ok_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_144; // @[Parameters.scala:612:40] wire [20:0] _GEN_15 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_145 = {io_in_c_bits_address_0[31:21], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_146 = {1'h0, _address_ok_T_145}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_147 = _address_ok_T_146 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_148 = _address_ok_T_147; // @[Parameters.scala:137:46] wire _address_ok_T_149 = _address_ok_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_149; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_150 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_151 = {1'h0, _address_ok_T_150}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_152 = _address_ok_T_151 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_153 = _address_ok_T_152; // @[Parameters.scala:137:46] wire _address_ok_T_154 = _address_ok_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_154; // @[Parameters.scala:612:40] wire [25:0] _GEN_16 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_155 = {io_in_c_bits_address_0[31:26], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_156 = {1'h0, _address_ok_T_155}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_157 = _address_ok_T_156 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_158 = _address_ok_T_157; // @[Parameters.scala:137:46] wire _address_ok_T_159 = _address_ok_T_158 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_159; // @[Parameters.scala:612:40] wire [25:0] _GEN_17 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_160 = {io_in_c_bits_address_0[31:26], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_161 = {1'h0, _address_ok_T_160}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_162 = _address_ok_T_161 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_163 = _address_ok_T_162; // @[Parameters.scala:137:46] wire _address_ok_T_164 = _address_ok_T_163 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_12 = _address_ok_T_164; // @[Parameters.scala:612:40] wire [27:0] _GEN_18 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_165 = {io_in_c_bits_address_0[31:28], _GEN_18}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_166 = {1'h0, _address_ok_T_165}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_167 = _address_ok_T_166 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_168 = _address_ok_T_167; // @[Parameters.scala:137:46] wire _address_ok_T_169 = _address_ok_T_168 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_13 = _address_ok_T_169; // @[Parameters.scala:612:40] wire [27:0] _GEN_19 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_170 = {io_in_c_bits_address_0[31:28], _GEN_19}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_171 = {1'h0, _address_ok_T_170}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_172 = _address_ok_T_171 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_173 = _address_ok_T_172; // @[Parameters.scala:137:46] wire _address_ok_T_174 = _address_ok_T_173 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_14 = _address_ok_T_174; // @[Parameters.scala:612:40] wire [28:0] _GEN_20 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_175 = {io_in_c_bits_address_0[31:29], _GEN_20}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_176 = {1'h0, _address_ok_T_175}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_177 = _address_ok_T_176 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_178 = _address_ok_T_177; // @[Parameters.scala:137:46] wire _address_ok_T_179 = _address_ok_T_178 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_15 = _address_ok_T_179; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_180 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_181 = {1'h0, _address_ok_T_180}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_182 = _address_ok_T_181 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_183 = _address_ok_T_182; // @[Parameters.scala:137:46] wire _address_ok_T_184 = _address_ok_T_183 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_16 = _address_ok_T_184; // @[Parameters.scala:612:40] wire _address_ok_T_185 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_186 = _address_ok_T_185 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_187 = _address_ok_T_186 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_188 = _address_ok_T_187 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_189 = _address_ok_T_188 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_190 = _address_ok_T_189 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_191 = _address_ok_T_190 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_192 = _address_ok_T_191 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_193 = _address_ok_T_192 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_194 = _address_ok_T_193 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_195 = _address_ok_T_194 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_196 = _address_ok_T_195 | _address_ok_WIRE_1_12; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_197 = _address_ok_T_196 | _address_ok_WIRE_1_13; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_198 = _address_ok_T_197 | _address_ok_WIRE_1_14; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_199 = _address_ok_T_198 | _address_ok_WIRE_1_15; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_199 | _address_ok_WIRE_1_16; // @[Parameters.scala:612:40, :636:64] wire _T_2718 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2718; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2718; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2792 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2792; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2792; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2792; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2792; // @[Decoupled.scala:51:35] wire [26:0] _GEN_21 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_21; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_21; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_21; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_21; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2789 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2789; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2789; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_22 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_22; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_22; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_22; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_22; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_23 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_23; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_23; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_23; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_23; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_24 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_24; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2644 = _T_2718 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2644 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2644 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2644 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2644 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2644 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_25 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_25; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_25; // @[Monitor.scala:673:46, :783:46] wire _T_2690 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_26 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_26; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_26; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_26; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_26; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2690 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2659 = _T_2792 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2659 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2659 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2659 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_27 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2731 = _T_2789 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2731 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2731 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2731 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2731 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2731 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2762 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2762 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2744 = _T_2792 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2744 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2744 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2744 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2798 = _T_2792 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2798 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2807 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2807 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_5( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] reg in_flight_10; // @[Monitor.scala:16:26] reg in_flight_11; // @[Monitor.scala:16:26] reg in_flight_12; // @[Monitor.scala:16:26] reg in_flight_13; // @[Monitor.scala:16:26] reg in_flight_14; // @[Monitor.scala:16:26] reg in_flight_15; // @[Monitor.scala:16:26] reg in_flight_16; // @[Monitor.scala:16:26] reg in_flight_17; // @[Monitor.scala:16:26] reg in_flight_18; // @[Monitor.scala:16:26] reg in_flight_19; // @[Monitor.scala:16:26] reg in_flight_20; // @[Monitor.scala:16:26] reg in_flight_21; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 5'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 5'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 5'h4; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 5'h5; // @[Monitor.scala:21:46] wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 5'h6; // @[Monitor.scala:21:46] wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 5'h7; // @[Monitor.scala:21:46] wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 5'h8; // @[Monitor.scala:21:46] wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 5'h9; // @[Monitor.scala:21:46] wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 5'hC; // @[Monitor.scala:21:46] wire _GEN_8 = io_in_flit_0_bits_virt_channel_id == 5'hD; // @[Monitor.scala:21:46] wire _GEN_9 = io_in_flit_0_bits_virt_channel_id == 5'h10; // @[Monitor.scala:21:46] wire _GEN_10 = io_in_flit_0_bits_virt_channel_id == 5'h11; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File TileResetSetter.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ // Currently only works if all tiles are already driven by independent clock groups // TODO: After https://github.com/chipsalliance/rocket-chip/pull/2842 is merged, we should // always put all tiles on independent clock groups class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("tile-reset-setter", Nil) val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) val clockNode = ClockGroupIdentityNode() lazy val module = new LazyModuleImp(this) { val nTiles = p(TilesLocated(InSubsystem)).size require (nTiles <= 4096 / 4) val tile_async_resets = Wire(Vec(nTiles, Reset())) val r_tile_resets = (0 until nTiles).map({ i => tile_async_resets(i) := true.B.asAsyncReset // Remove this line after https://github.com/chipsalliance/rocket-chip/pull/2842 withReset (tile_async_resets(i)) { Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0))) } }) if (nTiles > 0) tlNode.regmap((0 until nTiles).map({ i => i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)) }): _*) val tileMap = tileNames.zipWithIndex.map({ case (n, i) => n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i * 4) }) (clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) => (o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) => oD.clock := iD.clock oD.reset := iD.reset for ((n, (rIn, rOut, addr)) <- tileMap) { if (name.contains(n)) { println(s"${addr.toString(16)}: Tile $name reset control") // Async because the reset coming out of the AsyncResetRegVec is // clocked to the bus this is attached to, not the clock in this // clock bundle. We expect a ClockGroupResetSynchronizer downstream // to synchronize the resets // Also, this or enforces that the tiles come out of reset after the reset of the system oD.reset := (rOut.asBool || iD.reset.asBool).asAsyncReset rIn := iD.reset } } } } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire [2:0] tlNodeIn_d_bits_opcode = {2'h0, auto_tl_in_a_bits_opcode == 3'h4}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_63 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_tl_in_d_ready), .io_in_a_valid (auto_tl_in_a_valid), .io_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .io_in_a_bits_param (auto_tl_in_a_bits_param), .io_in_a_bits_size (auto_tl_in_a_bits_size), .io_in_a_bits_source (auto_tl_in_a_bits_source), .io_in_a_bits_address (auto_tl_in_a_bits_address), .io_in_a_bits_mask (auto_tl_in_a_bits_mask), .io_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .io_in_d_ready (auto_tl_in_d_ready), .io_in_d_valid (auto_tl_in_a_valid), .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_tl_in_a_bits_size), .io_in_d_bits_source (auto_tl_in_a_bits_source) ); // @[Nodes.scala:27:25] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = tlNodeIn_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File IBuf.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Decoupled,log2Ceil,Cat,UIntToOH,Fill} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters { val xcpt0 = new FrontendExceptions // exceptions on first half of instruction val xcpt1 = new FrontendExceptions // exceptions on second half of instruction val replay = Bool() val rvc = Bool() val inst = new ExpandedInstruction val raw = UInt(32.W) require(coreInstBits == (if (usingCompressed) 16 else 32)) } class IBuf(implicit p: Parameters) extends CoreModule { val io = IO(new Bundle { val imem = Flipped(Decoupled(new FrontendResp)) val kill = Input(Bool()) val pc = Output(UInt(vaddrBitsExtended.W)) val btb_resp = Output(new BTBResp()) val inst = Vec(retireWidth, Decoupled(new Instruction)) }) // This module is meant to be more general, but it's not there yet require(decodeWidth == 1) val n = fetchWidth - 1 val nBufValid = if (n == 0) 0.U else RegInit(init=0.U(log2Ceil(fetchWidth).W)) val buf = Reg(chiselTypeOf(io.imem.bits)) val ibufBTBResp = Reg(new BTBResp) val pcWordMask = (coreInstBytes*fetchWidth-1).U(vaddrBitsExtended.W) val pcWordBits = io.imem.bits.pc.extract(log2Ceil(fetchWidth*coreInstBytes)-1, log2Ceil(coreInstBytes)) val nReady = WireDefault(0.U(log2Ceil(fetchWidth+1).W)) val nIC = Mux(io.imem.bits.btb.taken, io.imem.bits.btb.bridx +& 1.U, fetchWidth.U) - pcWordBits val nICReady = nReady - nBufValid val nValid = Mux(io.imem.valid, nIC, 0.U) + nBufValid io.imem.ready := io.inst(0).ready && nReady >= nBufValid && (nICReady >= nIC || n.U >= nIC - nICReady) if (n > 0) { when (io.inst(0).ready) { nBufValid := Mux(nReady >== nBufValid, 0.U, nBufValid - nReady) if (n > 1) when (nReady > 0.U && nReady < nBufValid) { val shiftedBuf = shiftInsnRight(buf.data(n*coreInstBits-1, coreInstBits), (nReady-1.U)(log2Ceil(n-1)-1,0)) buf.data := Cat(buf.data(n*coreInstBits-1, (n-1)*coreInstBits), shiftedBuf((n-1)*coreInstBits-1, 0)) buf.pc := buf.pc & ~pcWordMask | (buf.pc + (nReady << log2Ceil(coreInstBytes))) & pcWordMask } when (io.imem.valid && nReady >= nBufValid && nICReady < nIC && n.U >= nIC - nICReady) { val shamt = pcWordBits + nICReady nBufValid := nIC - nICReady buf := io.imem.bits buf.data := shiftInsnRight(io.imem.bits.data, shamt)(n*coreInstBits-1,0) buf.pc := io.imem.bits.pc & ~pcWordMask | (io.imem.bits.pc + (nICReady << log2Ceil(coreInstBytes))) & pcWordMask ibufBTBResp := io.imem.bits.btb } } when (io.kill) { nBufValid := 0.U } } val icShiftAmt = (fetchWidth.U + nBufValid - pcWordBits)(log2Ceil(fetchWidth), 0) val icData = shiftInsnLeft(Cat(io.imem.bits.data, Fill(fetchWidth, io.imem.bits.data(coreInstBits-1, 0))), icShiftAmt) .extract(3*fetchWidth*coreInstBits-1, 2*fetchWidth*coreInstBits) val icMask = (~0.U((fetchWidth*coreInstBits).W) << (nBufValid << log2Ceil(coreInstBits)))(fetchWidth*coreInstBits-1,0) val inst = icData & icMask | buf.data & ~icMask val valid = (UIntToOH(nValid) - 1.U)(fetchWidth-1, 0) val bufMask = UIntToOH(nBufValid) - 1.U val xcpt = (0 until bufMask.getWidth).map(i => Mux(bufMask(i), buf.xcpt, io.imem.bits.xcpt)) val buf_replay = Mux(buf.replay, bufMask, 0.U) val ic_replay = buf_replay | Mux(io.imem.bits.replay, valid & ~bufMask, 0.U) assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits) io.btb_resp := io.imem.bits.btb io.pc := Mux(nBufValid > 0.U, buf.pc, io.imem.bits.pc) expand(0, 0.U, inst) def expand(i: Int, j: UInt, curInst: UInt): Unit = if (i < retireWidth) { val exp = Module(new RVCExpander) exp.io.in := curInst io.inst(i).bits.inst := exp.io.out io.inst(i).bits.raw := curInst if (usingCompressed) { val replay = ic_replay(j) || (!exp.io.rvc && ic_replay(j+1.U)) val full_insn = exp.io.rvc || valid(j+1.U) || buf_replay(j) io.inst(i).valid := valid(j) && full_insn io.inst(i).bits.xcpt0 := xcpt(j) io.inst(i).bits.xcpt1 := Mux(exp.io.rvc, 0.U, xcpt(j+1.U).asUInt).asTypeOf(new FrontendExceptions) io.inst(i).bits.replay := replay io.inst(i).bits.rvc := exp.io.rvc when ((bufMask(j) && exp.io.rvc) || bufMask(j+1.U)) { io.btb_resp := ibufBTBResp } when (full_insn && ((i == 0).B || io.inst(i).ready)) { nReady := Mux(exp.io.rvc, j+1.U, j+2.U) } expand(i+1, Mux(exp.io.rvc, j+1.U, j+2.U), Mux(exp.io.rvc, curInst >> 16, curInst >> 32)) } else { when ((i == 0).B || io.inst(i).ready) { nReady := (i+1).U } io.inst(i).valid := valid(i) io.inst(i).bits.xcpt0 := xcpt(i) io.inst(i).bits.xcpt1 := 0.U.asTypeOf(new FrontendExceptions) io.inst(i).bits.replay := ic_replay(i) io.inst(i).bits.rvc := false.B expand(i+1, null, curInst >> 32) } } def shiftInsnLeft(in: UInt, dist: UInt) = { val r = in.getWidth/coreInstBits require(in.getWidth % coreInstBits == 0) val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in) data << (dist << log2Ceil(coreInstBits)) } def shiftInsnRight(in: UInt, dist: UInt) = { val r = in.getWidth/coreInstBits require(in.getWidth % coreInstBits == 0) val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in) data >> (dist << log2Ceil(coreInstBits)) } }
module IBuf_2( // @[IBuf.scala:21:7] input clock, // @[IBuf.scala:21:7] input reset, // @[IBuf.scala:21:7] output io_imem_ready, // @[IBuf.scala:22:14] input io_imem_valid, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_cfiType, // @[IBuf.scala:22:14] input io_imem_bits_btb_taken, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_mask, // @[IBuf.scala:22:14] input io_imem_bits_btb_bridx, // @[IBuf.scala:22:14] input [38:0] io_imem_bits_btb_target, // @[IBuf.scala:22:14] input [4:0] io_imem_bits_btb_entry, // @[IBuf.scala:22:14] input [7:0] io_imem_bits_btb_bht_history, // @[IBuf.scala:22:14] input io_imem_bits_btb_bht_value, // @[IBuf.scala:22:14] input [39:0] io_imem_bits_pc, // @[IBuf.scala:22:14] input [31:0] io_imem_bits_data, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_mask, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_pf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_gf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_ae_inst, // @[IBuf.scala:22:14] input io_imem_bits_replay, // @[IBuf.scala:22:14] input io_kill, // @[IBuf.scala:22:14] output [39:0] io_pc, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_cfiType, // @[IBuf.scala:22:14] output io_btb_resp_taken, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_mask, // @[IBuf.scala:22:14] output io_btb_resp_bridx, // @[IBuf.scala:22:14] output [38:0] io_btb_resp_target, // @[IBuf.scala:22:14] output [4:0] io_btb_resp_entry, // @[IBuf.scala:22:14] output [7:0] io_btb_resp_bht_history, // @[IBuf.scala:22:14] output io_btb_resp_bht_value, // @[IBuf.scala:22:14] input io_inst_0_ready, // @[IBuf.scala:22:14] output io_inst_0_valid, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_replay, // @[IBuf.scala:22:14] output io_inst_0_bits_rvc, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_inst_bits, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rd, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs1, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs2, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs3, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_raw // @[IBuf.scala:22:14] ); wire _exp_io_rvc; // @[IBuf.scala:86:21] wire io_imem_valid_0 = io_imem_valid; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_cfiType_0 = io_imem_bits_btb_cfiType; // @[IBuf.scala:21:7] wire io_imem_bits_btb_taken_0 = io_imem_bits_btb_taken; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_mask_0 = io_imem_bits_btb_mask; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bridx_0 = io_imem_bits_btb_bridx; // @[IBuf.scala:21:7] wire [38:0] io_imem_bits_btb_target_0 = io_imem_bits_btb_target; // @[IBuf.scala:21:7] wire [4:0] io_imem_bits_btb_entry_0 = io_imem_bits_btb_entry; // @[IBuf.scala:21:7] wire [7:0] io_imem_bits_btb_bht_history_0 = io_imem_bits_btb_bht_history; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bht_value_0 = io_imem_bits_btb_bht_value; // @[IBuf.scala:21:7] wire [39:0] io_imem_bits_pc_0 = io_imem_bits_pc; // @[IBuf.scala:21:7] wire [31:0] io_imem_bits_data_0 = io_imem_bits_data; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_mask_0 = io_imem_bits_mask; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_pf_inst_0 = io_imem_bits_xcpt_pf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_gf_inst_0 = io_imem_bits_xcpt_gf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_ae_inst_0 = io_imem_bits_xcpt_ae_inst; // @[IBuf.scala:21:7] wire io_imem_bits_replay_0 = io_imem_bits_replay; // @[IBuf.scala:21:7] wire io_kill_0 = io_kill; // @[IBuf.scala:21:7] wire io_inst_0_ready_0 = io_inst_0_ready; // @[IBuf.scala:21:7] wire [1:0] _replay_T_3 = 2'h1; // @[IBuf.scala:92:63] wire [1:0] _full_insn_T = 2'h1; // @[IBuf.scala:93:44] wire [1:0] _io_inst_0_bits_xcpt1_T = 2'h1; // @[IBuf.scala:96:59] wire [1:0] _nReady_T = 2'h1; // @[IBuf.scala:102:89] wire [1:0] _nReady_T_3 = 2'h2; // @[IBuf.scala:102:96] wire _replay_T_4 = 1'h1; // @[IBuf.scala:92:63] wire _full_insn_T_1 = 1'h1; // @[IBuf.scala:93:44] wire _io_inst_0_bits_xcpt1_T_1 = 1'h1; // @[IBuf.scala:96:59] wire _io_inst_0_bits_xcpt1_T_2 = 1'h1; // @[package.scala:39:86] wire _nReady_T_1 = 1'h1; // @[IBuf.scala:102:89] wire _io_inst_0_bits_xcpt0_T = 1'h0; // @[package.scala:39:86] wire [31:0] _icMask_T = 32'hFFFFFFFF; // @[IBuf.scala:71:17] wire [39:0] _buf_pc_T = 40'hFFFFFFFFFC; // @[IBuf.scala:59:37] wire [2:0] _nReady_T_2 = 3'h2; // @[IBuf.scala:102:96] wire _io_imem_ready_T_7; // @[IBuf.scala:44:60] wire [39:0] _io_pc_T_1; // @[IBuf.scala:82:15] wire _io_inst_0_valid_T_2; // @[IBuf.scala:94:36] wire _io_inst_0_bits_xcpt0_T_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_ae_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_WIRE_pf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_gf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_ae_inst; // @[IBuf.scala:96:81] wire replay; // @[IBuf.scala:92:33] wire [31:0] inst; // @[IBuf.scala:72:30] wire io_imem_ready_0; // @[IBuf.scala:21:7] wire [7:0] io_btb_resp_bht_history_0; // @[IBuf.scala:21:7] wire io_btb_resp_bht_value_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_cfiType_0; // @[IBuf.scala:21:7] wire io_btb_resp_taken_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_mask_0; // @[IBuf.scala:21:7] wire io_btb_resp_bridx_0; // @[IBuf.scala:21:7] wire [38:0] io_btb_resp_target_0; // @[IBuf.scala:21:7] wire [4:0] io_btb_resp_entry_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_ae_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_ae_inst_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_inst_bits_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rd_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs1_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs2_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs3_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_replay_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_rvc_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_raw_0; // @[IBuf.scala:21:7] wire io_inst_0_valid_0; // @[IBuf.scala:21:7] wire [39:0] io_pc_0; // @[IBuf.scala:21:7] reg nBufValid; // @[IBuf.scala:34:47] wire _io_pc_T = nBufValid; // @[IBuf.scala:34:47, :82:26] reg [1:0] buf_btb_cfiType; // @[IBuf.scala:35:16] reg buf_btb_taken; // @[IBuf.scala:35:16] reg [1:0] buf_btb_mask; // @[IBuf.scala:35:16] reg buf_btb_bridx; // @[IBuf.scala:35:16] reg [38:0] buf_btb_target; // @[IBuf.scala:35:16] reg [4:0] buf_btb_entry; // @[IBuf.scala:35:16] reg [7:0] buf_btb_bht_history; // @[IBuf.scala:35:16] reg buf_btb_bht_value; // @[IBuf.scala:35:16] reg [39:0] buf_pc; // @[IBuf.scala:35:16] reg [31:0] buf_data; // @[IBuf.scala:35:16] reg [1:0] buf_mask; // @[IBuf.scala:35:16] reg buf_xcpt_pf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_gf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_ae_inst; // @[IBuf.scala:35:16] reg buf_replay; // @[IBuf.scala:35:16] reg [1:0] ibufBTBResp_cfiType; // @[IBuf.scala:36:24] reg ibufBTBResp_taken; // @[IBuf.scala:36:24] reg [1:0] ibufBTBResp_mask; // @[IBuf.scala:36:24] reg ibufBTBResp_bridx; // @[IBuf.scala:36:24] reg [38:0] ibufBTBResp_target; // @[IBuf.scala:36:24] reg [4:0] ibufBTBResp_entry; // @[IBuf.scala:36:24] reg [7:0] ibufBTBResp_bht_history; // @[IBuf.scala:36:24] reg ibufBTBResp_bht_value; // @[IBuf.scala:36:24] wire pcWordBits = io_imem_bits_pc_0[1]; // @[package.scala:163:13] wire [1:0] nReady; // @[IBuf.scala:40:27] wire [1:0] _nIC_T = {1'h0, io_imem_bits_btb_bridx_0} + 2'h1; // @[IBuf.scala:21:7, :41:64] wire [1:0] _nIC_T_1 = io_imem_bits_btb_taken_0 ? _nIC_T : 2'h2; // @[IBuf.scala:21:7, :41:{16,64}] wire [2:0] _GEN = {2'h0, pcWordBits}; // @[package.scala:163:13] wire [2:0] _nIC_T_2 = {1'h0, _nIC_T_1} - _GEN; // @[IBuf.scala:41:{16,86}] wire [1:0] nIC = _nIC_T_2[1:0]; // @[IBuf.scala:41:86] wire [2:0] _GEN_0 = {1'h0, nReady}; // @[IBuf.scala:40:27, :42:25] wire [2:0] _GEN_1 = {2'h0, nBufValid}; // @[IBuf.scala:34:47, :42:25] wire [2:0] _nICReady_T = _GEN_0 - _GEN_1; // @[IBuf.scala:42:25] wire [1:0] nICReady = _nICReady_T[1:0]; // @[IBuf.scala:42:25] wire [1:0] _nValid_T = io_imem_valid_0 ? nIC : 2'h0; // @[IBuf.scala:21:7, :41:86, :43:19] wire [2:0] _nValid_T_1 = {1'h0, _nValid_T} + _GEN_1; // @[IBuf.scala:42:25, :43:{19,45}] wire [1:0] nValid = _nValid_T_1[1:0]; // @[IBuf.scala:43:45] wire [1:0] _GEN_2 = {1'h0, nBufValid}; // @[IBuf.scala:34:47, :44:47] wire _T = nReady >= _GEN_2; // @[IBuf.scala:40:27, :44:47] wire _io_imem_ready_T; // @[IBuf.scala:44:47] assign _io_imem_ready_T = _T; // @[IBuf.scala:44:47] wire _nBufValid_T; // @[package.scala:218:33] assign _nBufValid_T = _T; // @[package.scala:218:33] wire _io_imem_ready_T_1 = io_inst_0_ready_0 & _io_imem_ready_T; // @[IBuf.scala:21:7, :44:{37,47}] wire _io_imem_ready_T_2 = nICReady >= nIC; // @[IBuf.scala:41:86, :42:25, :44:73] wire [2:0] _GEN_3 = {1'h0, nICReady}; // @[IBuf.scala:42:25, :44:94] wire [2:0] _T_4 = {1'h0, nIC} - _GEN_3; // @[IBuf.scala:41:86, :44:94] wire [2:0] _io_imem_ready_T_3; // @[IBuf.scala:44:94] assign _io_imem_ready_T_3 = _T_4; // @[IBuf.scala:44:94] wire [2:0] _nBufValid_T_6; // @[IBuf.scala:56:26] assign _nBufValid_T_6 = _T_4; // @[IBuf.scala:44:94, :56:26] wire [1:0] _io_imem_ready_T_4 = _io_imem_ready_T_3[1:0]; // @[IBuf.scala:44:94] wire _io_imem_ready_T_5 = ~(_io_imem_ready_T_4[1]); // @[IBuf.scala:44:{87,94}] wire _io_imem_ready_T_6 = _io_imem_ready_T_2 | _io_imem_ready_T_5; // @[IBuf.scala:44:{73,80,87}] assign _io_imem_ready_T_7 = _io_imem_ready_T_1 & _io_imem_ready_T_6; // @[IBuf.scala:44:{37,60,80}] assign io_imem_ready_0 = _io_imem_ready_T_7; // @[IBuf.scala:21:7, :44:60] wire _nBufValid_T_1 = ~nBufValid; // @[package.scala:218:43] wire _nBufValid_T_2 = _nBufValid_T | _nBufValid_T_1; // @[package.scala:218:{33,38,43}] wire [2:0] _nBufValid_T_3 = _GEN_1 - _GEN_0; // @[IBuf.scala:42:25, :48:61] wire [1:0] _nBufValid_T_4 = _nBufValid_T_3[1:0]; // @[IBuf.scala:48:61] wire [1:0] _nBufValid_T_5 = _nBufValid_T_2 ? 2'h0 : _nBufValid_T_4; // @[package.scala:218:38] wire [2:0] _shamt_T = _GEN + _GEN_3; // @[IBuf.scala:41:86, :44:94, :55:32] wire [1:0] shamt = _shamt_T[1:0]; // @[IBuf.scala:55:32] wire [1:0] _nBufValid_T_7 = _nBufValid_T_6[1:0]; // @[IBuf.scala:56:26] wire [15:0] _buf_data_data_T = io_imem_bits_data_0[31:16]; // @[IBuf.scala:21:7, :127:58] wire [31:0] _buf_data_data_T_1 = {2{_buf_data_data_T}}; // @[IBuf.scala:127:{24,58}] wire [63:0] buf_data_data = {_buf_data_data_T_1, io_imem_bits_data_0}; // @[IBuf.scala:21:7, :127:{19,24}] wire [5:0] _buf_data_T = {shamt, 4'h0}; // @[IBuf.scala:55:32, :128:19] wire [63:0] _buf_data_T_1 = buf_data_data >> _buf_data_T; // @[IBuf.scala:127:19, :128:{10,19}] wire [15:0] _buf_data_T_2 = _buf_data_T_1[15:0]; // @[IBuf.scala:58:61, :128:10] wire [39:0] _buf_pc_T_1 = io_imem_bits_pc_0 & 40'hFFFFFFFFFC; // @[IBuf.scala:21:7, :59:35] wire [2:0] _buf_pc_T_2 = {nICReady, 1'h0}; // @[IBuf.scala:42:25, :59:80] wire [40:0] _buf_pc_T_3 = {1'h0, io_imem_bits_pc_0} + {38'h0, _buf_pc_T_2}; // @[IBuf.scala:21:7, :59:{68,80}] wire [39:0] _buf_pc_T_4 = _buf_pc_T_3[39:0]; // @[IBuf.scala:59:68] wire [39:0] _buf_pc_T_5 = _buf_pc_T_4 & 40'h3; // @[IBuf.scala:59:{68,109}] wire [39:0] _buf_pc_T_6 = _buf_pc_T_1 | _buf_pc_T_5; // @[IBuf.scala:59:{35,49,109}] wire [2:0] _icShiftAmt_T = _GEN_1 + 3'h2; // @[IBuf.scala:42:25, :68:34] wire [1:0] _icShiftAmt_T_1 = _icShiftAmt_T[1:0]; // @[IBuf.scala:68:34] wire [2:0] _icShiftAmt_T_2 = {1'h0, _icShiftAmt_T_1} - _GEN; // @[IBuf.scala:41:86, :68:{34,46}] wire [1:0] _icShiftAmt_T_3 = _icShiftAmt_T_2[1:0]; // @[IBuf.scala:68:46] wire [1:0] icShiftAmt = _icShiftAmt_T_3; // @[IBuf.scala:68:{46,59}] wire [15:0] _icData_T = io_imem_bits_data_0[15:0]; // @[IBuf.scala:21:7, :69:87] wire [31:0] _icData_T_1 = {2{_icData_T}}; // @[IBuf.scala:69:{57,87}] wire [63:0] _icData_T_2 = {io_imem_bits_data_0, _icData_T_1}; // @[IBuf.scala:21:7, :69:{33,57}] wire [15:0] _icData_data_T = _icData_T_2[63:48]; // @[IBuf.scala:69:33, :120:58] wire [31:0] _icData_data_T_1 = {2{_icData_data_T}}; // @[IBuf.scala:120:{24,58}] wire [63:0] _icData_data_T_2 = {2{_icData_data_T_1}}; // @[IBuf.scala:120:24] wire [127:0] icData_data = {_icData_data_T_2, _icData_T_2}; // @[IBuf.scala:69:33, :120:{19,24}] wire [5:0] _icData_T_3 = {icShiftAmt, 4'h0}; // @[IBuf.scala:68:59, :121:19] wire [190:0] _icData_T_4 = {63'h0, icData_data} << _icData_T_3; // @[IBuf.scala:120:19, :121:{10,19}] wire [31:0] icData = _icData_T_4[95:64]; // @[package.scala:163:13] wire [4:0] _icMask_T_1 = {nBufValid, 4'h0}; // @[IBuf.scala:34:47, :71:65] wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << _icMask_T_1; // @[IBuf.scala:71:{51,65}] wire [31:0] icMask = _icMask_T_2[31:0]; // @[IBuf.scala:71:{51,92}] wire [31:0] _inst_T = icData & icMask; // @[package.scala:163:13] wire [31:0] _inst_T_1 = ~icMask; // @[IBuf.scala:71:92, :72:43] wire [31:0] _inst_T_2 = buf_data & _inst_T_1; // @[IBuf.scala:35:16, :72:{41,43}] assign inst = _inst_T | _inst_T_2; // @[IBuf.scala:72:{21,30,41}] assign io_inst_0_bits_raw_0 = inst; // @[IBuf.scala:21:7, :72:30] wire [3:0] _valid_T = 4'h1 << nValid; // @[OneHot.scala:58:35] wire [4:0] _valid_T_1 = {1'h0, _valid_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _valid_T_2 = _valid_T_1[3:0]; // @[IBuf.scala:74:33] wire [1:0] valid = _valid_T_2[1:0]; // @[IBuf.scala:74:{33,39}] wire [1:0] _io_inst_0_valid_T = valid; // @[IBuf.scala:74:39, :94:32] wire [1:0] _bufMask_T = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [2:0] _bufMask_T_1 = {1'h0, _bufMask_T} - 3'h1; // @[OneHot.scala:58:35] wire [1:0] bufMask = _bufMask_T_1[1:0]; // @[IBuf.scala:75:37] wire _xcpt_T = bufMask[0]; // @[IBuf.scala:75:37, :76:61] wire xcpt_0_pf_inst = _xcpt_T ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_gf_inst = _xcpt_T ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_ae_inst = _xcpt_T ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] assign _io_inst_0_bits_xcpt0_T_1_pf_inst = xcpt_0_pf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_gf_inst = xcpt_0_gf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_ae_inst = xcpt_0_ae_inst; // @[package.scala:39:76] wire _xcpt_T_1 = bufMask[1]; // @[IBuf.scala:75:37, :76:61] wire xcpt_1_pf_inst = _xcpt_T_1 ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_gf_inst = _xcpt_T_1 ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_ae_inst = _xcpt_T_1 ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire _io_inst_0_bits_xcpt1_T_3_pf_inst = xcpt_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_gf_inst = xcpt_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_ae_inst = xcpt_1_ae_inst; // @[package.scala:39:76] wire [1:0] buf_replay_0 = buf_replay ? bufMask : 2'h0; // @[IBuf.scala:35:16, :75:37, :77:23] wire [1:0] _full_insn_T_5 = buf_replay_0; // @[IBuf.scala:77:23, :93:63] wire [1:0] _ic_replay_T = ~bufMask; // @[IBuf.scala:75:37, :78:65] wire [1:0] _ic_replay_T_1 = valid & _ic_replay_T; // @[IBuf.scala:74:39, :78:{63,65}] wire [1:0] _ic_replay_T_2 = io_imem_bits_replay_0 ? _ic_replay_T_1 : 2'h0; // @[IBuf.scala:21:7, :78:{35,63}] wire [1:0] ic_replay = buf_replay_0 | _ic_replay_T_2; // @[IBuf.scala:77:23, :78:{30,35}] wire [1:0] _replay_T = ic_replay; // @[IBuf.scala:78:30, :92:29]
Generate the Verilog code corresponding to the following Chisel files. File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. */ class ClientMetadata extends Bundle { /** Actual state information stored in this bundle */ val state = UInt(ClientStates.width.W) /** Metadata equality */ def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /** Is the block's data present in this cache */ def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */ private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /** Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). */ private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd || param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /** Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). */ def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /** Does a secondary miss on the block require another Acquire message */ def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /** Metadata change on a returned Grant */ def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /** Determine what state to go to based on Probe param */ private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /** Translate cache control cmds into Probe param */ private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /** Factories for ClientMetadata, including on reset */ object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined || nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined || nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBits*rowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /** Bundle definitions for HellaCache interfaces */ trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /** Base classes for Diplomatic TL2 HellaCaches */ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated */ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /** Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst }
module L1MetadataArray( // @[HellaCache.scala:322:7] input clock, // @[HellaCache.scala:322:7] input reset, // @[HellaCache.scala:322:7] output io_read_ready, // @[HellaCache.scala:324:14] input io_read_valid, // @[HellaCache.scala:324:14] input [3:0] io_read_bits_idx, // @[HellaCache.scala:324:14] input [1:0] io_read_bits_way_en, // @[HellaCache.scala:324:14] input [21:0] io_read_bits_tag, // @[HellaCache.scala:324:14] output io_write_ready, // @[HellaCache.scala:324:14] input io_write_valid, // @[HellaCache.scala:324:14] input [3:0] io_write_bits_idx, // @[HellaCache.scala:324:14] input [1:0] io_write_bits_way_en, // @[HellaCache.scala:324:14] input [21:0] io_write_bits_tag, // @[HellaCache.scala:324:14] input [1:0] io_write_bits_data_coh_state, // @[HellaCache.scala:324:14] input [21:0] io_write_bits_data_tag, // @[HellaCache.scala:324:14] output [1:0] io_resp_0_coh_state, // @[HellaCache.scala:324:14] output [21:0] io_resp_0_tag, // @[HellaCache.scala:324:14] output [1:0] io_resp_1_coh_state, // @[HellaCache.scala:324:14] output [21:0] io_resp_1_tag // @[HellaCache.scala:324:14] ); wire tag_array_MPORT_1_en; // @[Decoupled.scala:51:35] wire [3:0] tag_array_MPORT_addr; // @[HellaCache.scala:342:20] wire [47:0] _tag_array_RW0_rdata; // @[HellaCache.scala:339:30] wire io_read_valid_0 = io_read_valid; // @[HellaCache.scala:322:7] wire [3:0] io_read_bits_idx_0 = io_read_bits_idx; // @[HellaCache.scala:322:7] wire [1:0] io_read_bits_way_en_0 = io_read_bits_way_en; // @[HellaCache.scala:322:7] wire [21:0] io_read_bits_tag_0 = io_read_bits_tag; // @[HellaCache.scala:322:7] wire io_write_valid_0 = io_write_valid; // @[HellaCache.scala:322:7] wire [3:0] io_write_bits_idx_0 = io_write_bits_idx; // @[HellaCache.scala:322:7] wire [1:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[HellaCache.scala:322:7] wire [21:0] io_write_bits_tag_0 = io_write_bits_tag; // @[HellaCache.scala:322:7] wire [1:0] io_write_bits_data_coh_state_0 = io_write_bits_data_coh_state; // @[HellaCache.scala:322:7] wire [21:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[HellaCache.scala:322:7] wire [1:0] rstVal_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] rstVal_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [21:0] rstVal_tag = 22'h0; // @[HellaCache.scala:305:20] wire _io_read_ready_T; // @[HellaCache.scala:346:20] wire [1:0] _rmask_T_1 = io_read_bits_way_en_0; // @[HellaCache.scala:322:7, :335:70] wire _io_write_ready_T; // @[HellaCache.scala:347:21] wire [1:0] _wmask_T_1 = io_write_bits_way_en_0; // @[HellaCache.scala:322:7, :334:71] wire io_read_ready_0; // @[HellaCache.scala:322:7] wire io_write_ready_0; // @[HellaCache.scala:322:7] wire [1:0] io_resp_0_coh_state_0; // @[HellaCache.scala:322:7] wire [21:0] io_resp_0_tag_0; // @[HellaCache.scala:322:7] wire [1:0] io_resp_1_coh_state_0; // @[HellaCache.scala:322:7] wire [21:0] io_resp_1_tag_0; // @[HellaCache.scala:322:7] reg [4:0] rst_cnt; // @[HellaCache.scala:330:24] wire rst = ~(rst_cnt[4]); // @[HellaCache.scala:330:24, :331:21] wire _wmask_T = rst; // @[HellaCache.scala:331:21, :334:23] wire _rmask_T = rst; // @[HellaCache.scala:331:21, :335:23] wire [4:0] waddr = rst ? rst_cnt : {1'h0, io_write_bits_idx_0}; // @[HellaCache.scala:322:7, :330:24, :331:21, :332:18] wire [1:0] _wdata_T_coh_state = rst ? 2'h0 : io_write_bits_data_coh_state_0; // @[HellaCache.scala:322:7, :331:21, :333:18] wire [21:0] _wdata_T_tag = rst ? 22'h0 : io_write_bits_data_tag_0; // @[HellaCache.scala:322:7, :331:21, :333:18] wire [23:0] wdata = {_wdata_T_coh_state, _wdata_T_tag}; // @[HellaCache.scala:333:{18,52}] wire [1:0] _wmask_T_2 = _wmask_T ? 2'h3 : _wmask_T_1; // @[HellaCache.scala:334:{18,23,71}] wire wmask_0 = _wmask_T_2[0]; // @[HellaCache.scala:334:{18,79}] wire wmask_1 = _wmask_T_2[1]; // @[HellaCache.scala:334:{18,79}] wire [1:0] _rmask_T_2 = _rmask_T ? 2'h3 : _rmask_T_1; // @[HellaCache.scala:335:{18,23,70}] wire rmask_0 = _rmask_T_2[0]; // @[HellaCache.scala:335:{18,78}] wire rmask_1 = _rmask_T_2[1]; // @[HellaCache.scala:335:{18,78}] wire [5:0] _rst_cnt_T = {1'h0, rst_cnt} + 6'h1; // @[HellaCache.scala:330:24, :332:18, :336:34] wire [4:0] _rst_cnt_T_1 = _rst_cnt_T[4:0]; // @[HellaCache.scala:336:34] wire wen; // @[HellaCache.scala:340:17] assign wen = rst | io_write_valid_0; // @[HellaCache.scala:322:7, :331:21, :340:17] assign tag_array_MPORT_addr = waddr[3:0]; // @[HellaCache.scala:332:18, :342:20] assign tag_array_MPORT_1_en = io_read_ready_0 & io_read_valid_0; // @[Decoupled.scala:51:35] assign io_resp_0_tag_0 = _tag_array_RW0_rdata[21:0]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign io_resp_0_coh_state_0 = _tag_array_RW0_rdata[23:22]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign io_resp_1_tag_0 = _tag_array_RW0_rdata[45:24]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign io_resp_1_coh_state_0 = _tag_array_RW0_rdata[47:46]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign _io_read_ready_T = ~wen; // @[HellaCache.scala:340:17, :346:20] assign io_read_ready_0 = _io_read_ready_T; // @[HellaCache.scala:322:7, :346:20] assign _io_write_ready_T = ~rst; // @[HellaCache.scala:331:21, :347:21] assign io_write_ready_0 = _io_write_ready_T; // @[HellaCache.scala:322:7, :347:21] always @(posedge clock) begin // @[HellaCache.scala:322:7] if (reset) // @[HellaCache.scala:322:7] rst_cnt <= 5'h0; // @[HellaCache.scala:330:24] else if (rst) // @[HellaCache.scala:331:21] rst_cnt <= _rst_cnt_T_1; // @[HellaCache.scala:330:24, :336:34] always @(posedge) tag_array tag_array ( // @[HellaCache.scala:339:30] .RW0_addr (wen ? tag_array_MPORT_addr : io_read_bits_idx_0), // @[HellaCache.scala:322:7, :339:30, :340:17, :342:20] .RW0_en (tag_array_MPORT_1_en | wen), // @[Decoupled.scala:51:35] .RW0_clk (clock), .RW0_wmode (wen), // @[HellaCache.scala:340:17] .RW0_wdata ({2{wdata}}), // @[HellaCache.scala:333:52, :339:30] .RW0_rdata (_tag_array_RW0_rdata), .RW0_wmask ({wmask_1, wmask_0}) // @[HellaCache.scala:334:79, :339:30] ); // @[HellaCache.scala:339:30] assign io_read_ready = io_read_ready_0; // @[HellaCache.scala:322:7] assign io_write_ready = io_write_ready_0; // @[HellaCache.scala:322:7] assign io_resp_0_coh_state = io_resp_0_coh_state_0; // @[HellaCache.scala:322:7] assign io_resp_0_tag = io_resp_0_tag_0; // @[HellaCache.scala:322:7] assign io_resp_1_coh_state = io_resp_1_coh_state_0; // @[HellaCache.scala:322:7] assign io_resp_1_tag = io_resp_1_tag_0; // @[HellaCache.scala:322:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_507( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_251 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File HasTiles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering} import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} import freechips.rocketchip.tilelink.TLWidthWidget import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing} import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap /** Entry point for Config-uring the presence of Tiles */ case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil) /** List of HierarchicalLocations which might contain a Tile */ case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) /** For determining static tile id */ case object NumTiles extends Field[Int](0) /** Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * * These are typically only desirable when a dynamically programmable prefix is being combined * with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]]. */ case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false) /** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block, * and if so, what their width should be. */ case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None) /** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block. * * Unlike the hart ids, the reset vector width is determined by the sinks within the tiles, * based on the size of the address map visible to the tiles. */ case object HasTilesExternalResetVectorKey extends Field[Boolean](true) /** These are sources of "constants" that are driven into the tile. * * While they are not expected to change dyanmically while the tile is executing code, * they may be either tied to a contant value or programmed during boot or reset. * They need to be instantiated before tiles are attached within the subsystem containing them. */ trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements => /** tileHartIdNode is used to collect publishers and subscribers of hartids. */ val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes. * * Each "prefix" input is actually the same full width as the outer hart id; the expected usage * is that each prefix source would set only some non-overlapping portion of the bits to non-zero values. * This node orReduces them, and further combines the reduction with the static ids assigned to each tile, * producing a unique, dynamic hart id for each tile. * * If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered. * * The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into * the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous. */ val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below shouldBeInlined = false // can't inline something whose output we are are dontTouching )).node // TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs /** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */ val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */ val tileResetVectorNexusNode = BundleBroadcast[UInt]( inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below ) /** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids. * * Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile. */ val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match { case Some(w) => (0 until nTotalTiles).map { i => val hartIdSource = BundleBridgeSource(() => UInt(w.W)) tileHartIdNodes(i) := hartIdSource hartIdSource } case None => { (0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode } Nil } } /** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors. * * Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile. */ val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match { case true => (0 until nTotalTiles).map { i => val resetVectorSource = BundleBridgeSource[UInt]() tileResetVectorNodes(i) := resetVectorSource resetVectorSource } case false => { (0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode } Nil } } } /** These are sinks of notifications that are driven out from the tile. * * They need to be instantiated before tiles are attached to the subsystem containing them. */ trait HasTileNotificationSinks { this: LazyModule => val tileHaltXbarNode = IntXbar() val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple()) tileHaltSinkNode := tileHaltXbarNode val tileWFIXbarNode = IntXbar() val tileWFISinkNode = IntSinkNode(IntSinkPortSimple()) tileWFISinkNode := tileWFIXbarNode val tileCeaseXbarNode = IntXbar() val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple()) tileCeaseSinkNode := tileCeaseXbarNode } /** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources. * * Sub-classes of this trait can optionally override the individual connect functions in order to specialize * their attachment behaviors, but most use cases should be be handled simply by changing the implementation * of the injectNode functions in crossingParams. */ trait CanAttachTile { type TileType <: BaseTile type TileContextType <: DefaultHierarchicalElementContextType def tileParams: InstantiableTileParams[TileType] def crossingParams: HierarchicalElementCrossingParamsLike /** Narrow waist through which all tiles are intended to pass while being instantiated. */ def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }) tile_prci_domain } /** A default set of connections that need to occur for most tile types */ def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) } /** Connect the port where the tile is the master to a TileLink interconnect. */ def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p val dataBus = context.locateTLBusWrapper(crossingParams.master.where) dataBus.coupleFrom(tileParams.baseName) { bus => bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) } } /** Connect the port where the tile is the slave to a TileLink interconnect. */ def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) controlBus.coupleTo(tileParams.baseName) { bus => domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus } } } /** Connect the various interrupts sent to and and raised by the tile. */ def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p // NOTE: The order of calls to := matters! They must match how interrupts // are decoded from tile.intInwardNode inside the tile. For this reason, // we stub out missing interrupts with constant sources here. // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" context.msipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.msipNodes(domain.element.tileId) } // From PLIC: "meip" context.meipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.meipNodes(domain.element.tileId) } // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { context.seipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.seipNodes(domain.element.tileId) } } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. // (they are connected to domain.element.intInwardNode in a seperate trait) // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) } }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */ def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p domain { context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode) context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode) context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode) } // TODO should context be forced to have a trace sink connected here? // for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally } /** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */ def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } /** Connect power/reset/clock resources. */ def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) (crossingParams.crossingType match { case _: SynchronousCrossing | _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { domain.clockNode := tlBusToGetClockDriverFrom.clockNode } else { domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode } case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode case _: AsynchronousCrossing => { val tileClockGroup = ClockGroup() tileClockGroup := context.allClockGroupsNode domain.clockNode := tileClockGroup } }) domain { domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode } } /** Function to handle all trace crossings when tile is instantiated inside domains */ def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode } } case class CloneTileAttachParams( sourceTileId: Int, cloneParams: CanAttachTile ) extends CanAttachTile { type TileType = cloneParams.TileType type TileContextType = cloneParams.TileContextType def tileParams = cloneParams.tileParams def crossingParams = cloneParams.crossingParams override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { require(instantiatedTiles.contains(sourceTileId)) val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = CloneLazyModule( new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }, instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]] ) tile_prci_domain } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module TilePRCIDomain( // @[ClockDomain.scala:14:9] input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [255:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_wdata, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_priv, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_exception, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_tval, // @[LazyModuleImp.scala:107:25] output [255:0] auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_wdata, // @[LazyModuleImp.scala:107:25] output [63:0] auto_element_reset_domain_shuttle_tile_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input auto_element_reset_domain_shuttle_tile_hartid_in, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_reset, // @[LazyModuleImp.scala:107:25] output clock, // @[ClockDomain.scala:21:19] output reset // @[ClockDomain.scala:22:19] ); wire _intsink_3_auto_out_0; // @[Crossing.scala:109:29] wire _intsink_2_auto_out_0; // @[Crossing.scala:109:29] wire _intsink_1_auto_out_0; // @[Crossing.scala:109:29] wire _intsink_1_auto_out_1; // @[Crossing.scala:109:29] wire _intsink_auto_out_0; // @[Crossing.scala:86:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_b_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_b_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_b_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_b_bits_size; // @[Buffer.scala:75:28] wire [5:0] _buffer_auto_in_b_bits_source; // @[Buffer.scala:75:28] wire [31:0] _buffer_auto_in_b_bits_address; // @[Buffer.scala:75:28] wire [15:0] _buffer_auto_in_b_bits_mask; // @[Buffer.scala:75:28] wire [127:0] _buffer_auto_in_b_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_in_c_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [5:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [127:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_in_e_ready; // @[Buffer.scala:75:28] wire _element_reset_domain_shuttle_tile_auto_buffer_out_a_valid; // @[HasTiles.scala:164:59] wire [2:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_opcode; // @[HasTiles.scala:164:59] wire [2:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_param; // @[HasTiles.scala:164:59] wire [3:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_size; // @[HasTiles.scala:164:59] wire [5:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_source; // @[HasTiles.scala:164:59] wire [31:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_address; // @[HasTiles.scala:164:59] wire [15:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_mask; // @[HasTiles.scala:164:59] wire [127:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_data; // @[HasTiles.scala:164:59] wire _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_corrupt; // @[HasTiles.scala:164:59] wire _element_reset_domain_shuttle_tile_auto_buffer_out_b_ready; // @[HasTiles.scala:164:59] wire _element_reset_domain_shuttle_tile_auto_buffer_out_c_valid; // @[HasTiles.scala:164:59] wire [2:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_opcode; // @[HasTiles.scala:164:59] wire [2:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_param; // @[HasTiles.scala:164:59] wire [3:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_size; // @[HasTiles.scala:164:59] wire [5:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_source; // @[HasTiles.scala:164:59] wire [31:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_address; // @[HasTiles.scala:164:59] wire [127:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_data; // @[HasTiles.scala:164:59] wire _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_corrupt; // @[HasTiles.scala:164:59] wire _element_reset_domain_shuttle_tile_auto_buffer_out_d_ready; // @[HasTiles.scala:164:59] wire _element_reset_domain_shuttle_tile_auto_buffer_out_e_valid; // @[HasTiles.scala:164:59] wire [3:0] _element_reset_domain_shuttle_tile_auto_buffer_out_e_bits_sink; // @[HasTiles.scala:164:59] ShuttleTile element_reset_domain_shuttle_tile ( // @[HasTiles.scala:164:59] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_buffer_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_buffer_out_a_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_data), .auto_buffer_out_a_bits_corrupt (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_corrupt), .auto_buffer_out_b_ready (_element_reset_domain_shuttle_tile_auto_buffer_out_b_ready), .auto_buffer_out_b_valid (_buffer_auto_in_b_valid), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_opcode (_buffer_auto_in_b_bits_opcode), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_param (_buffer_auto_in_b_bits_param), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_size (_buffer_auto_in_b_bits_size), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_source (_buffer_auto_in_b_bits_source), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_address (_buffer_auto_in_b_bits_address), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_mask (_buffer_auto_in_b_bits_mask), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_data (_buffer_auto_in_b_bits_data), // @[Buffer.scala:75:28] .auto_buffer_out_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), // @[Buffer.scala:75:28] .auto_buffer_out_c_ready (_buffer_auto_in_c_ready), // @[Buffer.scala:75:28] .auto_buffer_out_c_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_c_valid), .auto_buffer_out_c_bits_opcode (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_opcode), .auto_buffer_out_c_bits_param (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_param), .auto_buffer_out_c_bits_size (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_size), .auto_buffer_out_c_bits_source (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_source), .auto_buffer_out_c_bits_address (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_address), .auto_buffer_out_c_bits_data (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_data), .auto_buffer_out_c_bits_corrupt (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_corrupt), .auto_buffer_out_d_ready (_element_reset_domain_shuttle_tile_auto_buffer_out_d_ready), .auto_buffer_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_buffer_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28] .auto_buffer_out_e_ready (_buffer_auto_in_e_ready), // @[Buffer.scala:75:28] .auto_buffer_out_e_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_e_valid), .auto_buffer_out_e_bits_sink (_element_reset_domain_shuttle_tile_auto_buffer_out_e_bits_sink), .auto_int_local_in_3_0 (_intsink_3_auto_out_0), // @[Crossing.scala:109:29] .auto_int_local_in_2_0 (_intsink_2_auto_out_0), // @[Crossing.scala:109:29] .auto_int_local_in_1_0 (_intsink_1_auto_out_0), // @[Crossing.scala:109:29] .auto_int_local_in_1_1 (_intsink_1_auto_out_1), // @[Crossing.scala:109:29] .auto_int_local_in_0_0 (_intsink_auto_out_0), // @[Crossing.scala:86:29] .auto_trace_source_out_insns_0_valid (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_valid), .auto_trace_source_out_insns_0_iaddr (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_iaddr), .auto_trace_source_out_insns_0_insn (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_insn), .auto_trace_source_out_insns_0_priv (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_priv), .auto_trace_source_out_insns_0_exception (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_exception), .auto_trace_source_out_insns_0_interrupt (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_interrupt), .auto_trace_source_out_insns_0_cause (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_cause), .auto_trace_source_out_insns_0_tval (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_tval), .auto_trace_source_out_insns_0_wdata (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_wdata), .auto_trace_source_out_insns_1_valid (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_valid), .auto_trace_source_out_insns_1_iaddr (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_iaddr), .auto_trace_source_out_insns_1_insn (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_insn), .auto_trace_source_out_insns_1_priv (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_priv), .auto_trace_source_out_insns_1_exception (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_exception), .auto_trace_source_out_insns_1_interrupt (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_interrupt), .auto_trace_source_out_insns_1_cause (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_cause), .auto_trace_source_out_insns_1_tval (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_tval), .auto_trace_source_out_insns_1_wdata (auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_wdata), .auto_trace_source_out_time (auto_element_reset_domain_shuttle_tile_trace_source_out_time), .auto_hartid_in (auto_element_reset_domain_shuttle_tile_hartid_in) ); // @[HasTiles.scala:164:59] TLBuffer_a32d128s6k4z4c_2 buffer ( // @[Buffer.scala:75:28] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_a_valid), // @[HasTiles.scala:164:59] .auto_in_a_bits_opcode (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_opcode), // @[HasTiles.scala:164:59] .auto_in_a_bits_param (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_param), // @[HasTiles.scala:164:59] .auto_in_a_bits_size (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_size), // @[HasTiles.scala:164:59] .auto_in_a_bits_source (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_source), // @[HasTiles.scala:164:59] .auto_in_a_bits_address (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_address), // @[HasTiles.scala:164:59] .auto_in_a_bits_mask (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_mask), // @[HasTiles.scala:164:59] .auto_in_a_bits_data (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_data), // @[HasTiles.scala:164:59] .auto_in_a_bits_corrupt (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_corrupt), // @[HasTiles.scala:164:59] .auto_in_b_ready (_element_reset_domain_shuttle_tile_auto_buffer_out_b_ready), // @[HasTiles.scala:164:59] .auto_in_b_valid (_buffer_auto_in_b_valid), .auto_in_b_bits_opcode (_buffer_auto_in_b_bits_opcode), .auto_in_b_bits_param (_buffer_auto_in_b_bits_param), .auto_in_b_bits_size (_buffer_auto_in_b_bits_size), .auto_in_b_bits_source (_buffer_auto_in_b_bits_source), .auto_in_b_bits_address (_buffer_auto_in_b_bits_address), .auto_in_b_bits_mask (_buffer_auto_in_b_bits_mask), .auto_in_b_bits_data (_buffer_auto_in_b_bits_data), .auto_in_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), .auto_in_c_ready (_buffer_auto_in_c_ready), .auto_in_c_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_c_valid), // @[HasTiles.scala:164:59] .auto_in_c_bits_opcode (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_opcode), // @[HasTiles.scala:164:59] .auto_in_c_bits_param (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_param), // @[HasTiles.scala:164:59] .auto_in_c_bits_size (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_size), // @[HasTiles.scala:164:59] .auto_in_c_bits_source (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_source), // @[HasTiles.scala:164:59] .auto_in_c_bits_address (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_address), // @[HasTiles.scala:164:59] .auto_in_c_bits_data (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_data), // @[HasTiles.scala:164:59] .auto_in_c_bits_corrupt (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_corrupt), // @[HasTiles.scala:164:59] .auto_in_d_ready (_element_reset_domain_shuttle_tile_auto_buffer_out_d_ready), // @[HasTiles.scala:164:59] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_in_e_ready (_buffer_auto_in_e_ready), .auto_in_e_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_e_valid), // @[HasTiles.scala:164:59] .auto_in_e_bits_sink (_element_reset_domain_shuttle_tile_auto_buffer_out_e_bits_sink), // @[HasTiles.scala:164:59] .auto_out_a_ready (auto_tl_master_clock_xing_out_a_ready), .auto_out_a_valid (auto_tl_master_clock_xing_out_a_valid), .auto_out_a_bits_opcode (auto_tl_master_clock_xing_out_a_bits_opcode), .auto_out_a_bits_param (auto_tl_master_clock_xing_out_a_bits_param), .auto_out_a_bits_size (auto_tl_master_clock_xing_out_a_bits_size), .auto_out_a_bits_source (auto_tl_master_clock_xing_out_a_bits_source), .auto_out_a_bits_address (auto_tl_master_clock_xing_out_a_bits_address), .auto_out_a_bits_mask (auto_tl_master_clock_xing_out_a_bits_mask), .auto_out_a_bits_data (auto_tl_master_clock_xing_out_a_bits_data), .auto_out_a_bits_corrupt (auto_tl_master_clock_xing_out_a_bits_corrupt), .auto_out_b_ready (auto_tl_master_clock_xing_out_b_ready), .auto_out_b_valid (auto_tl_master_clock_xing_out_b_valid), .auto_out_b_bits_param (auto_tl_master_clock_xing_out_b_bits_param), .auto_out_b_bits_address (auto_tl_master_clock_xing_out_b_bits_address), .auto_out_c_ready (auto_tl_master_clock_xing_out_c_ready), .auto_out_c_valid (auto_tl_master_clock_xing_out_c_valid), .auto_out_c_bits_opcode (auto_tl_master_clock_xing_out_c_bits_opcode), .auto_out_c_bits_param (auto_tl_master_clock_xing_out_c_bits_param), .auto_out_c_bits_size (auto_tl_master_clock_xing_out_c_bits_size), .auto_out_c_bits_source (auto_tl_master_clock_xing_out_c_bits_source), .auto_out_c_bits_address (auto_tl_master_clock_xing_out_c_bits_address), .auto_out_c_bits_data (auto_tl_master_clock_xing_out_c_bits_data), .auto_out_c_bits_corrupt (auto_tl_master_clock_xing_out_c_bits_corrupt), .auto_out_d_ready (auto_tl_master_clock_xing_out_d_ready), .auto_out_d_valid (auto_tl_master_clock_xing_out_d_valid), .auto_out_d_bits_opcode (auto_tl_master_clock_xing_out_d_bits_opcode), .auto_out_d_bits_param (auto_tl_master_clock_xing_out_d_bits_param), .auto_out_d_bits_size (auto_tl_master_clock_xing_out_d_bits_size), .auto_out_d_bits_source (auto_tl_master_clock_xing_out_d_bits_source), .auto_out_d_bits_sink (auto_tl_master_clock_xing_out_d_bits_sink), .auto_out_d_bits_denied (auto_tl_master_clock_xing_out_d_bits_denied), .auto_out_d_bits_data (auto_tl_master_clock_xing_out_d_bits_data), .auto_out_d_bits_corrupt (auto_tl_master_clock_xing_out_d_bits_corrupt), .auto_out_e_valid (auto_tl_master_clock_xing_out_e_valid), .auto_out_e_bits_sink (auto_tl_master_clock_xing_out_e_bits_sink) ); // @[Buffer.scala:75:28] IntSyncAsyncCrossingSink_n1x1 intsink ( // @[Crossing.scala:86:29] .clock (auto_tap_clock_in_clock), .auto_in_sync_0 (auto_intsink_in_sync_0), .auto_out_0 (_intsink_auto_out_0) ); // @[Crossing.scala:86:29] IntSyncSyncCrossingSink_n1x2 intsink_1 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (auto_int_in_clock_xing_in_0_sync_0), .auto_in_sync_1 (auto_int_in_clock_xing_in_0_sync_1), .auto_out_0 (_intsink_1_auto_out_0), .auto_out_1 (_intsink_1_auto_out_1) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1 intsink_2 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (auto_int_in_clock_xing_in_1_sync_0), .auto_out_0 (_intsink_2_auto_out_0) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1 intsink_3 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (auto_int_in_clock_xing_in_2_sync_0), .auto_out_0 (_intsink_3_auto_out_0) ); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_in_0 (1'h0), // @[Buffer.scala:75:28] .auto_out_sync_0 (/* unused */) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1 intsource_1 ( // @[Crossing.scala:29:31] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_in_0 (1'h0), // @[Buffer.scala:75:28] .auto_out_sync_0 (/* unused */) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1 intsource_2 ( // @[Crossing.scala:29:31] .clock (auto_tap_clock_in_clock), .reset (auto_tap_clock_in_reset), .auto_in_0 (1'h0), // @[Buffer.scala:75:28] .auto_out_sync_0 (/* unused */) ); // @[Crossing.scala:29:31] assign clock = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9] assign reset = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_195( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } }
module Repeater_TLBundleA_a29d64s10k1z3u_1( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [28:0] io_enq_bits_address, // @[Repeater.scala:13:14] input io_enq_bits_user_amba_prot_bufferable, // @[Repeater.scala:13:14] input io_enq_bits_user_amba_prot_modifiable, // @[Repeater.scala:13:14] input io_enq_bits_user_amba_prot_readalloc, // @[Repeater.scala:13:14] input io_enq_bits_user_amba_prot_writealloc, // @[Repeater.scala:13:14] input io_enq_bits_user_amba_prot_privileged, // @[Repeater.scala:13:14] input io_enq_bits_user_amba_prot_secure, // @[Repeater.scala:13:14] input io_enq_bits_user_amba_prot_fetch, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [28:0] io_deq_bits_address, // @[Repeater.scala:13:14] output io_deq_bits_user_amba_prot_bufferable, // @[Repeater.scala:13:14] output io_deq_bits_user_amba_prot_modifiable, // @[Repeater.scala:13:14] output io_deq_bits_user_amba_prot_readalloc, // @[Repeater.scala:13:14] output io_deq_bits_user_amba_prot_writealloc, // @[Repeater.scala:13:14] output io_deq_bits_user_amba_prot_privileged, // @[Repeater.scala:13:14] output io_deq_bits_user_amba_prot_secure, // @[Repeater.scala:13:14] output io_deq_bits_user_amba_prot_fetch, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output [63:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [9:0] saved_source; // @[Repeater.scala:21:18] reg [28:0] saved_address; // @[Repeater.scala:21:18] reg saved_user_amba_prot_bufferable; // @[Repeater.scala:21:18] reg saved_user_amba_prot_modifiable; // @[Repeater.scala:21:18] reg saved_user_amba_prot_readalloc; // @[Repeater.scala:21:18] reg saved_user_amba_prot_writealloc; // @[Repeater.scala:21:18] reg saved_user_amba_prot_privileged; // @[Repeater.scala:21:18] reg saved_user_amba_prot_secure; // @[Repeater.scala:21:18] reg saved_user_amba_prot_fetch; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_user_amba_prot_bufferable <= io_enq_bits_user_amba_prot_bufferable; // @[Repeater.scala:21:18] saved_user_amba_prot_modifiable <= io_enq_bits_user_amba_prot_modifiable; // @[Repeater.scala:21:18] saved_user_amba_prot_readalloc <= io_enq_bits_user_amba_prot_readalloc; // @[Repeater.scala:21:18] saved_user_amba_prot_writealloc <= io_enq_bits_user_amba_prot_writealloc; // @[Repeater.scala:21:18] saved_user_amba_prot_privileged <= io_enq_bits_user_amba_prot_privileged; // @[Repeater.scala:21:18] saved_user_amba_prot_secure <= io_enq_bits_user_amba_prot_secure; // @[Repeater.scala:21:18] saved_user_amba_prot_fetch <= io_enq_bits_user_amba_prot_fetch; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_data <= io_enq_bits_data; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File rawFloatFromIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }
module INToRecFN_i32_e8_s24( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [31:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [32:0] io_out // @[INToRecFN.scala:46:16] ); wire intAsRawFloat_sign = io_signedIn & io_in[31]; // @[rawFloatFromIN.scala:51:{29,34}] wire [31:0] intAsRawFloat_absIn = intAsRawFloat_sign ? 32'h0 - io_in : io_in; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [4:0] intAsRawFloat_adjustedNormDist = intAsRawFloat_absIn[31] ? 5'h0 : intAsRawFloat_absIn[30] ? 5'h1 : intAsRawFloat_absIn[29] ? 5'h2 : intAsRawFloat_absIn[28] ? 5'h3 : intAsRawFloat_absIn[27] ? 5'h4 : intAsRawFloat_absIn[26] ? 5'h5 : intAsRawFloat_absIn[25] ? 5'h6 : intAsRawFloat_absIn[24] ? 5'h7 : intAsRawFloat_absIn[23] ? 5'h8 : intAsRawFloat_absIn[22] ? 5'h9 : intAsRawFloat_absIn[21] ? 5'hA : intAsRawFloat_absIn[20] ? 5'hB : intAsRawFloat_absIn[19] ? 5'hC : intAsRawFloat_absIn[18] ? 5'hD : intAsRawFloat_absIn[17] ? 5'hE : intAsRawFloat_absIn[16] ? 5'hF : intAsRawFloat_absIn[15] ? 5'h10 : intAsRawFloat_absIn[14] ? 5'h11 : intAsRawFloat_absIn[13] ? 5'h12 : intAsRawFloat_absIn[12] ? 5'h13 : intAsRawFloat_absIn[11] ? 5'h14 : intAsRawFloat_absIn[10] ? 5'h15 : intAsRawFloat_absIn[9] ? 5'h16 : intAsRawFloat_absIn[8] ? 5'h17 : intAsRawFloat_absIn[7] ? 5'h18 : intAsRawFloat_absIn[6] ? 5'h19 : intAsRawFloat_absIn[5] ? 5'h1A : intAsRawFloat_absIn[4] ? 5'h1B : intAsRawFloat_absIn[3] ? 5'h1C : intAsRawFloat_absIn[2] ? 5'h1D : {4'hF, ~(intAsRawFloat_absIn[1])}; // @[Mux.scala:50:70] wire [62:0] _intAsRawFloat_sig_T = {31'h0, intAsRawFloat_absIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] RoundAnyRawFNToRecFN_ie6_is32_oe8_os24 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (~(_intAsRawFloat_sig_T[31])), // @[rawFloatFromIN.scala:56:{22,41}, :62:{23,28}] .io_in_sign (intAsRawFloat_sign), // @[rawFloatFromIN.scala:51:29] .io_in_sExp ({3'h2, ~intAsRawFloat_adjustedNormDist}), // @[Mux.scala:50:70] .io_in_sig ({1'h0, _intAsRawFloat_sig_T[31:0]}), // @[rawFloatFromIN.scala:52:31, :56:{22,41}, :65:20] .io_roundingMode (io_roundingMode), .io_out (io_out) ); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_152( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_166 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_34( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [2047:0] _GEN = {2037'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [2047:0] _GEN_2 = {2037'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_140( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module TLXbar_MasterXbar_RocketTile_i2_o1_a32d128s2k4z4c( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_anon_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire [3:0] out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [1:0] in_0_c_bits_source; // @[Xbar.scala:159:18] wire [1:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18] wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire [15:0] auto_anon_in_1_a_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] anonIn_1_a_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] in_1_a_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] portsAOI_filtered_1_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [127:0] auto_anon_in_1_a_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] anonIn_1_a_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] in_1_a_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_1_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_1_c_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] portsAOI_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsCOI_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] _out_0_a_bits_T_4 = 128'h0; // @[Mux.scala:30:73] wire [7:0] beatsAI_1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] beatsBO_0 = 8'h0; // @[Edges.scala:221:14] wire [7:0] beatsCI_decode_1 = 8'h0; // @[Edges.scala:220:59] wire [7:0] beatsCI_1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_1 = 8'h0; // @[Arbiter.scala:82:69] wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_e_bits_sink = 4'h0; // @[Xbar.scala:159:18] wire [3:0] _requestEIO_uncommonBits_T_1 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] requestEIO_uncommonBits_1 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsEOI_filtered_1_0_bits_sink = 4'h0; // @[Xbar.scala:352:24] wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] in_1_b_bits_source = 2'h0; // @[Xbar.scala:159:18] wire [1:0] in_1_c_bits_source = 2'h0; // @[Xbar.scala:159:18] wire [1:0] portsCOI_filtered_1_0_bits_source = 2'h0; // @[Xbar.scala:352:24] wire [1:0] in_1_a_bits_source = 2'h2; // @[Xbar.scala:159:18] wire [1:0] _in_1_a_bits_source_T = 2'h2; // @[Xbar.scala:166:55] wire [1:0] portsAOI_filtered_1_0_bits_source = 2'h2; // @[Xbar.scala:352:24] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [7:0] beatsAI_decode_1 = 8'h3; // @[Edges.scala:220:59] wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [15:0] in_1_b_bits_mask = 16'h0; // @[Xbar.scala:159:18] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_b_ready = auto_anon_in_0_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_c_ready; // @[MixedNode.scala:551:17] wire anonIn_c_valid = auto_anon_in_0_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_e_ready; // @[MixedNode.scala:551:17] wire anonIn_e_valid = auto_anon_in_0_e_valid_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_b_ready; // @[MixedNode.scala:542:17] wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9] wire anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9] wire anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_b_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_b_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_0_b_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_b_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_b_ready = anonIn_b_ready; // @[Xbar.scala:159:18] wire in_0_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_valid_0 = anonIn_b_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_b_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_b_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size; // @[Xbar.scala:74:9] wire _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_0_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address; // @[Xbar.scala:74:9] wire [15:0] in_0_b_bits_mask; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask; // @[Xbar.scala:74:9] wire [127:0] in_0_b_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data; // @[Xbar.scala:74:9] wire in_0_b_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_c_ready_0 = anonIn_c_ready; // @[Xbar.scala:74:9] wire in_0_c_valid = anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_param = anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_c_bits_size = anonIn_c_bits_size; // @[Xbar.scala:159:18] wire _in_0_c_bits_source_T = anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] in_0_c_bits_address = anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_0_c_bits_data = anonIn_c_bits_data; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_e_ready_0 = anonIn_e_ready; // @[Xbar.scala:74:9] wire in_0_e_valid = anonIn_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_0_e_bits_sink = anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_b_ready; // @[Xbar.scala:216:19] assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9] wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19] wire [1:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19] wire [15:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19] wire [127:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19] wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19] wire out_0_c_valid; // @[Xbar.scala:216:19] assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] out_0_c_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] out_0_c_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [3:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19] wire out_0_e_valid; // @[Xbar.scala:216:19] assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9] wire [3:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [1:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_ready = in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_b_valid = in_0_b_valid; // @[Xbar.scala:159:18] wire [2:0] portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_b_bits_opcode = in_0_b_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_b_bits_param = in_0_b_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_b_bits_size = in_0_b_bits_size; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign anonIn_b_bits_address = in_0_b_bits_address; // @[Xbar.scala:159:18] wire [15:0] portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24] assign anonIn_b_bits_mask = in_0_b_bits_mask; // @[Xbar.scala:159:18] wire [127:0] portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_b_bits_data = in_0_b_bits_data; // @[Xbar.scala:159:18] wire portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt; // @[Xbar.scala:159:18] wire portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_c_ready = in_0_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [1:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T = in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [3:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsEOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_e_ready = in_0_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire [3:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire [3:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [1:0] in_0_b_bits_source; // @[Xbar.scala:159:18] wire [1:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [1:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T = in_0_b_bits_source[0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign in_0_c_bits_source = {1'h0, _in_0_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [1:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [15:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [127:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [1:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] wire [15:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19] assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19] assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19] assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19] assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19] assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [1:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24] wire portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19] assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire requestBOI_uncommonBits = _requestBOI_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T = out_0_b_bits_source[1]; // @[Xbar.scala:216:19] wire _requestBOI_T_1 = ~_requestBOI_T; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestBOI_0_0 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54] wire requestBOI_0_1 = out_0_b_bits_source == 2'h2; // @[Xbar.scala:216:19] wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54] wire requestDOI_uncommonBits = _requestDOI_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[1]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = out_0_d_bits_source == 2'h2; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [3:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode = _beatsAI_decode_T_2[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71] wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsBO_decode = _beatsBO_decode_T_2[11:4]; // @[package.scala:243:46] wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19] wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}] wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode = _beatsCI_decode_T_2[11:4]; // @[package.scala:243:46] wire beatsCI_opdata = in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsDO_decode = _beatsDO_decode_T_2[11:4]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [7:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_b_valid = portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_param = portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_size = portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_source = portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_address = portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_data = portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T; // @[Mux.scala:30:73] assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2; // @[Mux.scala:30:73] assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign in_0_c_ready = portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_c_valid = portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_param = portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_size = portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_source = portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_address = portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_data = portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign in_0_e_ready = portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_e_valid = portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] reg [7:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File Tilelink.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLMasterToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2)) a.io.protocol <> io.tilelink.a io.tilelink.b <> b.io.protocol c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol e.io.protocol <> io.tilelink.e io.flits.a <> a.io.flit b.io.flit <> io.flits.b io.flits.c <> c.io.flit d.io.flit <> io.flits.d io.flits.e <> e.io.flit } class TLMasterACDToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val a = Decoupled(new IngressFlit(flitWidth)) val c = Decoupled(new IngressFlit(flitWidth)) val d = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart)) val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart)) val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize)) a.io.protocol <> io.tilelink.a c.io.protocol <> io.tilelink.c io.tilelink.d <> d.io.protocol io.flits.a <> a.io.flit io.flits.c <> c.io.flit d.io.flit <> io.flits.d } class TLMasterBEToNoC( edgeIn: TLEdge, edgesOut: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, slaveToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = Flipped(new TLBundle(wideBundle)) val flits = new Bundle { val b = Flipped(Decoupled(new EgressFlit(flitWidth))) val e = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize)) val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0)) io.tilelink.b <> b.io.protocol e.io.protocol <> io.tilelink.e b.io.flit <> io.flits.b io.flits.e <> e.io.flit } class TLSlaveToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val b = Decoupled(new IngressFlit(flitWidth)) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) io.tilelink.a <> a.io.protocol b.io.protocol <> io.tilelink.b io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d io.tilelink.e <> e.io.protocol a.io.flit <> io.flits.a io.flits.b <> b.io.flit c.io.flit <> io.flits.c io.flits.d <> d.io.flit e.io.flit <> io.flits.e } class TLSlaveACDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val a = Flipped(Decoupled(new EgressFlit(flitWidth))) val c = Flipped(Decoupled(new EgressFlit(flitWidth))) val d = Decoupled(new IngressFlit(flitWidth)) } }) io.tilelink := DontCare val a = Module(new TLAFromNoC(edgeOut, wideBundle)) val c = Module(new TLCFromNoC(edgeOut, wideBundle)) val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart)) io.tilelink.a <> a.io.protocol io.tilelink.c <> c.io.protocol d.io.protocol <> io.tilelink.d a.io.flit <> io.flits.a c.io.flit <> io.flits.c io.flits.d <> d.io.flit } class TLSlaveBEToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], sourceStart: Int, sourceSize: Int, wideBundle: TLBundleParameters, masterToEgressOffset: Int => Int, flitWidth: Int )(implicit p: Parameters) extends Module { val io = IO(new Bundle { val tilelink = new TLBundle(wideBundle) val flits = new Bundle { val b = Decoupled(new IngressFlit(flitWidth)) val e = Flipped(Decoupled(new EgressFlit(flitWidth))) } }) io.tilelink := DontCare val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0)) val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize)) b.io.protocol <> io.tilelink.b io.tilelink.e <> e.io.protocol io.flits.b <> b.io.flit e.io.flit <> io.flits.e } class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle { val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) }) val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) }) } trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper { def edgesIn: Seq[TLEdge] def edgesOut: Seq[TLEdge] def edgeInNodes: Seq[Int] def edgeOutNodes: Seq[Int] require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size) def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle)) def genBundle = new TLBundle(wideBundle) def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut) } object TLConnect { def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = { l.valid := r.valid r.ready := l.ready l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll } } // BEGIN: TileLinkProtocolParams case class TileLinkABCDEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int] ) extends TileLinkProtocolParams { // END: TileLinkProtocolParams val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten val nVirtualNetworks = 5 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { edgesIn.zipWithIndex.map { case (e,i) => val nif_master = Module(new TLMasterToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 3 + edgesIn.size * 2 + egressOffset, minPayloadWidth )) nif_master.io.tilelink := DontCare nif_master.io.tilelink.a.valid := false.B nif_master.io.tilelink.c.valid := false.B nif_master.io.tilelink.e.valid := false.B TLConnect(nif_master.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master.io.tilelink.b) TLConnect(nif_master.io.tilelink.c, protocol.in(i).c) TLConnect(nif_master.io.tilelink.e, protocol.in(i).e) } ingresses(i * 3 + 0).flit <> nif_master.io.flits.a ingresses(i * 3 + 1).flit <> nif_master.io.flits.c ingresses(i * 3 + 2).flit <> nif_master.io.flits.e nif_master.io.flits.b <> egresses(i * 2 + 0).flit nif_master.io.flits.d <> egresses(i * 2 + 1).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave = Module(new TLSlaveToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 2 + egressOffset, minPayloadWidth )) nif_slave.io.tilelink := DontCare nif_slave.io.tilelink.b.valid := false.B nif_slave.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a) TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b) TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c) TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e) } ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit } } } } } case class TileLinkACDProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten val nVirtualNetworks = 3 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_acd = Module(new TLMasterACDToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 2 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_acd.io.tilelink := DontCare nif_master_acd.io.tilelink.a.valid := false.B nif_master_acd.io.tilelink.c.valid := false.B nif_master_acd.io.tilelink.e.valid := false.B TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a) TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d) if (protocol.in(i).params.hasBCE) { TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c) } ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_acd = Module(new TLSlaveACDToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_acd.io.tilelink := DontCare nif_slave_acd.io.tilelink.b.valid := false.B nif_slave_acd.io.tilelink.d.valid := false.B TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a) TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d) if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c) } ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit } }} } } case class TileLinkBEProtocolParams( edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge], edgeInNodes: Seq[Int], edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams { val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits)) val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten val nVirtualNetworks = 2 val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) => val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED) val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E }}.flatten.flatten def interface(terminals: NoCTerminalIO, ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = { val ingresses = terminals.ingress val egresses = terminals.egress protocol match { case protocol: TileLinkInterconnectInterface => { protocol := DontCare edgesIn.zipWithIndex.map { case (e,i) => val nif_master_be = Module(new TLMasterBEToNoC( e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size, wideBundle, (s) => s * 1 + edgesIn.size * 1 + egressOffset, minPayloadWidth )) nif_master_be.io.tilelink := DontCare nif_master_be.io.tilelink.a.valid := false.B nif_master_be.io.tilelink.c.valid := false.B nif_master_be.io.tilelink.e.valid := false.B if (protocol.in(i).params.hasBCE) { TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b) TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e) } ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit } edgesOut.zipWithIndex.map { case (e,i) => val nif_slave_be = Module(new TLSlaveBEToNoC( e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size, wideBundle, (s) => s * 1 + egressOffset, minPayloadWidth )) nif_slave_be.io.tilelink := DontCare nif_slave_be.io.tilelink.b.valid := false.B nif_slave_be.io.tilelink.d.valid := false.B if (protocol.out(i).params.hasBCE) { TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e) TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b) } ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit } }} } } abstract class TLNoCLike(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers port.managers map { manager => manager.v1copy(fifoId = None) } } ) } ) } abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) { val edgesIn: Seq[TLEdge] val edgesOut: Seq[TLEdge] val nodeMapping: DiplomaticNetworkNodeMapping val nocName: String lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name))) lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name))) lazy val edgeInNodes = nodeMapping.getNodesIn(inNames) lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames) def printNodeMappings() { println(s"Constellation: TLNoC $nocName inwards mapping:") for ((n, i) <- inNames zip edgeInNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } println(s"Constellation: TLNoC $nocName outwards mapping:") for ((n, i) <- outNames zip edgeOutNodes) { val node = i.map(_.toString).getOrElse("X") println(s" $node <- $n") } } } trait TLNoCParams // Instantiates a private TLNoC. Replaces the TLXbar // BEGIN: TLNoCParams case class SimpleTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, nocParams: NoCParams = NoCParams(), ) extends TLNoCParams class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { // END: TLNoCParams override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val noc = Module(new ProtocolNoC(ProtocolNoCParams( params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC), Seq(protocolParams), inlineNoC = inlineNoC ))) noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } } case class SplitACDxBETLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping, acdNoCParams: NoCParams = NoCParams(), beNoCParams: NoCParams = NoCParams(), beDivision: Int = 2 ) extends TLNoCParams class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike { override def shouldBeInlined = inlineNoC lazy val module = new TLNoCModuleImp(this) { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name printNodeMappings() val acdProtocolParams = TileLinkACDProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val beProtocolParams = TileLinkBEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC), Seq(acdProtocolParams), inlineNoC = inlineNoC ))) val be_noc = Module(new ProtocolNoC(ProtocolNoCParams( params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC), Seq(beProtocolParams), widthDivision = params.beDivision, inlineNoC = inlineNoC ))) acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.a <> r.a l.c <> r.c l.d <> r.d } }} be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l := DontCare l.b <> r.b l.e <> r.e } (io_out zip protocol.out).foreach { case (l,r) => r := DontCare l.b <> r.b l.e <> r.e } }} } } case class GlobalTLNoCParams( nodeMappings: DiplomaticNetworkNodeMapping ) extends TLNoCParams // Maps this interconnect onto a global NoC class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike { lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC { val (io_in, edgesIn) = node.in.unzip val (io_out, edgesOut) = node.out.unzip val nodeMapping = params.nodeMappings val nocName = name val protocolParams = TileLinkABCDEProtocolParams( edgesIn = edgesIn, edgesOut = edgesOut, edgeInNodes = edgeInNodes.flatten, edgeOutNodes = edgeOutNodes.flatten ) printNodeMappings() val io_global = IO(Flipped(protocolParams.genIO())) io_global match { case protocol: TileLinkInterconnectInterface => { (protocol.in zip io_in).foreach { case (l,r) => l <> r } (io_out zip protocol.out).foreach { case (l,r) => l <> r } } } } }
module TLMasterToNoC_4( // @[Tilelink.scala:37:7] input clock, // @[Tilelink.scala:37:7] input reset, // @[Tilelink.scala:37:7] output io_tilelink_a_ready, // @[Tilelink.scala:44:14] input io_tilelink_a_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_b_ready, // @[Tilelink.scala:44:14] output io_tilelink_b_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:44:14] output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:44:14] output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_c_ready, // @[Tilelink.scala:44:14] input io_tilelink_c_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_d_ready, // @[Tilelink.scala:44:14] output io_tilelink_d_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14] output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_e_ready, // @[Tilelink.scala:44:14] input io_tilelink_e_valid, // @[Tilelink.scala:44:14] input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:44:14] input io_flits_a_ready, // @[Tilelink.scala:44:14] output io_flits_a_valid, // @[Tilelink.scala:44:14] output io_flits_a_bits_head, // @[Tilelink.scala:44:14] output io_flits_a_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_b_ready, // @[Tilelink.scala:44:14] input io_flits_b_valid, // @[Tilelink.scala:44:14] input io_flits_b_bits_head, // @[Tilelink.scala:44:14] input io_flits_b_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:44:14] input io_flits_c_ready, // @[Tilelink.scala:44:14] output io_flits_c_valid, // @[Tilelink.scala:44:14] output io_flits_c_bits_head, // @[Tilelink.scala:44:14] output io_flits_c_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_d_ready, // @[Tilelink.scala:44:14] input io_flits_d_valid, // @[Tilelink.scala:44:14] input io_flits_d_bits_head, // @[Tilelink.scala:44:14] input io_flits_d_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:44:14] input io_flits_e_ready, // @[Tilelink.scala:44:14] output io_flits_e_valid, // @[Tilelink.scala:44:14] output io_flits_e_bits_head, // @[Tilelink.scala:44:14] output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_e_bits_egress_id // @[Tilelink.scala:44:14] ); wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:58:17] wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:56:17] TLAToNoC_4 a ( // @[Tilelink.scala:54:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:54:17] TLBFromNoC_1 b ( // @[Tilelink.scala:55:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_opcode (io_tilelink_b_bits_opcode), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_size (io_tilelink_b_bits_size), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_protocol_bits_mask (io_tilelink_b_bits_mask), .io_protocol_bits_data (io_tilelink_b_bits_data), .io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload) ); // @[Tilelink.scala:55:17] TLCToNoC_4 c ( // @[Tilelink.scala:56:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:56:17] TLDFromNoC_1 d ( // @[Tilelink.scala:57:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14] ); // @[Tilelink.scala:57:17] TLEToNoC e ( // @[Tilelink.scala:58:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_e_ready), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:58:17] assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :56:17, :67:14] assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :58:17, :69:14] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputUnit_8( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_8; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_8; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, vcalloc_vals_7, 1'h0, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, 1'h0, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_0 ? 20'h400 : vcalloc_vals_1 ? 20'h800 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_7 ? 20'h20000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_7 | vcalloc_vals_8 | vcalloc_vals_9; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File Switch.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel.{ChannelParams, IngressChannelParams, EgressChannelParams, Flit} class SwitchBundle(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams{ val flit = new Flit(allOutParams(0).payloadBits) val out_virt_channel = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) } class Switch( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val in = MixedVec(allInParams.map { u => Vec(u.destSpeedup, Input(Valid(new SwitchBundle(outParams, egressParams)))) }) val out = MixedVec(allOutParams.map { u => Vec(u.srcSpeedup, Output(Valid(new Flit(u.payloadBits)))) }) val sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Input(Bool())) })) }) }) val in_flat = Wire(Vec(allInParams.map(_.destSpeedup).reduce(_+_), Valid(new SwitchBundle(outParams, egressParams)))) var idx = 0 io.in.foreach(_.foreach { i => in_flat(idx) := i idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { val sel_flat = io.sel(i)(j).asUInt assert(PopCount(sel_flat) <= 1.U) io.out(i)(j).valid := Mux1H(sel_flat, in_flat.map(_.valid)) && sel_flat =/= 0.U io.out(i)(j).bits := Mux1H(sel_flat, in_flat.map(_.bits.flit)) io.out(i)(j).bits.virt_channel_id := Mux1H(sel_flat, in_flat.map(_.bits.out_virt_channel)) } } }
module Switch( // @[Switch.scala:16:7] input clock, // @[Switch.scala:16:7] input reset, // @[Switch.scala:16:7] input io_in_6_0_valid, // @[Switch.scala:27:14] input io_in_6_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_6_0_bits_flit_tail, // @[Switch.scala:27:14] input [144:0] io_in_6_0_bits_flit_payload, // @[Switch.scala:27:14] input [1:0] io_in_6_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_6_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_6_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_6_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_6_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [1:0] io_in_6_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_5_0_valid, // @[Switch.scala:27:14] input io_in_5_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_5_0_bits_flit_tail, // @[Switch.scala:27:14] input [144:0] io_in_5_0_bits_flit_payload, // @[Switch.scala:27:14] input [1:0] io_in_5_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_5_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_5_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_5_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_5_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [1:0] io_in_5_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_4_0_valid, // @[Switch.scala:27:14] input io_in_4_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_4_0_bits_flit_tail, // @[Switch.scala:27:14] input [144:0] io_in_4_0_bits_flit_payload, // @[Switch.scala:27:14] input [1:0] io_in_4_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_4_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_4_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_4_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_4_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [1:0] io_in_4_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_2_0_valid, // @[Switch.scala:27:14] input io_in_2_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_2_0_bits_flit_tail, // @[Switch.scala:27:14] input [144:0] io_in_2_0_bits_flit_payload, // @[Switch.scala:27:14] input [1:0] io_in_2_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_2_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_2_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_2_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_2_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input [1:0] io_in_2_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_1_0_valid, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14] input [144:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14] input [1:0] io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input io_in_0_0_valid, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14] input [144:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14] input [1:0] io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [2:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] output io_out_5_0_valid, // @[Switch.scala:27:14] output io_out_5_0_bits_head, // @[Switch.scala:27:14] output io_out_5_0_bits_tail, // @[Switch.scala:27:14] output [144:0] io_out_5_0_bits_payload, // @[Switch.scala:27:14] output io_out_4_0_valid, // @[Switch.scala:27:14] output io_out_4_0_bits_head, // @[Switch.scala:27:14] output io_out_4_0_bits_tail, // @[Switch.scala:27:14] output [144:0] io_out_4_0_bits_payload, // @[Switch.scala:27:14] output [3:0] io_out_4_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_4_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output io_out_3_0_valid, // @[Switch.scala:27:14] output io_out_3_0_bits_head, // @[Switch.scala:27:14] output io_out_3_0_bits_tail, // @[Switch.scala:27:14] output [144:0] io_out_3_0_bits_payload, // @[Switch.scala:27:14] output [3:0] io_out_3_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_3_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output io_out_2_0_valid, // @[Switch.scala:27:14] output io_out_2_0_bits_head, // @[Switch.scala:27:14] output io_out_2_0_bits_tail, // @[Switch.scala:27:14] output [144:0] io_out_2_0_bits_payload, // @[Switch.scala:27:14] output [3:0] io_out_2_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_2_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output io_out_1_0_valid, // @[Switch.scala:27:14] output io_out_1_0_bits_head, // @[Switch.scala:27:14] output io_out_1_0_bits_tail, // @[Switch.scala:27:14] output [144:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14] output [1:0] io_out_1_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_1_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_1_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_1_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [1:0] io_out_1_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output [1:0] io_out_1_0_bits_virt_channel_id, // @[Switch.scala:27:14] output io_out_0_0_valid, // @[Switch.scala:27:14] output io_out_0_0_bits_head, // @[Switch.scala:27:14] output io_out_0_0_bits_tail, // @[Switch.scala:27:14] output [144:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14] output [1:0] io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [2:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [1:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output [1:0] io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14] input io_sel_5_0_6_0, // @[Switch.scala:27:14] input io_sel_5_0_5_0, // @[Switch.scala:27:14] input io_sel_5_0_4_0, // @[Switch.scala:27:14] input io_sel_5_0_2_0, // @[Switch.scala:27:14] input io_sel_5_0_1_0, // @[Switch.scala:27:14] input io_sel_5_0_0_0, // @[Switch.scala:27:14] input io_sel_4_0_6_0, // @[Switch.scala:27:14] input io_sel_4_0_5_0, // @[Switch.scala:27:14] input io_sel_4_0_4_0, // @[Switch.scala:27:14] input io_sel_4_0_2_0, // @[Switch.scala:27:14] input io_sel_4_0_1_0, // @[Switch.scala:27:14] input io_sel_4_0_0_0, // @[Switch.scala:27:14] input io_sel_3_0_6_0, // @[Switch.scala:27:14] input io_sel_3_0_5_0, // @[Switch.scala:27:14] input io_sel_3_0_4_0, // @[Switch.scala:27:14] input io_sel_3_0_2_0, // @[Switch.scala:27:14] input io_sel_3_0_1_0, // @[Switch.scala:27:14] input io_sel_3_0_0_0, // @[Switch.scala:27:14] input io_sel_2_0_6_0, // @[Switch.scala:27:14] input io_sel_2_0_5_0, // @[Switch.scala:27:14] input io_sel_2_0_4_0, // @[Switch.scala:27:14] input io_sel_2_0_2_0, // @[Switch.scala:27:14] input io_sel_2_0_1_0, // @[Switch.scala:27:14] input io_sel_2_0_0_0, // @[Switch.scala:27:14] input io_sel_1_0_6_0, // @[Switch.scala:27:14] input io_sel_1_0_5_0, // @[Switch.scala:27:14] input io_sel_1_0_4_0, // @[Switch.scala:27:14] input io_sel_1_0_2_0, // @[Switch.scala:27:14] input io_sel_0_0_6_0, // @[Switch.scala:27:14] input io_sel_0_0_5_0, // @[Switch.scala:27:14] input io_sel_0_0_4_0, // @[Switch.scala:27:14] input io_sel_0_0_2_0 // @[Switch.scala:27:14] );
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_29( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_46 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Control.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ class InclusiveCacheControl(outer: InclusiveCache, control: InclusiveCacheControlParameters)(implicit p: Parameters) extends LazyModule()(p) { val ctrlnode = TLRegisterNode( address = Seq(AddressSet(control.address, InclusiveCacheParameters.L2ControlSize-1)), device = outer.device, concurrency = 1, // Only one flush at a time (else need to track who answers) beatBytes = control.beatBytes) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val flush_match = Input(Bool()) val flush_req = Decoupled(UInt(64.W)) val flush_resp = Input(Bool()) }) // Flush directive val flushInValid = RegInit(false.B) val flushInAddress = Reg(UInt(64.W)) val flushOutValid = RegInit(false.B) val flushOutReady = WireInit(init = false.B) when (flushOutReady) { flushOutValid := false.B } when (io.flush_resp) { flushOutValid := true.B } when (io.flush_req.ready) { flushInValid := false.B } io.flush_req.valid := flushInValid io.flush_req.bits := flushInAddress when (!io.flush_match && flushInValid) { flushInValid := false.B flushOutValid := true.B } val flush32 = RegField.w(32, RegWriteFn((ivalid, oready, data) => { when (oready) { flushOutReady := true.B } when (ivalid) { flushInValid := true.B } when (ivalid && !flushInValid) { flushInAddress := data << 4 } (!flushInValid, flushOutValid) }), RegFieldDesc("Flush32", "Flush the physical address equal to the 32-bit written data << 4 from the cache")) val flush64 = RegField.w(64, RegWriteFn((ivalid, oready, data) => { when (oready) { flushOutReady := true.B } when (ivalid) { flushInValid := true.B } when (ivalid && !flushInValid) { flushInAddress := data } (!flushInValid, flushOutValid) }), RegFieldDesc("Flush64", "Flush the phsyical address equal to the 64-bit written data from the cache")) // Information about the cache configuration val banksR = RegField.r(8, outer.node.edges.in.size.U, RegFieldDesc("Banks", "Number of banks in the cache", reset=Some(outer.node.edges.in.size))) val waysR = RegField.r(8, outer.cache.ways.U, RegFieldDesc("Ways", "Number of ways per bank", reset=Some(outer.cache.ways))) val lgSetsR = RegField.r(8, log2Ceil(outer.cache.sets).U, RegFieldDesc("lgSets", "Base-2 logarithm of the sets per bank", reset=Some(log2Ceil(outer.cache.sets)))) val lgBlockBytesR = RegField.r(8, log2Ceil(outer.cache.blockBytes).U, RegFieldDesc("lgBlockBytes", "Base-2 logarithm of the bytes per cache block", reset=Some(log2Ceil(outer.cache.blockBytes)))) val regmap = ctrlnode.regmap( 0x000 -> RegFieldGroup("Config", Some("Information about the Cache Configuration"), Seq(banksR, waysR, lgSetsR, lgBlockBytesR)), 0x200 -> (if (control.beatBytes >= 8) Seq(flush64) else Nil), 0x240 -> Seq(flush32) ) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module InclusiveCacheControl( // @[Control.scala:38:9] input clock, // @[Control.scala:38:9] input reset, // @[Control.scala:38:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_flush_match, // @[Control.scala:39:16] input io_flush_req_ready, // @[Control.scala:39:16] output io_flush_req_valid, // @[Control.scala:39:16] output [63:0] io_flush_req_bits, // @[Control.scala:39:16] input io_flush_resp // @[Control.scala:39:16] ); wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9] wire [11:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9] wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9] wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9] wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9] wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9] wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801}; wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_14 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h1; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend = 12'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_22 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_23 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = 16'h801; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_1 = 20'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_31 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_32 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [26:0] out_prepend_2 = 27'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_40 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_41 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60A0801; // @[MuxLiteral.scala:49:48] wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9] wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9] wire [11:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9] wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9] wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9] wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9] wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] wire [11:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] wire io_flush_req_valid_0; // @[Control.scala:38:9] wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9] wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9] wire [11:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9] reg flushInValid; // @[Control.scala:45:33] assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33] reg [63:0] flushInAddress; // @[Control.scala:46:29] assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29] reg flushOutValid; // @[Control.scala:47:33] wire flushOutReady; // @[Control.scala:48:34] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23] wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24] wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8] wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24] wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_wiready | _out_T_48; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = flushOutValid | _out_T_51; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24] assign flushOutReady = out_f_woready_5 | out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23] wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24] wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24] wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23] wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24] wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wiready_1 | _out_T_61; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24] wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = flushOutValid | _out_T_64; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = out_wifireMux_out_2 | _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = out_wifireMux_out_3 | _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10] wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = out_wofireMux_out_2 | _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = out_wofireMux_out_3 | _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] wire out_iready = out_front_bits_read | out_wifireMux; // @[MuxLiteral.scala:49:10] wire out_oready = _out_back_front_q_io_deq_bits_read | out_wofireMux; // @[MuxLiteral.scala:49:10] assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}] always @(posedge clock) begin // @[Control.scala:38:9] if (reset) begin // @[Control.scala:38:9] flushInValid <= 1'h0; // @[Control.scala:45:33] flushOutValid <= 1'h0; // @[Control.scala:47:33] end else begin // @[Control.scala:38:9] flushInValid <= out_f_wivalid_5 | out_f_wivalid_4 | ~(_T_1 | io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24] flushOutValid <= _T_1 | io_flush_resp_0 | ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21] end if (_out_T_57) // @[Control.scala:64:20] flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}] else if (_out_T_44) // @[Control.scala:71:20] flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24] always @(posedge) TLMonitor_36 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9] assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File BankedStore.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.DescribedSRAM import scala.math.{max, min} abstract class BankedStoreAddress(val inner: Boolean, params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val noop = Bool() // do not actually use the SRAMs, just block their use val way = UInt(params.wayBits.W) val set = UInt(params.setBits.W) val beat = UInt((if (inner) params.innerBeatBits else params.outerBeatBits).W) val mask = UInt((if (inner) params.innerMaskBits else params.outerMaskBits).W) } trait BankedStoreRW { val write = Bool() } class BankedStoreOuterAddress(params: InclusiveCacheParameters) extends BankedStoreAddress(false, params) class BankedStoreInnerAddress(params: InclusiveCacheParameters) extends BankedStoreAddress(true, params) class BankedStoreInnerAddressRW(params: InclusiveCacheParameters) extends BankedStoreInnerAddress(params) with BankedStoreRW abstract class BankedStoreData(val inner: Boolean, params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(((if (inner) params.inner.manager.beatBytes else params.outer.manager.beatBytes)*8).W) } class BankedStoreOuterData(params: InclusiveCacheParameters) extends BankedStoreData(false, params) class BankedStoreInnerData(params: InclusiveCacheParameters) extends BankedStoreData(true, params) class BankedStoreInnerPoison(params: InclusiveCacheParameters) extends BankedStoreInnerData(params) class BankedStoreOuterPoison(params: InclusiveCacheParameters) extends BankedStoreOuterData(params) class BankedStoreInnerDecoded(params: InclusiveCacheParameters) extends BankedStoreInnerData(params) class BankedStoreOuterDecoded(params: InclusiveCacheParameters) extends BankedStoreOuterData(params) class BankedStore(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val sinkC_adr = Flipped(Decoupled(new BankedStoreInnerAddress(params))) val sinkC_dat = Flipped(new BankedStoreInnerPoison(params)) val sinkD_adr = Flipped(Decoupled(new BankedStoreOuterAddress(params))) val sinkD_dat = Flipped(new BankedStoreOuterPoison(params)) val sourceC_adr = Flipped(Decoupled(new BankedStoreOuterAddress(params))) val sourceC_dat = new BankedStoreOuterDecoded(params) val sourceD_radr = Flipped(Decoupled(new BankedStoreInnerAddress(params))) val sourceD_rdat = new BankedStoreInnerDecoded(params) val sourceD_wadr = Flipped(Decoupled(new BankedStoreInnerAddress(params))) val sourceD_wdat = Flipped(new BankedStoreInnerPoison(params)) }) val innerBytes = params.inner.manager.beatBytes val outerBytes = params.outer.manager.beatBytes val rowBytes = params.micro.portFactor * max(innerBytes, outerBytes) require (rowBytes < params.cache.sizeBytes) val rowEntries = params.cache.sizeBytes / rowBytes val rowBits = log2Ceil(rowEntries) val numBanks = rowBytes / params.micro.writeBytes val codeBits = 8*params.micro.writeBytes val cc_banks = Seq.tabulate(numBanks) { i => DescribedSRAM( name = s"cc_banks_$i", desc = "Banked Store", size = rowEntries, data = UInt(codeBits.W) ) } // These constraints apply on the port priorities: // sourceC > sinkD outgoing Release > incoming Grant (we start eviction+refill concurrently) // sinkC > sourceC incoming ProbeAck > outgoing ProbeAck (we delay probeack writeback by 1 cycle for QoR) // sinkC > sourceDr incoming ProbeAck > SourceD read (we delay probeack writeback by 1 cycle for QoR) // sourceDw > sourceDr modified data visible on next cycle (needed to ensure SourceD forward progress) // sinkC > sourceC inner ProbeAck > outer ProbeAck (make wormhole routing possible [not yet implemented]) // sinkC&D > sourceD* beat arrival > beat read|update (make wormhole routing possible [not yet implemented]) // Combining these restrictions yields a priority scheme of: // sinkC > sourceC > sinkD > sourceDw > sourceDr // ^^^^^^^^^^^^^^^ outer interface // Requests have different port widths, but we don't want to allow cutting in line. // Suppose we have requests A > B > C requesting ports --A-, --BB, ---C. // The correct arbitration is to allow --A- only, not --AC. // Obviously --A-, BB--, ---C should still be resolved to BBAC. class Request extends Bundle { val wen = Bool() val index = UInt(rowBits.W) val bankSel = UInt(numBanks.W) val bankSum = UInt(numBanks.W) // OR of all higher priority bankSels val bankEn = UInt(numBanks.W) // ports actually activated by request val data = Vec(numBanks, UInt(codeBits.W)) } def req[T <: BankedStoreAddress](b: DecoupledIO[T], write: Bool, d: UInt): Request = { val beatBytes = if (b.bits.inner) innerBytes else outerBytes val ports = beatBytes / params.micro.writeBytes val bankBits = log2Ceil(numBanks / ports) val words = Seq.tabulate(ports) { i => val data = d((i + 1) * 8 * params.micro.writeBytes - 1, i * 8 * params.micro.writeBytes) data } val a = if (params.cache.blockBytes == beatBytes) Cat(b.bits.way, b.bits.set) else Cat(b.bits.way, b.bits.set, b.bits.beat) val m = b.bits.mask val out = Wire(new Request) val select = UIntToOH(a(bankBits-1, 0), numBanks/ports) val ready = Cat(Seq.tabulate(numBanks/ports) { i => !(out.bankSum((i+1)*ports-1, i*ports) & m).orR } .reverse) b.ready := ready(a(bankBits-1, 0)) out.wen := write out.index := a >> bankBits out.bankSel := Mux(b.valid, FillInterleaved(ports, select) & Fill(numBanks/ports, m), 0.U) out.bankEn := Mux(b.bits.noop, 0.U, out.bankSel & FillInterleaved(ports, ready)) out.data := Seq.fill(numBanks/ports) { words }.flatten out } val innerData = 0.U((8*innerBytes).W) val outerData = 0.U((8*outerBytes).W) val W = true.B val R = false.B val sinkC_req = req(io.sinkC_adr, W, io.sinkC_dat.data) val sinkD_req = req(io.sinkD_adr, W, io.sinkD_dat.data) val sourceC_req = req(io.sourceC_adr, R, outerData) val sourceD_rreq = req(io.sourceD_radr, R, innerData) val sourceD_wreq = req(io.sourceD_wadr, W, io.sourceD_wdat.data) // See the comments above for why this prioritization is used val reqs = Seq(sinkC_req, sourceC_req, sinkD_req, sourceD_wreq, sourceD_rreq) // Connect priorities; note that even if a request does not go through due to failing // to obtain a needed subbank, it still blocks overlapping lower priority requests. reqs.foldLeft(0.U) { case (sum, req) => req.bankSum := sum req.bankSel | sum } // Access the banks val regout = VecInit(cc_banks.zipWithIndex.map { case (b, i) => val en = reqs.map(_.bankEn(i)).reduce(_||_) val sel = reqs.map(_.bankSel(i)) val wen = PriorityMux(sel, reqs.map(_.wen)) val idx = PriorityMux(sel, reqs.map(_.index)) val data= PriorityMux(sel, reqs.map(_.data(i))) when (wen && en) { b.write(idx, data) } RegEnable(b.read(idx, !wen && en), RegNext(!wen && en)) }) val regsel_sourceC = RegNext(RegNext(sourceC_req.bankEn)) val regsel_sourceD = RegNext(RegNext(sourceD_rreq.bankEn)) val decodeC = regout.zipWithIndex.map { case (r, i) => Mux(regsel_sourceC(i), r, 0.U) }.grouped(outerBytes/params.micro.writeBytes).toList.transpose.map(s => s.reduce(_|_)) io.sourceC_dat.data := Cat(decodeC.reverse) val decodeD = regout.zipWithIndex.map { // Intentionally not Mux1H and/or an indexed-mux b/c we want it 0 when !sel to save decode power case (r, i) => Mux(regsel_sourceD(i), r, 0.U) }.grouped(innerBytes/params.micro.writeBytes).toList.transpose.map(s => s.reduce(_|_)) io.sourceD_rdat.data := Cat(decodeD.reverse) private def banks = cc_banks.map("\"" + _.pathName + "\"").mkString(",") def json: String = s"""{"widthBytes":${params.micro.writeBytes},"mem":[${banks}]}""" } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module BankedStore( // @[BankedStore.scala:59:7] input clock, // @[BankedStore.scala:59:7] input reset, // @[BankedStore.scala:59:7] output io_sinkD_adr_ready, // @[BankedStore.scala:61:14] input io_sinkD_adr_valid, // @[BankedStore.scala:61:14] input io_sinkD_adr_bits_noop, // @[BankedStore.scala:61:14] input [2:0] io_sinkD_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sinkD_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sinkD_adr_bits_beat, // @[BankedStore.scala:61:14] input [63:0] io_sinkD_dat_data, // @[BankedStore.scala:61:14] output io_sourceC_adr_ready, // @[BankedStore.scala:61:14] input io_sourceC_adr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceC_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceC_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sourceC_adr_bits_beat, // @[BankedStore.scala:61:14] output [63:0] io_sourceC_dat_data, // @[BankedStore.scala:61:14] output io_sourceD_radr_ready, // @[BankedStore.scala:61:14] input io_sourceD_radr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_radr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceD_radr_bits_set, // @[BankedStore.scala:61:14] input [3:0] io_sourceD_radr_bits_beat, // @[BankedStore.scala:61:14] input io_sourceD_radr_bits_mask, // @[BankedStore.scala:61:14] output [31:0] io_sourceD_rdat_data, // @[BankedStore.scala:61:14] output io_sourceD_wadr_ready, // @[BankedStore.scala:61:14] input io_sourceD_wadr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_wadr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceD_wadr_bits_set, // @[BankedStore.scala:61:14] input [3:0] io_sourceD_wadr_bits_beat, // @[BankedStore.scala:61:14] input io_sourceD_wadr_bits_mask, // @[BankedStore.scala:61:14] input [31:0] io_sourceD_wdat_data // @[BankedStore.scala:61:14] ); wire [31:0] _cc_banks_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [31:0] _cc_banks_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [31:0] _cc_banks_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [31:0] _cc_banks_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [31:0] _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [31:0] _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [31:0] _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [31:0] _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_sinkD_adr_valid_0 = io_sinkD_adr_valid; // @[BankedStore.scala:59:7] wire io_sinkD_adr_bits_noop_0 = io_sinkD_adr_bits_noop; // @[BankedStore.scala:59:7] wire [2:0] io_sinkD_adr_bits_way_0 = io_sinkD_adr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sinkD_adr_bits_set_0 = io_sinkD_adr_bits_set; // @[BankedStore.scala:59:7] wire [2:0] io_sinkD_adr_bits_beat_0 = io_sinkD_adr_bits_beat; // @[BankedStore.scala:59:7] wire [63:0] io_sinkD_dat_data_0 = io_sinkD_dat_data; // @[BankedStore.scala:59:7] wire io_sourceC_adr_valid_0 = io_sourceC_adr_valid; // @[BankedStore.scala:59:7] wire [2:0] io_sourceC_adr_bits_way_0 = io_sourceC_adr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sourceC_adr_bits_set_0 = io_sourceC_adr_bits_set; // @[BankedStore.scala:59:7] wire [2:0] io_sourceC_adr_bits_beat_0 = io_sourceC_adr_bits_beat; // @[BankedStore.scala:59:7] wire io_sourceD_radr_valid_0 = io_sourceD_radr_valid; // @[BankedStore.scala:59:7] wire [2:0] io_sourceD_radr_bits_way_0 = io_sourceD_radr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sourceD_radr_bits_set_0 = io_sourceD_radr_bits_set; // @[BankedStore.scala:59:7] wire [3:0] io_sourceD_radr_bits_beat_0 = io_sourceD_radr_bits_beat; // @[BankedStore.scala:59:7] wire io_sourceD_radr_bits_mask_0 = io_sourceD_radr_bits_mask; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_valid_0 = io_sourceD_wadr_valid; // @[BankedStore.scala:59:7] wire [2:0] io_sourceD_wadr_bits_way_0 = io_sourceD_wadr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sourceD_wadr_bits_set_0 = io_sourceD_wadr_bits_set; // @[BankedStore.scala:59:7] wire [3:0] io_sourceD_wadr_bits_beat_0 = io_sourceD_wadr_bits_beat; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_bits_mask_0 = io_sourceD_wadr_bits_mask; // @[BankedStore.scala:59:7] wire [31:0] io_sourceD_wdat_data_0 = io_sourceD_wdat_data; // @[BankedStore.scala:59:7] wire [12:0] sinkC_req_a_hi = 13'h0; // @[BankedStore.scala:126:91] wire [16:0] sinkC_req_a = 17'h0; // @[BankedStore.scala:126:91] wire [13:0] sinkC_req_index = 14'h0; // @[BankedStore.scala:128:19, :135:23] wire [13:0] _sinkC_req_out_index_T = 14'h0; // @[BankedStore.scala:128:19, :135:23] wire [1:0] sinkC_req_out_bankSel_lo_lo = 2'h1; // @[BankedStore.scala:136:49] wire [3:0] sinkC_req_out_bankSel_lo = 4'h1; // @[BankedStore.scala:136:49] wire [7:0] _sinkC_req_select_T_1 = 8'h1; // @[OneHot.scala:65:{12,27}] wire [7:0] sinkC_req_select = 8'h1; // @[OneHot.scala:65:{12,27}] wire [7:0] _sinkC_req_out_bankSel_T_8 = 8'h1; // @[OneHot.scala:65:{12,27}] wire [7:0] sinkC_req_bankSel = 8'h0; // @[BankedStore.scala:128:19] wire [7:0] sinkC_req_bankSum = 8'h0; // @[BankedStore.scala:128:19] wire [7:0] sinkC_req_bankEn = 8'h0; // @[BankedStore.scala:128:19] wire [7:0] _sinkC_req_out_bankSel_T_10 = 8'h0; // @[BankedStore.scala:136:71] wire [7:0] _sinkC_req_out_bankSel_T_11 = 8'h0; // @[BankedStore.scala:136:65] wire [7:0] _sinkC_req_out_bankSel_T_12 = 8'h0; // @[BankedStore.scala:136:24] wire [7:0] _sinkC_req_out_bankEn_T_9 = 8'h0; // @[BankedStore.scala:137:55] wire [7:0] _sinkC_req_out_bankEn_T_10 = 8'h0; // @[BankedStore.scala:137:24] wire [7:0] sourceC_req_bankSum = 8'h0; // @[BankedStore.scala:128:19] wire [1:0] sinkC_req_out_bankSel_lo_hi = 2'h0; // @[BankedStore.scala:136:49] wire [1:0] sinkC_req_out_bankSel_hi_lo = 2'h0; // @[BankedStore.scala:136:49] wire [1:0] sinkC_req_out_bankSel_hi_hi = 2'h0; // @[BankedStore.scala:136:49] wire [1:0] _sourceC_req_ready_T = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sourceC_req_ready_T_1 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sourceC_req_ready_T_4 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sourceC_req_ready_T_5 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sourceC_req_ready_T_8 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sourceC_req_ready_T_9 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sourceC_req_ready_T_12 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sourceC_req_ready_T_13 = 2'h0; // @[BankedStore.scala:131:96] wire [3:0] sinkC_req_ready_lo = 4'hF; // @[BankedStore.scala:131:21, :136:71, :137:72] wire [3:0] sinkC_req_ready_hi = 4'hF; // @[BankedStore.scala:131:21, :136:71, :137:72] wire [3:0] sinkC_req_out_bankEn_lo = 4'hF; // @[BankedStore.scala:131:21, :136:71, :137:72] wire [3:0] sinkC_req_out_bankEn_hi = 4'hF; // @[BankedStore.scala:131:21, :136:71, :137:72] wire [3:0] _sinkD_req_out_bankSel_T_9 = 4'hF; // @[BankedStore.scala:131:21, :136:71, :137:72] wire [3:0] sourceC_req_ready = 4'hF; // @[BankedStore.scala:131:21, :136:71, :137:72] wire [3:0] _sourceC_req_out_bankSel_T_9 = 4'hF; // @[BankedStore.scala:131:21, :136:71, :137:72] wire [3:0] sourceC_req_out_bankEn_lo = 4'hF; // @[BankedStore.scala:131:21, :136:71, :137:72] wire [3:0] sourceC_req_out_bankEn_hi = 4'hF; // @[BankedStore.scala:131:21, :136:71, :137:72] wire [7:0] sinkC_req_ready = 8'hFF; // @[BankedStore.scala:131:21] wire [7:0] _sinkC_req_io_sinkC_adr_ready_T_1 = 8'hFF; // @[BankedStore.scala:132:21] wire [7:0] _sinkC_req_out_bankEn_T_8 = 8'hFF; // @[BankedStore.scala:137:72] wire [7:0] _sinkD_req_out_bankSel_T_10 = 8'hFF; // @[BankedStore.scala:136:71] wire [7:0] _sourceC_req_out_bankSel_T_10 = 8'hFF; // @[BankedStore.scala:136:71] wire [7:0] _sourceC_req_out_bankEn_T_8 = 8'hFF; // @[BankedStore.scala:137:72] wire [1:0] io_sinkD_adr_bits_mask = 2'h3; // @[BankedStore.scala:59:7] wire [1:0] io_sourceC_adr_bits_mask = 2'h3; // @[BankedStore.scala:59:7] wire [1:0] sinkC_req_ready_lo_lo = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] sinkC_req_ready_lo_hi = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] sinkC_req_ready_hi_lo = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] sinkC_req_ready_hi_hi = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] sinkC_req_out_bankEn_lo_lo = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] sinkC_req_out_bankEn_lo_hi = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] sinkC_req_out_bankEn_hi_lo = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] sinkC_req_out_bankEn_hi_hi = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_ready_lo = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] sourceC_req_ready_hi = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] _sourceC_req_out_bankEn_T_4 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sourceC_req_out_bankEn_T_5 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sourceC_req_out_bankEn_T_6 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sourceC_req_out_bankEn_T_7 = 2'h3; // @[BankedStore.scala:137:72] wire [31:0] io_sinkC_dat_data = 32'h0; // @[BankedStore.scala:59:7] wire [31:0] sinkC_req_words_0 = 32'h0; // @[BankedStore.scala:123:19] wire [31:0] sinkC_req_data_0 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sinkC_req_data_1 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sinkC_req_data_2 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sinkC_req_data_3 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sinkC_req_data_4 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sinkC_req_data_5 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sinkC_req_data_6 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sinkC_req_data_7 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceC_req_data_0 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceC_req_data_1 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceC_req_data_2 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceC_req_data_3 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceC_req_data_4 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceC_req_data_5 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceC_req_data_6 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceC_req_data_7 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceD_rreq_data_0 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceD_rreq_data_1 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceD_rreq_data_2 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceD_rreq_data_3 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceD_rreq_data_4 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceD_rreq_data_5 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceD_rreq_data_6 = 32'h0; // @[BankedStore.scala:128:19] wire [31:0] sourceD_rreq_data_7 = 32'h0; // @[BankedStore.scala:128:19] wire [3:0] io_sinkC_adr_bits_beat = 4'h0; // @[BankedStore.scala:59:7, :61:14, :136:49] wire [3:0] sinkC_req_out_bankSel_hi = 4'h0; // @[BankedStore.scala:59:7, :61:14, :136:49] wire [9:0] io_sinkC_adr_bits_set = 10'h0; // @[BankedStore.scala:59:7, :61:14] wire [2:0] io_sinkC_adr_bits_way = 3'h0; // @[OneHot.scala:64:49] wire [2:0] _sinkC_req_select_T = 3'h0; // @[OneHot.scala:64:49] wire [2:0] sinkC_req_select_shiftAmount = 3'h0; // @[OneHot.scala:64:49] wire [2:0] _sinkC_req_io_sinkC_adr_ready_T = 3'h0; // @[OneHot.scala:64:49] wire io_sinkC_adr_valid = 1'h0; // @[BankedStore.scala:59:7] wire io_sinkC_adr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire io_sinkC_adr_bits_mask = 1'h0; // @[BankedStore.scala:59:7] wire io_sourceC_adr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire io_sourceD_radr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire _sinkC_req_ready_T = 1'h0; // @[BankedStore.scala:131:71] wire _sinkC_req_ready_T_1 = 1'h0; // @[BankedStore.scala:131:96] wire _sinkC_req_ready_T_2 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_4 = 1'h0; // @[BankedStore.scala:131:71] wire _sinkC_req_ready_T_5 = 1'h0; // @[BankedStore.scala:131:96] wire _sinkC_req_ready_T_6 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_8 = 1'h0; // @[BankedStore.scala:131:71] wire _sinkC_req_ready_T_9 = 1'h0; // @[BankedStore.scala:131:96] wire _sinkC_req_ready_T_10 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_12 = 1'h0; // @[BankedStore.scala:131:71] wire _sinkC_req_ready_T_13 = 1'h0; // @[BankedStore.scala:131:96] wire _sinkC_req_ready_T_14 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_16 = 1'h0; // @[BankedStore.scala:131:71] wire _sinkC_req_ready_T_17 = 1'h0; // @[BankedStore.scala:131:96] wire _sinkC_req_ready_T_18 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_20 = 1'h0; // @[BankedStore.scala:131:71] wire _sinkC_req_ready_T_21 = 1'h0; // @[BankedStore.scala:131:96] wire _sinkC_req_ready_T_22 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_24 = 1'h0; // @[BankedStore.scala:131:71] wire _sinkC_req_ready_T_25 = 1'h0; // @[BankedStore.scala:131:96] wire _sinkC_req_ready_T_26 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_28 = 1'h0; // @[BankedStore.scala:131:71] wire _sinkC_req_ready_T_29 = 1'h0; // @[BankedStore.scala:131:96] wire _sinkC_req_ready_T_30 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_out_bankSel_T_1 = 1'h0; // @[BankedStore.scala:136:49] wire _sinkC_req_out_bankSel_T_2 = 1'h0; // @[BankedStore.scala:136:49] wire _sinkC_req_out_bankSel_T_3 = 1'h0; // @[BankedStore.scala:136:49] wire _sinkC_req_out_bankSel_T_4 = 1'h0; // @[BankedStore.scala:136:49] wire _sinkC_req_out_bankSel_T_5 = 1'h0; // @[BankedStore.scala:136:49] wire _sinkC_req_out_bankSel_T_6 = 1'h0; // @[BankedStore.scala:136:49] wire _sinkC_req_out_bankSel_T_7 = 1'h0; // @[BankedStore.scala:136:49] wire _sinkC_req_out_bankSel_T_9 = 1'h0; // @[BankedStore.scala:136:71] wire sourceC_req_wen = 1'h0; // @[BankedStore.scala:128:19] wire _sourceC_req_ready_T_2 = 1'h0; // @[BankedStore.scala:131:101] wire _sourceC_req_ready_T_6 = 1'h0; // @[BankedStore.scala:131:101] wire _sourceC_req_ready_T_10 = 1'h0; // @[BankedStore.scala:131:101] wire _sourceC_req_ready_T_14 = 1'h0; // @[BankedStore.scala:131:101] wire sourceD_rreq_wen = 1'h0; // @[BankedStore.scala:128:19] wire _regout_en_T = 1'h0; // @[BankedStore.scala:165:32] wire regout_sel_0 = 1'h0; // @[BankedStore.scala:166:33] wire _regout_en_T_8 = 1'h0; // @[BankedStore.scala:165:32] wire regout_sel_0_1 = 1'h0; // @[BankedStore.scala:166:33] wire _regout_en_T_16 = 1'h0; // @[BankedStore.scala:165:32] wire regout_sel_0_2 = 1'h0; // @[BankedStore.scala:166:33] wire _regout_en_T_24 = 1'h0; // @[BankedStore.scala:165:32] wire regout_sel_0_3 = 1'h0; // @[BankedStore.scala:166:33] wire _regout_en_T_32 = 1'h0; // @[BankedStore.scala:165:32] wire regout_sel_0_4 = 1'h0; // @[BankedStore.scala:166:33] wire _regout_en_T_40 = 1'h0; // @[BankedStore.scala:165:32] wire regout_sel_0_5 = 1'h0; // @[BankedStore.scala:166:33] wire _regout_en_T_48 = 1'h0; // @[BankedStore.scala:165:32] wire regout_sel_0_6 = 1'h0; // @[BankedStore.scala:166:33] wire _regout_en_T_56 = 1'h0; // @[BankedStore.scala:165:32] wire regout_sel_0_7 = 1'h0; // @[BankedStore.scala:166:33] wire io_sinkC_adr_ready = 1'h1; // @[BankedStore.scala:59:7] wire sinkC_req_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkC_req_ready_T_3 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_7 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_11 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_15 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_19 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_23 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_27 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_31 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_io_sinkC_adr_ready_T_2 = 1'h1; // @[BankedStore.scala:132:21] wire _sinkC_req_out_bankSel_T = 1'h1; // @[BankedStore.scala:136:49] wire _sinkC_req_out_bankEn_T = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_1 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_2 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_3 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_4 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_5 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_6 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_7 = 1'h1; // @[BankedStore.scala:137:72] wire sinkD_req_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sourceC_req_ready_T_3 = 1'h1; // @[BankedStore.scala:131:58] wire _sourceC_req_ready_T_7 = 1'h1; // @[BankedStore.scala:131:58] wire _sourceC_req_ready_T_11 = 1'h1; // @[BankedStore.scala:131:58] wire _sourceC_req_ready_T_15 = 1'h1; // @[BankedStore.scala:131:58] wire _sourceC_req_out_bankEn_T = 1'h1; // @[BankedStore.scala:137:72] wire _sourceC_req_out_bankEn_T_1 = 1'h1; // @[BankedStore.scala:137:72] wire _sourceC_req_out_bankEn_T_2 = 1'h1; // @[BankedStore.scala:137:72] wire _sourceC_req_out_bankEn_T_3 = 1'h1; // @[BankedStore.scala:137:72] wire sourceD_wreq_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:132:21] wire _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:132:21] wire [63:0] _io_sourceC_dat_data_T; // @[BankedStore.scala:182:29] wire _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:132:21] wire _sourceD_rreq_out_bankSel_T_9 = io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :136:71] wire [31:0] decodeD_0; // @[BankedStore.scala:187:85] wire _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:132:21] wire _sourceD_wreq_out_bankSel_T_9 = io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :136:71] wire [31:0] sourceD_wreq_words_0 = io_sourceD_wdat_data_0; // @[BankedStore.scala:59:7, :123:19] wire io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7] wire io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7] wire [63:0] io_sourceC_dat_data_0; // @[BankedStore.scala:59:7] wire io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7] wire [31:0] io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7] wire [13:0] regout_idx; // @[Mux.scala:50:70] wire _regout_T; // @[BankedStore.scala:171:15] wire [13:0] _regout_WIRE; // @[BankedStore.scala:172:21] wire _regout_T_2; // @[BankedStore.scala:172:32] wire [13:0] regout_idx_1; // @[Mux.scala:50:70] wire _regout_T_5; // @[BankedStore.scala:171:15] wire [13:0] _regout_WIRE_1; // @[BankedStore.scala:172:21] wire _regout_T_7; // @[BankedStore.scala:172:32] wire [13:0] regout_idx_2; // @[Mux.scala:50:70] wire _regout_T_10; // @[BankedStore.scala:171:15] wire [13:0] _regout_WIRE_2; // @[BankedStore.scala:172:21] wire _regout_T_12; // @[BankedStore.scala:172:32] wire [13:0] regout_idx_3; // @[Mux.scala:50:70] wire _regout_T_15; // @[BankedStore.scala:171:15] wire [13:0] _regout_WIRE_3; // @[BankedStore.scala:172:21] wire _regout_T_17; // @[BankedStore.scala:172:32] wire [13:0] regout_idx_4; // @[Mux.scala:50:70] wire _regout_T_20; // @[BankedStore.scala:171:15] wire [13:0] _regout_WIRE_4; // @[BankedStore.scala:172:21] wire _regout_T_22; // @[BankedStore.scala:172:32] wire [13:0] regout_idx_5; // @[Mux.scala:50:70] wire _regout_T_25; // @[BankedStore.scala:171:15] wire [13:0] _regout_WIRE_5; // @[BankedStore.scala:172:21] wire _regout_T_27; // @[BankedStore.scala:172:32] wire [13:0] regout_idx_6; // @[Mux.scala:50:70] wire _regout_T_30; // @[BankedStore.scala:171:15] wire [13:0] _regout_WIRE_6; // @[BankedStore.scala:172:21] wire _regout_T_32; // @[BankedStore.scala:172:32] wire [13:0] regout_idx_7; // @[Mux.scala:50:70] wire _regout_T_35; // @[BankedStore.scala:171:15] wire [13:0] _regout_WIRE_7; // @[BankedStore.scala:172:21] wire _regout_T_37; // @[BankedStore.scala:172:32] wire [31:0] sinkD_req_words_0 = io_sinkD_dat_data_0[31:0]; // @[BankedStore.scala:59:7, :123:19] wire [31:0] sinkD_req_data_0 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sinkD_req_data_2 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sinkD_req_data_4 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sinkD_req_data_6 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sinkD_req_words_1 = io_sinkD_dat_data_0[63:32]; // @[BankedStore.scala:59:7, :123:19] wire [31:0] sinkD_req_data_1 = sinkD_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sinkD_req_data_3 = sinkD_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sinkD_req_data_5 = sinkD_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sinkD_req_data_7 = sinkD_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [12:0] sinkD_req_a_hi = {io_sinkD_adr_bits_way_0, io_sinkD_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [15:0] sinkD_req_a = {sinkD_req_a_hi, io_sinkD_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [13:0] _sinkD_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sinkD_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] sourceC_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] _sinkD_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [13:0] sinkD_req_index; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sinkD_req_select_T = sinkD_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sinkD_req_io_sinkD_adr_ready_T = sinkD_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sinkD_req_select_shiftAmount = _sinkD_req_select_T; // @[OneHot.scala:64:49] wire [3:0] _sinkD_req_select_T_1 = 4'h1 << sinkD_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sinkD_req_select = _sinkD_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] _sinkD_req_ready_T = sinkD_req_bankSum[1:0]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sinkD_req_ready_T_1 = _sinkD_req_ready_T; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_2 = |_sinkD_req_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_3 = ~_sinkD_req_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sinkD_req_ready_T_4 = sinkD_req_bankSum[3:2]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sinkD_req_ready_T_5 = _sinkD_req_ready_T_4; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_6 = |_sinkD_req_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_7 = ~_sinkD_req_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sinkD_req_ready_T_8 = sinkD_req_bankSum[5:4]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sinkD_req_ready_T_9 = _sinkD_req_ready_T_8; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_10 = |_sinkD_req_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_11 = ~_sinkD_req_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sinkD_req_ready_T_12 = sinkD_req_bankSum[7:6]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sinkD_req_ready_T_13 = _sinkD_req_ready_T_12; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_14 = |_sinkD_req_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_15 = ~_sinkD_req_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire [1:0] sinkD_req_ready_lo = {_sinkD_req_ready_T_7, _sinkD_req_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sinkD_req_ready_hi = {_sinkD_req_ready_T_15, _sinkD_req_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sinkD_req_ready = {sinkD_req_ready_hi, sinkD_req_ready_lo}; // @[BankedStore.scala:131:21] wire [3:0] _sinkD_req_io_sinkD_adr_ready_T_1 = sinkD_req_ready >> _sinkD_req_io_sinkD_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sinkD_req_io_sinkD_adr_ready_T_2 = _sinkD_req_io_sinkD_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sinkD_adr_ready_0 = _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sinkD_req_out_index_T = sinkD_req_a[15:2]; // @[BankedStore.scala:126:91, :135:23] assign sinkD_req_index = _sinkD_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sinkD_req_out_bankSel_T = sinkD_req_select[0]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_1 = sinkD_req_select[1]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_2 = sinkD_req_select[2]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_3 = sinkD_req_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sinkD_req_out_bankSel_T_4 = {2{_sinkD_req_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkD_req_out_bankSel_T_5 = {2{_sinkD_req_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkD_req_out_bankSel_T_6 = {2{_sinkD_req_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkD_req_out_bankSel_T_7 = {2{_sinkD_req_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sinkD_req_out_bankSel_lo = {_sinkD_req_out_bankSel_T_5, _sinkD_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sinkD_req_out_bankSel_hi = {_sinkD_req_out_bankSel_T_7, _sinkD_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sinkD_req_out_bankSel_T_8 = {sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sinkD_req_out_bankSel_T_11 = _sinkD_req_out_bankSel_T_8; // @[BankedStore.scala:136:{49,65}] assign _sinkD_req_out_bankSel_T_12 = io_sinkD_adr_valid_0 ? _sinkD_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sinkD_req_bankSel = _sinkD_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sinkD_req_out_bankEn_T = sinkD_req_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_1 = sinkD_req_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_2 = sinkD_req_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_3 = sinkD_req_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] _sinkD_req_out_bankEn_T_4 = {2{_sinkD_req_out_bankEn_T}}; // @[BankedStore.scala:137:72] wire [1:0] _sinkD_req_out_bankEn_T_5 = {2{_sinkD_req_out_bankEn_T_1}}; // @[BankedStore.scala:137:72] wire [1:0] _sinkD_req_out_bankEn_T_6 = {2{_sinkD_req_out_bankEn_T_2}}; // @[BankedStore.scala:137:72] wire [1:0] _sinkD_req_out_bankEn_T_7 = {2{_sinkD_req_out_bankEn_T_3}}; // @[BankedStore.scala:137:72] wire [3:0] sinkD_req_out_bankEn_lo = {_sinkD_req_out_bankEn_T_5, _sinkD_req_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [3:0] sinkD_req_out_bankEn_hi = {_sinkD_req_out_bankEn_T_7, _sinkD_req_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [7:0] _sinkD_req_out_bankEn_T_8 = {sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sinkD_req_out_bankEn_T_9 = sinkD_req_bankSel & _sinkD_req_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sinkD_req_out_bankEn_T_10 = io_sinkD_adr_bits_noop_0 ? 8'h0 : _sinkD_req_out_bankEn_T_9; // @[BankedStore.scala:59:7, :137:{24,55}] assign sinkD_req_bankEn = _sinkD_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [12:0] sourceC_req_a_hi = {io_sourceC_adr_bits_way_0, io_sourceC_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [15:0] sourceC_req_a = {sourceC_req_a_hi, io_sourceC_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [13:0] _sourceC_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceC_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] assign sinkD_req_bankSum = sourceC_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] _sourceC_req_out_bankEn_T_9 = sourceC_req_bankSel; // @[BankedStore.scala:128:19, :137:55] wire [7:0] _sourceC_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [13:0] sourceC_req_index; // @[BankedStore.scala:128:19] wire [7:0] sourceC_req_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sourceC_req_select_T = sourceC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sourceC_req_io_sourceC_adr_ready_T = sourceC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sourceC_req_select_shiftAmount = _sourceC_req_select_T; // @[OneHot.scala:64:49] wire [3:0] _sourceC_req_select_T_1 = 4'h1 << sourceC_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sourceC_req_select = _sourceC_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] _sourceC_req_io_sourceC_adr_ready_T_1 = 4'hF >> _sourceC_req_io_sourceC_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}, :136:71, :137:72] assign _sourceC_req_io_sourceC_adr_ready_T_2 = _sourceC_req_io_sourceC_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceC_adr_ready_0 = _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceC_req_out_index_T = sourceC_req_a[15:2]; // @[BankedStore.scala:126:91, :135:23] assign sourceC_req_index = _sourceC_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceC_req_out_bankSel_T = sourceC_req_select[0]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_1 = sourceC_req_select[1]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_2 = sourceC_req_select[2]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_3 = sourceC_req_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sourceC_req_out_bankSel_T_4 = {2{_sourceC_req_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceC_req_out_bankSel_T_5 = {2{_sourceC_req_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceC_req_out_bankSel_T_6 = {2{_sourceC_req_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceC_req_out_bankSel_T_7 = {2{_sourceC_req_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sourceC_req_out_bankSel_lo = {_sourceC_req_out_bankSel_T_5, _sourceC_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sourceC_req_out_bankSel_hi = {_sourceC_req_out_bankSel_T_7, _sourceC_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sourceC_req_out_bankSel_T_8 = {sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceC_req_out_bankSel_T_11 = _sourceC_req_out_bankSel_T_8; // @[BankedStore.scala:136:{49,65}] assign _sourceC_req_out_bankSel_T_12 = io_sourceC_adr_valid_0 ? _sourceC_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceC_req_bankSel = _sourceC_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] assign _sourceC_req_out_bankEn_T_10 = _sourceC_req_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceC_req_bankEn = _sourceC_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [12:0] sourceD_rreq_a_hi = {io_sourceD_radr_bits_way_0, io_sourceD_radr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [16:0] sourceD_rreq_a = {sourceD_rreq_a_hi, io_sourceD_radr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [13:0] _sourceD_rreq_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceD_rreq_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceD_rreq_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [13:0] sourceD_rreq_index; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankEn; // @[BankedStore.scala:128:19] wire [2:0] _sourceD_rreq_select_T = sourceD_rreq_a[2:0]; // @[BankedStore.scala:126:91, :130:28] wire [2:0] _sourceD_rreq_io_sourceD_radr_ready_T = sourceD_rreq_a[2:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [2:0] sourceD_rreq_select_shiftAmount = _sourceD_rreq_select_T; // @[OneHot.scala:64:49] wire [7:0] _sourceD_rreq_select_T_1 = 8'h1 << sourceD_rreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:{12,27}] wire [7:0] sourceD_rreq_select = _sourceD_rreq_select_T_1; // @[OneHot.scala:65:{12,27}] wire _sourceD_rreq_ready_T = sourceD_rreq_bankSum[0]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_rreq_ready_T_1 = _sourceD_rreq_ready_T & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_2 = _sourceD_rreq_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_3 = ~_sourceD_rreq_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire _sourceD_rreq_ready_T_4 = sourceD_rreq_bankSum[1]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_rreq_ready_T_5 = _sourceD_rreq_ready_T_4 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_6 = _sourceD_rreq_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_7 = ~_sourceD_rreq_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire _sourceD_rreq_ready_T_8 = sourceD_rreq_bankSum[2]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_rreq_ready_T_9 = _sourceD_rreq_ready_T_8 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_10 = _sourceD_rreq_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_11 = ~_sourceD_rreq_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire _sourceD_rreq_ready_T_12 = sourceD_rreq_bankSum[3]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_rreq_ready_T_13 = _sourceD_rreq_ready_T_12 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_14 = _sourceD_rreq_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_15 = ~_sourceD_rreq_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire _sourceD_rreq_ready_T_16 = sourceD_rreq_bankSum[4]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_rreq_ready_T_17 = _sourceD_rreq_ready_T_16 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_18 = _sourceD_rreq_ready_T_17; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_19 = ~_sourceD_rreq_ready_T_18; // @[BankedStore.scala:131:{58,101}] wire _sourceD_rreq_ready_T_20 = sourceD_rreq_bankSum[5]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_rreq_ready_T_21 = _sourceD_rreq_ready_T_20 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_22 = _sourceD_rreq_ready_T_21; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_23 = ~_sourceD_rreq_ready_T_22; // @[BankedStore.scala:131:{58,101}] wire _sourceD_rreq_ready_T_24 = sourceD_rreq_bankSum[6]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_rreq_ready_T_25 = _sourceD_rreq_ready_T_24 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_26 = _sourceD_rreq_ready_T_25; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_27 = ~_sourceD_rreq_ready_T_26; // @[BankedStore.scala:131:{58,101}] wire _sourceD_rreq_ready_T_28 = sourceD_rreq_bankSum[7]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_rreq_ready_T_29 = _sourceD_rreq_ready_T_28 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_30 = _sourceD_rreq_ready_T_29; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_31 = ~_sourceD_rreq_ready_T_30; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceD_rreq_ready_lo_lo = {_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_rreq_ready_lo_hi = {_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_rreq_ready_lo = {sourceD_rreq_ready_lo_hi, sourceD_rreq_ready_lo_lo}; // @[BankedStore.scala:131:21] wire [1:0] sourceD_rreq_ready_hi_lo = {_sourceD_rreq_ready_T_23, _sourceD_rreq_ready_T_19}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_rreq_ready_hi_hi = {_sourceD_rreq_ready_T_31, _sourceD_rreq_ready_T_27}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_rreq_ready_hi = {sourceD_rreq_ready_hi_hi, sourceD_rreq_ready_hi_lo}; // @[BankedStore.scala:131:21] wire [7:0] sourceD_rreq_ready = {sourceD_rreq_ready_hi, sourceD_rreq_ready_lo}; // @[BankedStore.scala:131:21] wire [7:0] _sourceD_rreq_io_sourceD_radr_ready_T_1 = sourceD_rreq_ready >> _sourceD_rreq_io_sourceD_radr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceD_rreq_io_sourceD_radr_ready_T_2 = _sourceD_rreq_io_sourceD_radr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceD_radr_ready_0 = _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceD_rreq_out_index_T = sourceD_rreq_a[16:3]; // @[BankedStore.scala:126:91, :135:23] assign sourceD_rreq_index = _sourceD_rreq_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceD_rreq_out_bankSel_T = sourceD_rreq_select[0]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_1 = sourceD_rreq_select[1]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_2 = sourceD_rreq_select[2]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_3 = sourceD_rreq_select[3]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_4 = sourceD_rreq_select[4]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_5 = sourceD_rreq_select[5]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_6 = sourceD_rreq_select[6]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_7 = sourceD_rreq_select[7]; // @[OneHot.scala:65:27] wire [1:0] sourceD_rreq_out_bankSel_lo_lo = {_sourceD_rreq_out_bankSel_T_1, _sourceD_rreq_out_bankSel_T}; // @[BankedStore.scala:136:49] wire [1:0] sourceD_rreq_out_bankSel_lo_hi = {_sourceD_rreq_out_bankSel_T_3, _sourceD_rreq_out_bankSel_T_2}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_rreq_out_bankSel_lo = {sourceD_rreq_out_bankSel_lo_hi, sourceD_rreq_out_bankSel_lo_lo}; // @[BankedStore.scala:136:49] wire [1:0] sourceD_rreq_out_bankSel_hi_lo = {_sourceD_rreq_out_bankSel_T_5, _sourceD_rreq_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [1:0] sourceD_rreq_out_bankSel_hi_hi = {_sourceD_rreq_out_bankSel_T_7, _sourceD_rreq_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_rreq_out_bankSel_hi = {sourceD_rreq_out_bankSel_hi_hi, sourceD_rreq_out_bankSel_hi_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_rreq_out_bankSel_T_8 = {sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_rreq_out_bankSel_T_10 = {8{_sourceD_rreq_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sourceD_rreq_out_bankSel_T_11 = _sourceD_rreq_out_bankSel_T_8 & _sourceD_rreq_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sourceD_rreq_out_bankSel_T_12 = io_sourceD_radr_valid_0 ? _sourceD_rreq_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceD_rreq_bankSel = _sourceD_rreq_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceD_rreq_out_bankEn_T = sourceD_rreq_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_1 = sourceD_rreq_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_2 = sourceD_rreq_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_3 = sourceD_rreq_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_4 = sourceD_rreq_ready[4]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_5 = sourceD_rreq_ready[5]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_6 = sourceD_rreq_ready[6]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_7 = sourceD_rreq_ready[7]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] sourceD_rreq_out_bankEn_lo_lo = {_sourceD_rreq_out_bankEn_T_1, _sourceD_rreq_out_bankEn_T}; // @[BankedStore.scala:137:72] wire [1:0] sourceD_rreq_out_bankEn_lo_hi = {_sourceD_rreq_out_bankEn_T_3, _sourceD_rreq_out_bankEn_T_2}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_rreq_out_bankEn_lo = {sourceD_rreq_out_bankEn_lo_hi, sourceD_rreq_out_bankEn_lo_lo}; // @[BankedStore.scala:137:72] wire [1:0] sourceD_rreq_out_bankEn_hi_lo = {_sourceD_rreq_out_bankEn_T_5, _sourceD_rreq_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [1:0] sourceD_rreq_out_bankEn_hi_hi = {_sourceD_rreq_out_bankEn_T_7, _sourceD_rreq_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_rreq_out_bankEn_hi = {sourceD_rreq_out_bankEn_hi_hi, sourceD_rreq_out_bankEn_hi_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_rreq_out_bankEn_T_8 = {sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_rreq_out_bankEn_T_9 = sourceD_rreq_bankSel & _sourceD_rreq_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceD_rreq_out_bankEn_T_10 = _sourceD_rreq_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceD_rreq_bankEn = _sourceD_rreq_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [31:0] sourceD_wreq_data_0 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sourceD_wreq_data_1 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sourceD_wreq_data_2 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sourceD_wreq_data_3 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sourceD_wreq_data_4 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sourceD_wreq_data_5 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sourceD_wreq_data_6 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [31:0] sourceD_wreq_data_7 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [12:0] sourceD_wreq_a_hi = {io_sourceD_wadr_bits_way_0, io_sourceD_wadr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [16:0] sourceD_wreq_a = {sourceD_wreq_a_hi, io_sourceD_wadr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [13:0] _sourceD_wreq_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceD_wreq_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceD_wreq_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [13:0] sourceD_wreq_index; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankEn; // @[BankedStore.scala:128:19] wire [2:0] _sourceD_wreq_select_T = sourceD_wreq_a[2:0]; // @[BankedStore.scala:126:91, :130:28] wire [2:0] _sourceD_wreq_io_sourceD_wadr_ready_T = sourceD_wreq_a[2:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [2:0] sourceD_wreq_select_shiftAmount = _sourceD_wreq_select_T; // @[OneHot.scala:64:49] wire [7:0] _sourceD_wreq_select_T_1 = 8'h1 << sourceD_wreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:{12,27}] wire [7:0] sourceD_wreq_select = _sourceD_wreq_select_T_1; // @[OneHot.scala:65:{12,27}] wire _sourceD_wreq_ready_T = sourceD_wreq_bankSum[0]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_wreq_ready_T_1 = _sourceD_wreq_ready_T & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_2 = _sourceD_wreq_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_3 = ~_sourceD_wreq_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire _sourceD_wreq_ready_T_4 = sourceD_wreq_bankSum[1]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_wreq_ready_T_5 = _sourceD_wreq_ready_T_4 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_6 = _sourceD_wreq_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_7 = ~_sourceD_wreq_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire _sourceD_wreq_ready_T_8 = sourceD_wreq_bankSum[2]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_wreq_ready_T_9 = _sourceD_wreq_ready_T_8 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_10 = _sourceD_wreq_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_11 = ~_sourceD_wreq_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire _sourceD_wreq_ready_T_12 = sourceD_wreq_bankSum[3]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_wreq_ready_T_13 = _sourceD_wreq_ready_T_12 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_14 = _sourceD_wreq_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_15 = ~_sourceD_wreq_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire _sourceD_wreq_ready_T_16 = sourceD_wreq_bankSum[4]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_wreq_ready_T_17 = _sourceD_wreq_ready_T_16 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_18 = _sourceD_wreq_ready_T_17; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_19 = ~_sourceD_wreq_ready_T_18; // @[BankedStore.scala:131:{58,101}] wire _sourceD_wreq_ready_T_20 = sourceD_wreq_bankSum[5]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_wreq_ready_T_21 = _sourceD_wreq_ready_T_20 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_22 = _sourceD_wreq_ready_T_21; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_23 = ~_sourceD_wreq_ready_T_22; // @[BankedStore.scala:131:{58,101}] wire _sourceD_wreq_ready_T_24 = sourceD_wreq_bankSum[6]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_wreq_ready_T_25 = _sourceD_wreq_ready_T_24 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_26 = _sourceD_wreq_ready_T_25; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_27 = ~_sourceD_wreq_ready_T_26; // @[BankedStore.scala:131:{58,101}] wire _sourceD_wreq_ready_T_28 = sourceD_wreq_bankSum[7]; // @[BankedStore.scala:128:19, :131:71] wire _sourceD_wreq_ready_T_29 = _sourceD_wreq_ready_T_28 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_30 = _sourceD_wreq_ready_T_29; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_31 = ~_sourceD_wreq_ready_T_30; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceD_wreq_ready_lo_lo = {_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_wreq_ready_lo_hi = {_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_wreq_ready_lo = {sourceD_wreq_ready_lo_hi, sourceD_wreq_ready_lo_lo}; // @[BankedStore.scala:131:21] wire [1:0] sourceD_wreq_ready_hi_lo = {_sourceD_wreq_ready_T_23, _sourceD_wreq_ready_T_19}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_wreq_ready_hi_hi = {_sourceD_wreq_ready_T_31, _sourceD_wreq_ready_T_27}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_wreq_ready_hi = {sourceD_wreq_ready_hi_hi, sourceD_wreq_ready_hi_lo}; // @[BankedStore.scala:131:21] wire [7:0] sourceD_wreq_ready = {sourceD_wreq_ready_hi, sourceD_wreq_ready_lo}; // @[BankedStore.scala:131:21] wire [7:0] _sourceD_wreq_io_sourceD_wadr_ready_T_1 = sourceD_wreq_ready >> _sourceD_wreq_io_sourceD_wadr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceD_wreq_io_sourceD_wadr_ready_T_2 = _sourceD_wreq_io_sourceD_wadr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceD_wadr_ready_0 = _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceD_wreq_out_index_T = sourceD_wreq_a[16:3]; // @[BankedStore.scala:126:91, :135:23] assign sourceD_wreq_index = _sourceD_wreq_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceD_wreq_out_bankSel_T = sourceD_wreq_select[0]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_1 = sourceD_wreq_select[1]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_2 = sourceD_wreq_select[2]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_3 = sourceD_wreq_select[3]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_4 = sourceD_wreq_select[4]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_5 = sourceD_wreq_select[5]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_6 = sourceD_wreq_select[6]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_7 = sourceD_wreq_select[7]; // @[OneHot.scala:65:27] wire [1:0] sourceD_wreq_out_bankSel_lo_lo = {_sourceD_wreq_out_bankSel_T_1, _sourceD_wreq_out_bankSel_T}; // @[BankedStore.scala:136:49] wire [1:0] sourceD_wreq_out_bankSel_lo_hi = {_sourceD_wreq_out_bankSel_T_3, _sourceD_wreq_out_bankSel_T_2}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_wreq_out_bankSel_lo = {sourceD_wreq_out_bankSel_lo_hi, sourceD_wreq_out_bankSel_lo_lo}; // @[BankedStore.scala:136:49] wire [1:0] sourceD_wreq_out_bankSel_hi_lo = {_sourceD_wreq_out_bankSel_T_5, _sourceD_wreq_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [1:0] sourceD_wreq_out_bankSel_hi_hi = {_sourceD_wreq_out_bankSel_T_7, _sourceD_wreq_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_wreq_out_bankSel_hi = {sourceD_wreq_out_bankSel_hi_hi, sourceD_wreq_out_bankSel_hi_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_wreq_out_bankSel_T_8 = {sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_wreq_out_bankSel_T_10 = {8{_sourceD_wreq_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sourceD_wreq_out_bankSel_T_11 = _sourceD_wreq_out_bankSel_T_8 & _sourceD_wreq_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sourceD_wreq_out_bankSel_T_12 = io_sourceD_wadr_valid_0 ? _sourceD_wreq_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceD_wreq_bankSel = _sourceD_wreq_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceD_wreq_out_bankEn_T = sourceD_wreq_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_1 = sourceD_wreq_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_2 = sourceD_wreq_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_3 = sourceD_wreq_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_4 = sourceD_wreq_ready[4]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_5 = sourceD_wreq_ready[5]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_6 = sourceD_wreq_ready[6]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_7 = sourceD_wreq_ready[7]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] sourceD_wreq_out_bankEn_lo_lo = {_sourceD_wreq_out_bankEn_T_1, _sourceD_wreq_out_bankEn_T}; // @[BankedStore.scala:137:72] wire [1:0] sourceD_wreq_out_bankEn_lo_hi = {_sourceD_wreq_out_bankEn_T_3, _sourceD_wreq_out_bankEn_T_2}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_wreq_out_bankEn_lo = {sourceD_wreq_out_bankEn_lo_hi, sourceD_wreq_out_bankEn_lo_lo}; // @[BankedStore.scala:137:72] wire [1:0] sourceD_wreq_out_bankEn_hi_lo = {_sourceD_wreq_out_bankEn_T_5, _sourceD_wreq_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [1:0] sourceD_wreq_out_bankEn_hi_hi = {_sourceD_wreq_out_bankEn_T_7, _sourceD_wreq_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_wreq_out_bankEn_hi = {sourceD_wreq_out_bankEn_hi_hi, sourceD_wreq_out_bankEn_hi_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_wreq_out_bankEn_T_8 = {sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_wreq_out_bankEn_T_9 = sourceD_wreq_bankSel & _sourceD_wreq_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceD_wreq_out_bankEn_T_10 = _sourceD_wreq_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceD_wreq_bankEn = _sourceD_wreq_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] assign sourceD_wreq_bankSum = sinkD_req_bankSel | sourceC_req_bankSel; // @[BankedStore.scala:128:19, :161:17] assign sourceD_rreq_bankSum = sourceD_wreq_bankSel | sourceD_wreq_bankSum; // @[BankedStore.scala:128:19, :161:17] wire _regout_en_T_1 = sourceC_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_5 = _regout_en_T_1; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_2 = sinkD_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_3 = sourceD_wreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_4 = sourceD_rreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_6 = _regout_en_T_5 | _regout_en_T_2; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_7 = _regout_en_T_6 | _regout_en_T_3; // @[BankedStore.scala:165:{32,45}] wire regout_en = _regout_en_T_7 | _regout_en_T_4; // @[BankedStore.scala:165:{32,45}] wire regout_sel_1 = sourceC_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2 = sinkD_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3 = sourceD_wreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T = regout_sel_3; // @[Mux.scala:50:70] wire regout_sel_4 = sourceD_rreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_1 = regout_sel_2 | _regout_wen_T; // @[Mux.scala:50:70] wire _regout_wen_T_2 = ~regout_sel_1 & _regout_wen_T_1; // @[Mux.scala:50:70] wire regout_wen = _regout_wen_T_2; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T = regout_sel_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_1 = regout_sel_2 ? sinkD_req_index : _regout_idx_T; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_2 = regout_sel_1 ? sourceC_req_index : _regout_idx_T_1; // @[Mux.scala:50:70] assign regout_idx = _regout_idx_T_2; // @[Mux.scala:50:70] assign _regout_WIRE = regout_idx; // @[Mux.scala:50:70] wire [31:0] _regout_data_T = regout_sel_3 ? sourceD_wreq_data_0 : 32'h0; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_1 = regout_sel_2 ? sinkD_req_data_0 : _regout_data_T; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_2 = regout_sel_1 ? 32'h0 : _regout_data_T_1; // @[Mux.scala:50:70] wire [31:0] regout_data = _regout_data_T_2; // @[Mux.scala:50:70] assign _regout_T = regout_wen & regout_en; // @[Mux.scala:50:70] wire _regout_T_1 = ~regout_wen; // @[Mux.scala:50:70] assign _regout_T_2 = _regout_T_1 & regout_en; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_3 = ~regout_wen; // @[Mux.scala:50:70] wire _regout_T_4 = _regout_T_3 & regout_en; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG; // @[BankedStore.scala:172:47] reg [31:0] regout_r; // @[BankedStore.scala:172:14] wire [31:0] regout_0 = regout_r; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_9 = sourceC_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_13 = _regout_en_T_9; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_10 = sinkD_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_11 = sourceD_wreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_12 = sourceD_rreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_14 = _regout_en_T_13 | _regout_en_T_10; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_15 = _regout_en_T_14 | _regout_en_T_11; // @[BankedStore.scala:165:{32,45}] wire regout_en_1 = _regout_en_T_15 | _regout_en_T_12; // @[BankedStore.scala:165:{32,45}] wire regout_sel_1_1 = sourceC_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_1 = sinkD_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_1 = sourceD_wreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_3 = regout_sel_3_1; // @[Mux.scala:50:70] wire regout_sel_4_1 = sourceD_rreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_4 = regout_sel_2_1 | _regout_wen_T_3; // @[Mux.scala:50:70] wire _regout_wen_T_5 = ~regout_sel_1_1 & _regout_wen_T_4; // @[Mux.scala:50:70] wire regout_wen_1 = _regout_wen_T_5; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_3 = regout_sel_3_1 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_4 = regout_sel_2_1 ? sinkD_req_index : _regout_idx_T_3; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_5 = regout_sel_1_1 ? sourceC_req_index : _regout_idx_T_4; // @[Mux.scala:50:70] assign regout_idx_1 = _regout_idx_T_5; // @[Mux.scala:50:70] assign _regout_WIRE_1 = regout_idx_1; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_3 = regout_sel_3_1 ? sourceD_wreq_data_1 : 32'h0; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_4 = regout_sel_2_1 ? sinkD_req_data_1 : _regout_data_T_3; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_5 = regout_sel_1_1 ? 32'h0 : _regout_data_T_4; // @[Mux.scala:50:70] wire [31:0] regout_data_1 = _regout_data_T_5; // @[Mux.scala:50:70] assign _regout_T_5 = regout_wen_1 & regout_en_1; // @[Mux.scala:50:70] wire _regout_T_6 = ~regout_wen_1; // @[Mux.scala:50:70] assign _regout_T_7 = _regout_T_6 & regout_en_1; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_8 = ~regout_wen_1; // @[Mux.scala:50:70] wire _regout_T_9 = _regout_T_8 & regout_en_1; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_1; // @[BankedStore.scala:172:47] reg [31:0] regout_r_1; // @[BankedStore.scala:172:14] wire [31:0] regout_1 = regout_r_1; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_17 = sourceC_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_21 = _regout_en_T_17; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_18 = sinkD_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_19 = sourceD_wreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_20 = sourceD_rreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_22 = _regout_en_T_21 | _regout_en_T_18; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_23 = _regout_en_T_22 | _regout_en_T_19; // @[BankedStore.scala:165:{32,45}] wire regout_en_2 = _regout_en_T_23 | _regout_en_T_20; // @[BankedStore.scala:165:{32,45}] wire regout_sel_1_2 = sourceC_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_2 = sinkD_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_2 = sourceD_wreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_6 = regout_sel_3_2; // @[Mux.scala:50:70] wire regout_sel_4_2 = sourceD_rreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_7 = regout_sel_2_2 | _regout_wen_T_6; // @[Mux.scala:50:70] wire _regout_wen_T_8 = ~regout_sel_1_2 & _regout_wen_T_7; // @[Mux.scala:50:70] wire regout_wen_2 = _regout_wen_T_8; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_6 = regout_sel_3_2 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_7 = regout_sel_2_2 ? sinkD_req_index : _regout_idx_T_6; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_8 = regout_sel_1_2 ? sourceC_req_index : _regout_idx_T_7; // @[Mux.scala:50:70] assign regout_idx_2 = _regout_idx_T_8; // @[Mux.scala:50:70] assign _regout_WIRE_2 = regout_idx_2; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_6 = regout_sel_3_2 ? sourceD_wreq_data_2 : 32'h0; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_7 = regout_sel_2_2 ? sinkD_req_data_2 : _regout_data_T_6; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_8 = regout_sel_1_2 ? 32'h0 : _regout_data_T_7; // @[Mux.scala:50:70] wire [31:0] regout_data_2 = _regout_data_T_8; // @[Mux.scala:50:70] assign _regout_T_10 = regout_wen_2 & regout_en_2; // @[Mux.scala:50:70] wire _regout_T_11 = ~regout_wen_2; // @[Mux.scala:50:70] assign _regout_T_12 = _regout_T_11 & regout_en_2; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_13 = ~regout_wen_2; // @[Mux.scala:50:70] wire _regout_T_14 = _regout_T_13 & regout_en_2; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_2; // @[BankedStore.scala:172:47] reg [31:0] regout_r_2; // @[BankedStore.scala:172:14] wire [31:0] regout_2 = regout_r_2; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_25 = sourceC_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_29 = _regout_en_T_25; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_26 = sinkD_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_27 = sourceD_wreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_28 = sourceD_rreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_30 = _regout_en_T_29 | _regout_en_T_26; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_31 = _regout_en_T_30 | _regout_en_T_27; // @[BankedStore.scala:165:{32,45}] wire regout_en_3 = _regout_en_T_31 | _regout_en_T_28; // @[BankedStore.scala:165:{32,45}] wire regout_sel_1_3 = sourceC_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_3 = sinkD_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_3 = sourceD_wreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_9 = regout_sel_3_3; // @[Mux.scala:50:70] wire regout_sel_4_3 = sourceD_rreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_10 = regout_sel_2_3 | _regout_wen_T_9; // @[Mux.scala:50:70] wire _regout_wen_T_11 = ~regout_sel_1_3 & _regout_wen_T_10; // @[Mux.scala:50:70] wire regout_wen_3 = _regout_wen_T_11; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_9 = regout_sel_3_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_10 = regout_sel_2_3 ? sinkD_req_index : _regout_idx_T_9; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_11 = regout_sel_1_3 ? sourceC_req_index : _regout_idx_T_10; // @[Mux.scala:50:70] assign regout_idx_3 = _regout_idx_T_11; // @[Mux.scala:50:70] assign _regout_WIRE_3 = regout_idx_3; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_9 = regout_sel_3_3 ? sourceD_wreq_data_3 : 32'h0; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_10 = regout_sel_2_3 ? sinkD_req_data_3 : _regout_data_T_9; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_11 = regout_sel_1_3 ? 32'h0 : _regout_data_T_10; // @[Mux.scala:50:70] wire [31:0] regout_data_3 = _regout_data_T_11; // @[Mux.scala:50:70] assign _regout_T_15 = regout_wen_3 & regout_en_3; // @[Mux.scala:50:70] wire _regout_T_16 = ~regout_wen_3; // @[Mux.scala:50:70] assign _regout_T_17 = _regout_T_16 & regout_en_3; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_18 = ~regout_wen_3; // @[Mux.scala:50:70] wire _regout_T_19 = _regout_T_18 & regout_en_3; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_3; // @[BankedStore.scala:172:47] reg [31:0] regout_r_3; // @[BankedStore.scala:172:14] wire [31:0] regout_3 = regout_r_3; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_33 = sourceC_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_37 = _regout_en_T_33; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_34 = sinkD_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_35 = sourceD_wreq_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_36 = sourceD_rreq_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_38 = _regout_en_T_37 | _regout_en_T_34; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_39 = _regout_en_T_38 | _regout_en_T_35; // @[BankedStore.scala:165:{32,45}] wire regout_en_4 = _regout_en_T_39 | _regout_en_T_36; // @[BankedStore.scala:165:{32,45}] wire regout_sel_1_4 = sourceC_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_4 = sinkD_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_4 = sourceD_wreq_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_12 = regout_sel_3_4; // @[Mux.scala:50:70] wire regout_sel_4_4 = sourceD_rreq_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_13 = regout_sel_2_4 | _regout_wen_T_12; // @[Mux.scala:50:70] wire _regout_wen_T_14 = ~regout_sel_1_4 & _regout_wen_T_13; // @[Mux.scala:50:70] wire regout_wen_4 = _regout_wen_T_14; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_12 = regout_sel_3_4 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_13 = regout_sel_2_4 ? sinkD_req_index : _regout_idx_T_12; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_14 = regout_sel_1_4 ? sourceC_req_index : _regout_idx_T_13; // @[Mux.scala:50:70] assign regout_idx_4 = _regout_idx_T_14; // @[Mux.scala:50:70] assign _regout_WIRE_4 = regout_idx_4; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_12 = regout_sel_3_4 ? sourceD_wreq_data_4 : 32'h0; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_13 = regout_sel_2_4 ? sinkD_req_data_4 : _regout_data_T_12; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_14 = regout_sel_1_4 ? 32'h0 : _regout_data_T_13; // @[Mux.scala:50:70] wire [31:0] regout_data_4 = _regout_data_T_14; // @[Mux.scala:50:70] assign _regout_T_20 = regout_wen_4 & regout_en_4; // @[Mux.scala:50:70] wire _regout_T_21 = ~regout_wen_4; // @[Mux.scala:50:70] assign _regout_T_22 = _regout_T_21 & regout_en_4; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_23 = ~regout_wen_4; // @[Mux.scala:50:70] wire _regout_T_24 = _regout_T_23 & regout_en_4; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_4; // @[BankedStore.scala:172:47] reg [31:0] regout_r_4; // @[BankedStore.scala:172:14] wire [31:0] regout_4 = regout_r_4; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_41 = sourceC_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_45 = _regout_en_T_41; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_42 = sinkD_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_43 = sourceD_wreq_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_44 = sourceD_rreq_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_46 = _regout_en_T_45 | _regout_en_T_42; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_47 = _regout_en_T_46 | _regout_en_T_43; // @[BankedStore.scala:165:{32,45}] wire regout_en_5 = _regout_en_T_47 | _regout_en_T_44; // @[BankedStore.scala:165:{32,45}] wire regout_sel_1_5 = sourceC_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_5 = sinkD_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_5 = sourceD_wreq_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_15 = regout_sel_3_5; // @[Mux.scala:50:70] wire regout_sel_4_5 = sourceD_rreq_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_16 = regout_sel_2_5 | _regout_wen_T_15; // @[Mux.scala:50:70] wire _regout_wen_T_17 = ~regout_sel_1_5 & _regout_wen_T_16; // @[Mux.scala:50:70] wire regout_wen_5 = _regout_wen_T_17; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_15 = regout_sel_3_5 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_16 = regout_sel_2_5 ? sinkD_req_index : _regout_idx_T_15; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_17 = regout_sel_1_5 ? sourceC_req_index : _regout_idx_T_16; // @[Mux.scala:50:70] assign regout_idx_5 = _regout_idx_T_17; // @[Mux.scala:50:70] assign _regout_WIRE_5 = regout_idx_5; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_15 = regout_sel_3_5 ? sourceD_wreq_data_5 : 32'h0; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_16 = regout_sel_2_5 ? sinkD_req_data_5 : _regout_data_T_15; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_17 = regout_sel_1_5 ? 32'h0 : _regout_data_T_16; // @[Mux.scala:50:70] wire [31:0] regout_data_5 = _regout_data_T_17; // @[Mux.scala:50:70] assign _regout_T_25 = regout_wen_5 & regout_en_5; // @[Mux.scala:50:70] wire _regout_T_26 = ~regout_wen_5; // @[Mux.scala:50:70] assign _regout_T_27 = _regout_T_26 & regout_en_5; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_28 = ~regout_wen_5; // @[Mux.scala:50:70] wire _regout_T_29 = _regout_T_28 & regout_en_5; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_5; // @[BankedStore.scala:172:47] reg [31:0] regout_r_5; // @[BankedStore.scala:172:14] wire [31:0] regout_5 = regout_r_5; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_49 = sourceC_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_53 = _regout_en_T_49; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_50 = sinkD_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_51 = sourceD_wreq_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_52 = sourceD_rreq_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_54 = _regout_en_T_53 | _regout_en_T_50; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_55 = _regout_en_T_54 | _regout_en_T_51; // @[BankedStore.scala:165:{32,45}] wire regout_en_6 = _regout_en_T_55 | _regout_en_T_52; // @[BankedStore.scala:165:{32,45}] wire regout_sel_1_6 = sourceC_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_6 = sinkD_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_6 = sourceD_wreq_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_18 = regout_sel_3_6; // @[Mux.scala:50:70] wire regout_sel_4_6 = sourceD_rreq_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_19 = regout_sel_2_6 | _regout_wen_T_18; // @[Mux.scala:50:70] wire _regout_wen_T_20 = ~regout_sel_1_6 & _regout_wen_T_19; // @[Mux.scala:50:70] wire regout_wen_6 = _regout_wen_T_20; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_18 = regout_sel_3_6 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_19 = regout_sel_2_6 ? sinkD_req_index : _regout_idx_T_18; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_20 = regout_sel_1_6 ? sourceC_req_index : _regout_idx_T_19; // @[Mux.scala:50:70] assign regout_idx_6 = _regout_idx_T_20; // @[Mux.scala:50:70] assign _regout_WIRE_6 = regout_idx_6; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_18 = regout_sel_3_6 ? sourceD_wreq_data_6 : 32'h0; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_19 = regout_sel_2_6 ? sinkD_req_data_6 : _regout_data_T_18; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_20 = regout_sel_1_6 ? 32'h0 : _regout_data_T_19; // @[Mux.scala:50:70] wire [31:0] regout_data_6 = _regout_data_T_20; // @[Mux.scala:50:70] assign _regout_T_30 = regout_wen_6 & regout_en_6; // @[Mux.scala:50:70] wire _regout_T_31 = ~regout_wen_6; // @[Mux.scala:50:70] assign _regout_T_32 = _regout_T_31 & regout_en_6; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_33 = ~regout_wen_6; // @[Mux.scala:50:70] wire _regout_T_34 = _regout_T_33 & regout_en_6; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_6; // @[BankedStore.scala:172:47] reg [31:0] regout_r_6; // @[BankedStore.scala:172:14] wire [31:0] regout_6 = regout_r_6; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_57 = sourceC_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_61 = _regout_en_T_57; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_58 = sinkD_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_59 = sourceD_wreq_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_60 = sourceD_rreq_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_62 = _regout_en_T_61 | _regout_en_T_58; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_63 = _regout_en_T_62 | _regout_en_T_59; // @[BankedStore.scala:165:{32,45}] wire regout_en_7 = _regout_en_T_63 | _regout_en_T_60; // @[BankedStore.scala:165:{32,45}] wire regout_sel_1_7 = sourceC_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_7 = sinkD_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_7 = sourceD_wreq_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_21 = regout_sel_3_7; // @[Mux.scala:50:70] wire regout_sel_4_7 = sourceD_rreq_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_22 = regout_sel_2_7 | _regout_wen_T_21; // @[Mux.scala:50:70] wire _regout_wen_T_23 = ~regout_sel_1_7 & _regout_wen_T_22; // @[Mux.scala:50:70] wire regout_wen_7 = _regout_wen_T_23; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_21 = regout_sel_3_7 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_22 = regout_sel_2_7 ? sinkD_req_index : _regout_idx_T_21; // @[Mux.scala:50:70] wire [13:0] _regout_idx_T_23 = regout_sel_1_7 ? sourceC_req_index : _regout_idx_T_22; // @[Mux.scala:50:70] assign regout_idx_7 = _regout_idx_T_23; // @[Mux.scala:50:70] assign _regout_WIRE_7 = regout_idx_7; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_21 = regout_sel_3_7 ? sourceD_wreq_data_7 : 32'h0; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_22 = regout_sel_2_7 ? sinkD_req_data_7 : _regout_data_T_21; // @[Mux.scala:50:70] wire [31:0] _regout_data_T_23 = regout_sel_1_7 ? 32'h0 : _regout_data_T_22; // @[Mux.scala:50:70] wire [31:0] regout_data_7 = _regout_data_T_23; // @[Mux.scala:50:70] assign _regout_T_35 = regout_wen_7 & regout_en_7; // @[Mux.scala:50:70] wire _regout_T_36 = ~regout_wen_7; // @[Mux.scala:50:70] assign _regout_T_37 = _regout_T_36 & regout_en_7; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_38 = ~regout_wen_7; // @[Mux.scala:50:70] wire _regout_T_39 = _regout_T_38 & regout_en_7; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_7; // @[BankedStore.scala:172:47] reg [31:0] regout_r_7; // @[BankedStore.scala:172:14] wire [31:0] regout_7 = regout_r_7; // @[BankedStore.scala:164:23, :172:14] reg [7:0] regsel_sourceC_REG; // @[BankedStore.scala:175:39] reg [7:0] regsel_sourceC; // @[BankedStore.scala:175:31] reg [7:0] regsel_sourceD_REG; // @[BankedStore.scala:176:39] reg [7:0] regsel_sourceD; // @[BankedStore.scala:176:31] wire _decodeC_T = regsel_sourceC[0]; // @[BankedStore.scala:175:31, :179:38] wire [31:0] _decodeC_T_1 = _decodeC_T ? regout_0 : 32'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_2 = regsel_sourceC[1]; // @[BankedStore.scala:175:31, :179:38] wire [31:0] _decodeC_T_3 = _decodeC_T_2 ? regout_1 : 32'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_4 = regsel_sourceC[2]; // @[BankedStore.scala:175:31, :179:38] wire [31:0] _decodeC_T_5 = _decodeC_T_4 ? regout_2 : 32'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_6 = regsel_sourceC[3]; // @[BankedStore.scala:175:31, :179:38] wire [31:0] _decodeC_T_7 = _decodeC_T_6 ? regout_3 : 32'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_8 = regsel_sourceC[4]; // @[BankedStore.scala:175:31, :179:38] wire [31:0] _decodeC_T_9 = _decodeC_T_8 ? regout_4 : 32'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_10 = regsel_sourceC[5]; // @[BankedStore.scala:175:31, :179:38] wire [31:0] _decodeC_T_11 = _decodeC_T_10 ? regout_5 : 32'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_12 = regsel_sourceC[6]; // @[BankedStore.scala:175:31, :179:38] wire [31:0] _decodeC_T_13 = _decodeC_T_12 ? regout_6 : 32'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_14 = regsel_sourceC[7]; // @[BankedStore.scala:175:31, :179:38] wire [31:0] _decodeC_T_15 = _decodeC_T_14 ? regout_7 : 32'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire [31:0] _decodeC_T_16 = _decodeC_T_1 | _decodeC_T_5; // @[BankedStore.scala:179:23, :180:85] wire [31:0] _decodeC_T_17 = _decodeC_T_16 | _decodeC_T_9; // @[BankedStore.scala:179:23, :180:85] wire [31:0] decodeC_0 = _decodeC_T_17 | _decodeC_T_13; // @[BankedStore.scala:179:23, :180:85] wire [31:0] _decodeC_T_18 = _decodeC_T_3 | _decodeC_T_7; // @[BankedStore.scala:179:23, :180:85] wire [31:0] _decodeC_T_19 = _decodeC_T_18 | _decodeC_T_11; // @[BankedStore.scala:179:23, :180:85] wire [31:0] decodeC_1 = _decodeC_T_19 | _decodeC_T_15; // @[BankedStore.scala:179:23, :180:85] assign _io_sourceC_dat_data_T = {decodeC_1, decodeC_0}; // @[BankedStore.scala:180:85, :182:29] assign io_sourceC_dat_data_0 = _io_sourceC_dat_data_T; // @[BankedStore.scala:59:7, :182:29] wire _decodeD_T = regsel_sourceD[0]; // @[BankedStore.scala:176:31, :186:38] wire [31:0] _decodeD_T_1 = _decodeD_T ? regout_0 : 32'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_2 = regsel_sourceD[1]; // @[BankedStore.scala:176:31, :186:38] wire [31:0] _decodeD_T_3 = _decodeD_T_2 ? regout_1 : 32'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_4 = regsel_sourceD[2]; // @[BankedStore.scala:176:31, :186:38] wire [31:0] _decodeD_T_5 = _decodeD_T_4 ? regout_2 : 32'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_6 = regsel_sourceD[3]; // @[BankedStore.scala:176:31, :186:38] wire [31:0] _decodeD_T_7 = _decodeD_T_6 ? regout_3 : 32'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_8 = regsel_sourceD[4]; // @[BankedStore.scala:176:31, :186:38] wire [31:0] _decodeD_T_9 = _decodeD_T_8 ? regout_4 : 32'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_10 = regsel_sourceD[5]; // @[BankedStore.scala:176:31, :186:38] wire [31:0] _decodeD_T_11 = _decodeD_T_10 ? regout_5 : 32'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_12 = regsel_sourceD[6]; // @[BankedStore.scala:176:31, :186:38] wire [31:0] _decodeD_T_13 = _decodeD_T_12 ? regout_6 : 32'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_14 = regsel_sourceD[7]; // @[BankedStore.scala:176:31, :186:38] wire [31:0] _decodeD_T_15 = _decodeD_T_14 ? regout_7 : 32'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire [31:0] _decodeD_T_16 = _decodeD_T_1 | _decodeD_T_3; // @[BankedStore.scala:186:23, :187:85] wire [31:0] _decodeD_T_17 = _decodeD_T_16 | _decodeD_T_5; // @[BankedStore.scala:186:23, :187:85] wire [31:0] _decodeD_T_18 = _decodeD_T_17 | _decodeD_T_7; // @[BankedStore.scala:186:23, :187:85] wire [31:0] _decodeD_T_19 = _decodeD_T_18 | _decodeD_T_9; // @[BankedStore.scala:186:23, :187:85] wire [31:0] _decodeD_T_20 = _decodeD_T_19 | _decodeD_T_11; // @[BankedStore.scala:186:23, :187:85] wire [31:0] _decodeD_T_21 = _decodeD_T_20 | _decodeD_T_13; // @[BankedStore.scala:186:23, :187:85] assign decodeD_0 = _decodeD_T_21 | _decodeD_T_15; // @[BankedStore.scala:186:23, :187:85] assign io_sourceD_rdat_data_0 = decodeD_0; // @[BankedStore.scala:59:7, :187:85] always @(posedge clock) begin // @[BankedStore.scala:59:7] regout_REG <= _regout_T_4; // @[BankedStore.scala:172:{47,53}] if (regout_REG) // @[BankedStore.scala:172:47] regout_r <= _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_1 <= _regout_T_9; // @[BankedStore.scala:172:{47,53}] if (regout_REG_1) // @[BankedStore.scala:172:47] regout_r_1 <= _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_2 <= _regout_T_14; // @[BankedStore.scala:172:{47,53}] if (regout_REG_2) // @[BankedStore.scala:172:47] regout_r_2 <= _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_3 <= _regout_T_19; // @[BankedStore.scala:172:{47,53}] if (regout_REG_3) // @[BankedStore.scala:172:47] regout_r_3 <= _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_4 <= _regout_T_24; // @[BankedStore.scala:172:{47,53}] if (regout_REG_4) // @[BankedStore.scala:172:47] regout_r_4 <= _cc_banks_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_5 <= _regout_T_29; // @[BankedStore.scala:172:{47,53}] if (regout_REG_5) // @[BankedStore.scala:172:47] regout_r_5 <= _cc_banks_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_6 <= _regout_T_34; // @[BankedStore.scala:172:{47,53}] if (regout_REG_6) // @[BankedStore.scala:172:47] regout_r_6 <= _cc_banks_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_7 <= _regout_T_39; // @[BankedStore.scala:172:{47,53}] if (regout_REG_7) // @[BankedStore.scala:172:47] regout_r_7 <= _cc_banks_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] regsel_sourceC_REG <= sourceC_req_bankEn; // @[BankedStore.scala:128:19, :175:39] regsel_sourceC <= regsel_sourceC_REG; // @[BankedStore.scala:175:{31,39}] regsel_sourceD_REG <= sourceD_rreq_bankEn; // @[BankedStore.scala:128:19, :176:39] regsel_sourceD <= regsel_sourceD_REG; // @[BankedStore.scala:176:{31,39}] always @(posedge) cc_banks_0 cc_banks_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T ? regout_idx : _regout_WIRE), // @[Mux.scala:50:70] .RW0_en (_regout_T_2 | _regout_T), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen), // @[Mux.scala:50:70] .RW0_wdata (regout_data), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_0_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_1 cc_banks_1 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_5 ? regout_idx_1 : _regout_WIRE_1), // @[Mux.scala:50:70] .RW0_en (_regout_T_7 | _regout_T_5), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_1), // @[Mux.scala:50:70] .RW0_wdata (regout_data_1), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_1_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_2 cc_banks_2 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_10 ? regout_idx_2 : _regout_WIRE_2), // @[Mux.scala:50:70] .RW0_en (_regout_T_12 | _regout_T_10), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_2), // @[Mux.scala:50:70] .RW0_wdata (regout_data_2), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_2_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_3 cc_banks_3 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_15 ? regout_idx_3 : _regout_WIRE_3), // @[Mux.scala:50:70] .RW0_en (_regout_T_17 | _regout_T_15), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_3), // @[Mux.scala:50:70] .RW0_wdata (regout_data_3), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_3_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_4 cc_banks_4 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_20 ? regout_idx_4 : _regout_WIRE_4), // @[Mux.scala:50:70] .RW0_en (_regout_T_22 | _regout_T_20), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_4), // @[Mux.scala:50:70] .RW0_wdata (regout_data_4), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_4_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_5 cc_banks_5 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_25 ? regout_idx_5 : _regout_WIRE_5), // @[Mux.scala:50:70] .RW0_en (_regout_T_27 | _regout_T_25), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_5), // @[Mux.scala:50:70] .RW0_wdata (regout_data_5), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_5_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_6 cc_banks_6 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_30 ? regout_idx_6 : _regout_WIRE_6), // @[Mux.scala:50:70] .RW0_en (_regout_T_32 | _regout_T_30), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_6), // @[Mux.scala:50:70] .RW0_wdata (regout_data_6), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_6_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_7 cc_banks_7 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_35 ? regout_idx_7 : _regout_WIRE_7), // @[Mux.scala:50:70] .RW0_en (_regout_T_37 | _regout_T_35), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_7), // @[Mux.scala:50:70] .RW0_wdata (regout_data_7), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_7_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] assign io_sinkD_adr_ready = io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceC_adr_ready = io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceC_dat_data = io_sourceC_dat_data_0; // @[BankedStore.scala:59:7] assign io_sourceD_radr_ready = io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceD_rdat_data = io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7] assign io_sourceD_wadr_ready = io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File BaseTile.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util.{log2Ceil, log2Up} import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.bundlebridge._ import freechips.rocketchip.resources.{PropertyMap, PropertyOption, ResourceReference, DTSTimebase} import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode} import freechips.rocketchip.rocket.{ICacheParams, DCacheParams, BTBParams, ASIdBits, VMIdBits, TraceAux, BPWatch} import freechips.rocketchip.subsystem.{ HierarchicalElementParams, InstantiableHierarchicalElementParams, HierarchicalElementCrossingParamsLike, CacheBlockBytes, SystemBusKey, BaseHierarchicalElement, InsertTimingClosureRegistersOnHartIds, BaseHierarchicalElementModuleImp } import freechips.rocketchip.tilelink.{TLEphemeralNode, TLOutwardNode, TLNode, TLFragmenter, EarlyAck, TLWidthWidget, TLManagerParameters, ManagerUnification} import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters} import freechips.rocketchip.util.{TraceCoreParams, TraceCoreInterface} import freechips.rocketchip.resources.{BigIntToProperty, IntToProperty, StringToProperty} import freechips.rocketchip.util.BooleanToAugmentedBoolean case object TileVisibilityNodeKey extends Field[TLEphemeralNode] case object TileKey extends Field[TileParams] case object LookupByHartId extends Field[LookupByHartIdImpl] trait TileParams extends HierarchicalElementParams { val core: CoreParams val icache: Option[ICacheParams] val dcache: Option[DCacheParams] val btb: Option[BTBParams] val tileId: Int // may not be hartid val blockerCtrlAddr: Option[BigInt] } abstract class InstantiableTileParams[TileType <: BaseTile] extends InstantiableHierarchicalElementParams[TileType] with TileParams { def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl) (implicit p: Parameters): TileType } /** These parameters values are not computed based on diplomacy negotiation * and so are safe to use while diplomacy itself is running. */ trait HasNonDiplomaticTileParameters { implicit val p: Parameters def tileParams: TileParams = p(TileKey) def usingVM: Boolean = tileParams.core.useVM def usingUser: Boolean = tileParams.core.useUser || usingSupervisor def usingSupervisor: Boolean = tileParams.core.hasSupervisorMode def usingHypervisor: Boolean = usingVM && tileParams.core.useHypervisor def usingDebug: Boolean = tileParams.core.useDebug def usingRoCC: Boolean = !p(BuildRoCC).isEmpty def usingBTB: Boolean = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0 def usingPTW: Boolean = usingVM def usingDataScratchpad: Boolean = tileParams.dcache.flatMap(_.scratch).isDefined def xLen: Int = tileParams.core.xLen def xBytes: Int = xLen / 8 def iLen: Int = 32 def pgIdxBits: Int = 12 def pgLevelBits: Int = 10 - log2Ceil(xLen / 32) def pgLevels: Int = tileParams.core.pgLevels def maxSVAddrBits: Int = pgIdxBits + pgLevels * pgLevelBits def maxHypervisorExtraAddrBits: Int = 2 def hypervisorExtraAddrBits: Int = { if (usingHypervisor) maxHypervisorExtraAddrBits else 0 } def maxHVAddrBits: Int = maxSVAddrBits + hypervisorExtraAddrBits def minPgLevels: Int = { val res = xLen match { case 32 => 2; case 64 => 3 } require(pgLevels >= res) res } def asIdBits: Int = p(ASIdBits) def vmIdBits: Int = p(VMIdBits) lazy val maxPAddrBits: Int = { require(xLen == 32 || xLen == 64, s"Only XLENs of 32 or 64 are supported, but got $xLen") xLen match { case 32 => 34; case 64 => 56 } } def tileId: Int = tileParams.tileId def cacheBlockBytes = p(CacheBlockBytes) def lgCacheBlockBytes = log2Up(cacheBlockBytes) def masterPortBeatBytes = p(SystemBusKey).beatBytes // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt // TODO merge with isaString in CSR.scala def isaDTS: String = { val ie = if (tileParams.core.useRVE) "e" else "i" val m = if (tileParams.core.mulDiv.nonEmpty) "m" else "" val a = if (tileParams.core.useAtomics) "a" else "" val f = if (tileParams.core.fpu.nonEmpty) "f" else "" val d = if (tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen > 32) "d" else "" val c = if (tileParams.core.useCompressed) "c" else "" val b = if (tileParams.core.useBitmanip) "b" else "" val v = if (tileParams.core.useVector && tileParams.core.vLen >= 128 && tileParams.core.eLen == 64 && tileParams.core.vfLen == 64) "v" else "" val h = if (usingHypervisor) "h" else "" val ext_strs = Seq( (tileParams.core.useVector) -> s"zvl${tileParams.core.vLen}b", (tileParams.core.useVector) -> { val c = tileParams.core.vfLen match { case 64 => "d" case 32 => "f" case 0 => "x" } s"zve${tileParams.core.eLen}$c" }, (tileParams.core.useVector && tileParams.core.vfh) -> "zvfh", (tileParams.core.fpu.map(_.fLen >= 16).getOrElse(false) && tileParams.core.minFLen <= 16) -> "zfh", (tileParams.core.useZba) -> "zba", (tileParams.core.useZbb) -> "zbb", (tileParams.core.useZbs) -> "zbs", (tileParams.core.useConditionalZero) -> "zicond" ).filter(_._1).map(_._2) val multiLetterExt = ( // rdcycle[h], rdinstret[h] is implemented // rdtime[h] is not implemented, and could be provided by software emulation // see https://github.com/chipsalliance/rocket-chip/issues/3207 //Some(Seq("zicntr")) ++ Some(Seq("zicsr", "zifencei", "zihpm")) ++ Some(ext_strs) ++ Some(tileParams.core.vExts) ++ tileParams.core.customIsaExt.map(Seq(_)) ).flatten val multiLetterString = multiLetterExt.mkString("_") s"rv$xLen$ie$m$a$f$d$c$b$v$h$multiLetterString" } def tileProperties: PropertyMap = { val dcache = tileParams.dcache.filter(!_.scratch.isDefined).map(d => Map( "d-cache-block-size" -> cacheBlockBytes.asProperty, "d-cache-sets" -> d.nSets.asProperty, "d-cache-size" -> (d.nSets * d.nWays * cacheBlockBytes).asProperty) ).getOrElse(Nil) val incoherent = if (!tileParams.core.useAtomicsOnlyForIO) Nil else Map( "sifive,d-cache-incoherent" -> Nil) val icache = tileParams.icache.map(i => Map( "i-cache-block-size" -> cacheBlockBytes.asProperty, "i-cache-sets" -> i.nSets.asProperty, "i-cache-size" -> (i.nSets * i.nWays * cacheBlockBytes).asProperty) ).getOrElse(Nil) val dtlb = tileParams.dcache.filter(_ => tileParams.core.useVM).map(d => Map( "d-tlb-size" -> (d.nTLBWays * d.nTLBSets).asProperty, "d-tlb-sets" -> d.nTLBSets.asProperty)).getOrElse(Nil) val itlb = tileParams.icache.filter(_ => tileParams.core.useVM).map(i => Map( "i-tlb-size" -> (i.nTLBWays * i.nTLBSets).asProperty, "i-tlb-sets" -> i.nTLBSets.asProperty)).getOrElse(Nil) val mmu = if (tileParams.core.useVM) { if (tileParams.core.useHypervisor) { Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv${maxSVAddrBits},sv${maxSVAddrBits}x4".asProperty) } else { Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv$maxSVAddrBits".asProperty) } } else { Nil } val pmp = if (tileParams.core.nPMPs > 0) Map( "riscv,pmpregions" -> tileParams.core.nPMPs.asProperty, "riscv,pmpgranularity" -> tileParams.core.pmpGranularity.asProperty) else Nil dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ pmp ++ incoherent } } /** These parameters values are computed based on diplomacy negotiations * and so are NOT safe to use while diplomacy itself is running. * Only mix this trait into LazyModuleImps, Modules, Bundles, Data, etc. */ trait HasTileParameters extends HasNonDiplomaticTileParameters { protected def tlBundleParams = p(TileVisibilityNodeKey).edges.out.head.bundle lazy val paddrBits: Int = { val bits = tlBundleParams.addressBits require(bits <= maxPAddrBits, s"Requested $bits paddr bits, but since xLen is $xLen only $maxPAddrBits will fit") bits } def vaddrBits: Int = if (usingVM) { val v = maxHVAddrBits require(v == xLen || xLen > v && v > paddrBits) v } else { // since virtual addresses sign-extend but physical addresses // zero-extend, make room for a zero sign bit for physical addresses (paddrBits + 1) min xLen } def vpnBits: Int = vaddrBits - pgIdxBits def ppnBits: Int = paddrBits - pgIdxBits def vpnBitsExtended: Int = vpnBits + (if (vaddrBits < xLen) 1 + usingHypervisor.toInt else 0) def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits } /** Base class for all Tiles that use TileLink */ abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters) extends BaseHierarchicalElement(crossing)(q) with HasNonDiplomaticTileParameters { // Public constructor alters Parameters to supply some legacy compatibility keys def this(tileParams: TileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, p: Parameters) = { this(crossing, p.alterMap(Map( TileKey -> tileParams, TileVisibilityNodeKey -> TLEphemeralNode()(ValName("tile_master")), LookupByHartId -> lookup ))) } def intInwardNode: IntInwardNode // Interrupts to the core from external devices def intOutwardNode: Option[IntOutwardNode] // Interrupts from tile-internal devices (e.g. BEU) def haltNode: IntOutwardNode // Unrecoverable error has occurred; suggest reset def ceaseNode: IntOutwardNode // Tile has ceased to retire instructions def wfiNode: IntOutwardNode // Tile is waiting for an interrupt def module: BaseTileModuleImp[BaseTile] /** Node for broadcasting a hart id to diplomatic consumers within the tile. */ val hartIdNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) /** Node for consuming the hart id input in tile-layer Chisel logic. */ val hartIdSinkNode = BundleBridgeSink[UInt]() /** Node for driving a hart id input, which is to be broadcast to units within the tile. * * Making this id value an IO and then using it to do lookups of information * that would make otherwise-homogeneous tiles heterogeneous is a useful trick * to enable deduplication of tiles for hierarchical P&R flows. */ val hartIdNode: BundleBridgeInwardNode[UInt] = hartIdSinkNode := hartIdNexusNode := BundleBridgeNameNode("hartid") /** Node for broadcasting a reset vector to diplomatic consumers within the tile. */ val resetVectorNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt]() /** Node for consuming the reset vector input in tile-layer Chisel logic. * * Its width is sized by looking at the size of the address space visible * on the tile's master ports, but this lookup is not evaluated until * diplomacy has completed and Chisel elaboration has begun. */ val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(visiblePhysAddrBits.W))) /** Node for supplying a reset vector that processors in this tile might begin fetching instructions from as they come out of reset. */ val resetVectorNode: BundleBridgeInwardNode[UInt] = resetVectorSinkNode := resetVectorNexusNode := BundleBridgeNameNode("reset_vector") /** Nodes for connecting NMI interrupt sources and vectors into the tile */ val nmiSinkNode = Option.when(tileParams.core.useNMI) { BundleBridgeSink[NMI](Some(() => new NMI(visiblePhysAddrBits))) } val nmiNode: Option[BundleBridgeInwardNode[NMI]] = nmiSinkNode.map(_ := BundleBridgeNameNode("nmi")) /** Node for broadcasting an address prefix to diplomatic consumers within the tile. * * The prefix should be applied by consumers by or-ing ouputs of this node * with a static base address (which is looked up based on the driven hartid value). */ val mmioAddressPrefixNexusNode = BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = false) _, outputFn = BundleBridgeNexus.fillN[UInt](registered = false) _, default = Some(() => 0.U(1.W)) ) /** Node for external drivers to prefix base addresses of MMIO devices to which the core has a direct access path. */ val mmioAddressPrefixNode: BundleBridgeInwardNode[UInt] = mmioAddressPrefixNexusNode :=* BundleBridgeNameNode("mmio_address_prefix") // TODO: Any node marked "consumed by the core" or "driven by the core" // should be moved to either be: a member of a specific BaseTile subclass, // or actually just a member of the core's LazyModule itself, // assuming the core itself is diplomatic. // Then these nodes should just become IdentityNodes of their respective type protected def traceRetireWidth = tileParams.core.retireWidth /** Node for the core to drive legacy "raw" instruction trace. */ val traceSourceNode = BundleBridgeSource(() => new TraceBundle) /** Node for external consumers to source a legacy instruction trace from the core. */ val traceNode = traceSourceNode def traceCoreParams = new TraceCoreParams() /** Node for core to drive instruction trace conforming to RISC-V Processor Trace spec V1.0 */ val traceCoreSourceNode = BundleBridgeSource(() => new TraceCoreInterface(traceCoreParams)) /** Node for external consumers to source a V1.0 instruction trace from the core. */ val traceCoreNode = traceCoreSourceNode /** Node to broadcast collected trace sideband signals into the tile. */ val traceAuxNexusNode = BundleBridgeNexus[TraceAux](default = Some(() => { val aux = Wire(new TraceAux) aux.stall := false.B aux.enable := false.B aux })) /** Trace sideband signals to be consumed by the core. */ val traceAuxSinkNode = BundleBridgeSink[TraceAux]() /** Trace sideband signals collected here to be driven into the tile. */ val traceAuxNode: BundleBridgeInwardNode[TraceAux] = traceAuxSinkNode := traceAuxNexusNode :=* BundleBridgeNameNode("trace_aux") /** Node for watchpoints to control trace driven by core. */ val bpwatchSourceNode = BundleBridgeSource(() => Vec(tileParams.core.nBreakpoints, new BPWatch(traceRetireWidth))) /** Node to broadcast watchpoints to control trace. */ val bpwatchNexusNode = BundleBroadcast[Vec[BPWatch]]() /** Node for external consumers to source watchpoints to control trace. */ val bpwatchNode: BundleBridgeOutwardNode[Vec[BPWatch]] = BundleBridgeNameNode("bpwatch") :*= bpwatchNexusNode := bpwatchSourceNode /** Helper function for connecting MMIO devices inside the tile to an xbar that will make them visible to external masters. */ def connectTLSlave(xbarNode: TLOutwardNode, node: TLNode, bytes: Int): Unit = { DisableMonitors { implicit p => (Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls)) ++ (xBytes != bytes).option(TLWidthWidget(xBytes))) .foldRight(xbarNode)(_ :*= _) } } def connectTLSlave(node: TLNode, bytes: Int): Unit = { connectTLSlave(tlSlaveXbar.node, node, bytes) } /** TileLink node which represents the view that the intra-tile masters have of the rest of the system. */ val visibilityNode = p(TileVisibilityNodeKey) protected def visibleManagers = visibilityNode.edges.out.flatMap(_.manager.managers) protected def visiblePhysAddrBits = visibilityNode.edges.out.head.bundle.addressBits def unifyManagers: List[TLManagerParameters] = ManagerUnification(visibleManagers) /** Finds resource labels for all the outward caches. */ def nextLevelCacheProperty: PropertyOption = { val outer = visibleManagers .filter(_.supportsAcquireB) .flatMap(_.resources.headOption) .map(_.owner.label) .distinct if (outer.isEmpty) None else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList) } /** Create a DTS representation of this "cpu". */ def cpuProperties: PropertyMap = Map( "device_type" -> "cpu".asProperty, "status" -> "okay".asProperty, "clock-frequency" -> tileParams.core.bootFreqHz.asProperty, "riscv,isa" -> isaDTS.asProperty, "timebase-frequency" -> p(DTSTimebase).asProperty, "hardware-exec-breakpoint-count" -> tileParams.core.nBreakpoints.asProperty ) /** Can be used to access derived params calculated by HasCoreParameters * * However, callers must ensure they do not access a diplomatically-determined parameter * before the graph in question has been fully connected. */ protected lazy val lazyCoreParamsView: HasCoreParameters = { class C(implicit val p: Parameters) extends HasCoreParameters new C } this.suggestName(tileParams.baseName) } abstract class BaseTileModuleImp[+L <: BaseTile](outer: L) extends BaseHierarchicalElementModuleImp[L](outer) File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined || nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined || nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBits*rowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /** Bundle definitions for HellaCache interfaces */ trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /** Base classes for Diplomatic TL2 HellaCaches */ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated */ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /** Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File Interrupts.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.resources.{Device, DeviceSnippet, Description, ResourceBinding, ResourceInt} import freechips.rocketchip.interrupts.{IntIdentityNode, IntSinkNode, IntSinkPortSimple, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.util.CanHaveErrors import freechips.rocketchip.resources.{IntToProperty, StringToProperty} import freechips.rocketchip.util.BooleanToAugmentedBoolean class NMI(val w: Int) extends Bundle { val rnmi = Bool() val rnmi_interrupt_vector = UInt(w.W) val rnmi_exception_vector = UInt(w.W) } class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { val debug = Bool() val mtip = Bool() val msip = Bool() val meip = Bool() val seip = usingSupervisor.option(Bool()) val lip = Vec(coreParams.nLocalInterrupts, Bool()) val nmi = usingNMI.option(new NMI(resetVectorLen)) } // Use diplomatic interrupts to external interrupts from the subsystem into the tile trait SinksExternalInterrupts { this: BaseTile => val intInwardNode = intXbar.intnode :=* IntIdentityNode()(ValName("int_local")) protected val intSinkNode = IntSinkNode(IntSinkPortSimple()) intSinkNode := intXbar.intnode def cpuDevice: Device val intcDevice = new DeviceSnippet { override def parent = Some(cpuDevice) def describe(): Description = { Description("interrupt-controller", Map( "compatible" -> "riscv,cpu-intc".asProperty, "interrupt-controller" -> Nil, "#interrupt-cells" -> 1.asProperty)) } } ResourceBinding { intSinkNode.edges.in.flatMap(_.source.sources).map { case s => for (i <- s.range.start until s.range.end) { csrIntMap.lift(i).foreach { j => s.resources.foreach { r => r.bind(intcDevice, ResourceInt(j)) } } } } } // TODO: the order of the following two functions must match, and // also match the order which things are connected to the // per-tile crossbar in subsystem.HasTiles.connectInterrupts // debug, msip, mtip, meip, seip, lip offsets in CSRs def csrIntMap: List[Int] = { val nlips = tileParams.core.nLocalInterrupts val seip = if (usingSupervisor) Seq(9) else Nil List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16) } // go from flat diplomatic Interrupts to bundled TileInterrupts def decodeCoreInterrupts(core: TileInterrupts): Unit = { val async_ips = Seq(core.debug) val periph_ips = Seq( core.msip, core.mtip, core.meip) val seip = if (core.seip.isDefined) Seq(core.seip.get) else Nil val core_ips = core.lip val (interrupts, _) = intSinkNode.in(0) (async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i } } } trait SourcesExternalNotifications { this: BaseTile => // Report unrecoverable error conditions val haltNode = IntSourceNode(IntSourcePortSimple()) def reportHalt(could_halt: Option[Bool]): Unit = { val (halt_and_catch_fire, _) = haltNode.out(0) halt_and_catch_fire(0) := could_halt.map(RegEnable(true.B, false.B, _)).getOrElse(false.B) } def reportHalt(errors: Seq[CanHaveErrors]): Unit = { reportHalt(errors.flatMap(_.uncorrectable).map(_.valid).reduceOption(_||_)) } // Report when the tile has ceased to retire instructions val ceaseNode = IntSourceNode(IntSourcePortSimple()) def reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8): Unit = { def waitForQuiescence(cease: Bool): Bool = { // don't report cease until signal is stable for longer than any pipeline depth val count = RegInit(0.U(log2Ceil(quiescenceCycles + 1).W)) val saturated = count >= quiescenceCycles.U when (!cease) { count := 0.U } when (cease && !saturated) { count := count + 1.U } saturated } val (cease, _) = ceaseNode.out(0) cease(0) := could_cease.map{ c => val cease = (waitForQuiescence(c)) // Test-Only Code -- val prev_cease = RegNext(cease, false.B) assert(!(prev_cease & !cease), "CEASE line can not glitch once raised") cease }.getOrElse(false.B) } // Report when the tile is waiting for an interrupt val wfiNode = IntSourceNode(IntSourcePortSimple()) def reportWFI(could_wfi: Option[Bool]): Unit = { val (wfi, _) = wfiNode.out(0) wfi(0) := could_wfi.map(RegNext(_, init=false.B)).getOrElse(false.B) } } File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File Frontend.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tile.{CoreBundle, BaseTile} import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut} import freechips.rocketchip.util.{ClockGate, ShiftQueue, property} import freechips.rocketchip.util.UIntToAugmentedUInt class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val speculative = Bool() } class FrontendExceptions extends Bundle { val pf = new Bundle { val inst = Bool() } val gf = new Bundle { val inst = Bool() } val ae = new Bundle { val inst = Bool() } } class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) { val btb = new BTBResp val pc = UInt(vaddrBitsExtended.W) // ID stage PC val data = UInt((fetchWidth * coreInstBits).W) val mask = Bits(fetchWidth.W) val xcpt = new FrontendExceptions val replay = Bool() } class FrontendPerfEvents extends Bundle { val acquire = Bool() val tlbMiss = Bool() } class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val might_request = Output(Bool()) val clock_enabled = Input(Bool()) val req = Valid(new FrontendReq) val sfence = Valid(new SFenceReq) val resp = Flipped(Decoupled(new FrontendResp)) val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W))) val gpa_is_pte = Input(Bool()) val btb_update = Valid(new BTBUpdate) val bht_update = Valid(new BHTUpdate) val ras_update = Valid(new RASUpdate) val flush_icache = Output(Bool()) val npc = Input(UInt(vaddrBitsExtended.W)) val perf = Input(new FrontendPerfEvents()) val progress = Output(Bool()) } class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) val icache = LazyModule(new ICache(icacheParams, tileId)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) } class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) { val cpu = Flipped(new FrontendIO()) val ptw = new TLBPTWIO() val errors = new ICacheErrors } class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasRocketCoreParameters with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) val fq = withReset(reset.asBool || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cpu.might_request io.cpu.clock_enabled := clock_en assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "icache_clock_gate") icache.clock := gated_clock icache.io.clock_enabled := clock_en withClock (gated_clock) { // entering gated-clock domain val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages))) val s1_valid = Reg(Bool()) val s2_valid = RegInit(false.B) val s0_fq_has_space = !fq.io.mask(fq.io.mask.getWidth-3) || (!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid || !s2_valid)) || (!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid)) val s0_valid = io.cpu.req.valid || s0_fq_has_space s1_valid := s0_valid val s1_pc = Reg(UInt(vaddrBitsExtended.W)) val s1_speculative = Reg(Bool()) val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector)) val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B val s2_btb_resp_bits = Reg(new BTBResp) val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken val s2_tlb_resp = Reg(tlb.io.resp.cloneType) val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst || s2_tlb_resp.gf.inst val s2_speculative = RegInit(false.B) val s2_partial_insn_valid = RegInit(false.B) val s2_partial_insn = Reg(UInt(coreInstBits.W)) val wrong_path = RegInit(false.B) val s1_base_pc = ~(~s1_pc | (fetchBytes - 1).U) val ntpc = s1_base_pc + fetchBytes.U val predicted_npc = WireDefault(ntpc) val predicted_taken = WireDefault(false.B) val s2_replay = Wire(Bool()) s2_replay := (s2_valid && !fq.io.enq.fire) || RegNext(s2_replay && !s0_valid, true.B) val npc = Mux(s2_replay, s2_pc, predicted_npc) s1_pc := io.cpu.npc // consider RVC fetches across blocks to be non-speculative if the first // part was non-speculative val s0_speculative = if (usingCompressed) s1_speculative || s2_valid && !s2_speculative || predicted_taken else true.B s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative)) val s2_redirect = WireDefault(io.cpu.req.valid) s2_valid := false.B when (!s2_replay) { s2_valid := !s2_redirect s2_pc := s1_pc s2_speculative := s1_speculative s2_tlb_resp := tlb.io.resp } val recent_progress_counter_init = 3.U val recent_progress_counter = RegInit(recent_progress_counter_init) val recent_progress = recent_progress_counter > 0.U when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U } when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init } val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress io.ptw <> tlb.io.ptw tlb.io.req.valid := s1_valid && !s2_replay tlb.io.req.bits.cmd := M_XRD // Frontend only reads tlb.io.req.bits.vaddr := s1_pc tlb.io.req.bits.passthrough := false.B tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth).U tlb.io.req.bits.prv := io.ptw.status.prv tlb.io.req.bits.v := io.ptw.status.v tlb.io.sfence := io.cpu.sfence tlb.io.kill := !s2_valid || s2_kill_speculative_tlb_refill icache.io.req.valid := s0_valid icache.io.req.bits.addr := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s2_vaddr := s2_pc icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill || s2_xcpt icache.io.s2_cacheable := s2_tlb_resp.cacheable icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) || (!s2_tlb_resp.miss && icache.io.s2_kill)) fq.io.enq.bits.pc := s2_pc io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)) fq.io.enq.bits.data := icache.io.resp.bits.data fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) fq.io.enq.bits.replay := (icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) fq.io.enq.bits.btb := s2_btb_resp_bits fq.io.enq.bits.btb.taken := s2_btb_taken fq.io.enq.bits.xcpt := s2_tlb_resp assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill)) when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B } if (usingBTB) { val btb = Module(new BTB) btb.io.flush := false.B btb.io.req.valid := false.B btb.io.req.bits.addr := s1_pc btb.io.btb_update := io.cpu.btb_update btb.io.bht_update := io.cpu.bht_update btb.io.ras_update.valid := false.B btb.io.ras_update.bits := DontCare btb.io.bht_advance.valid := false.B btb.io.bht_advance.bits := DontCare when (!s2_replay) { btb.io.req.valid := !s2_redirect s2_btb_resp_valid := btb.io.resp.valid s2_btb_resp_bits := btb.io.resp.bits } when (btb.io.resp.valid && btb.io.resp.bits.taken) { predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended) predicted_taken := true.B } val force_taken = io.ptw.customCSRs.bpmStatic when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B } when (force_taken) { btb.io.bht_update.valid := false.B } val s2_base_pc = ~(~s2_pc | (fetchBytes-1).U) val taken_idx = Wire(UInt()) val after_idx = Wire(UInt()) val useRAS = WireDefault(false.B) val updateBTB = WireDefault(false.B) // If !prevTaken, ras_update / bht_update is always invalid. taken_idx := DontCare after_idx := DontCare def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = { def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U val prevRVI = prevValid && !insnIsRVC(prevBits) val valid = fq.io.enq.bits.mask(idx) && !prevRVI val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx) val rvc = insnIsRVC(bits) val rviBits = Cat(bits, prevBits) val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0) val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0) val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0) val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15) val rviCall = (rviJALR || rviJump) && rviBits(7) val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL val rvcJump = bits === Instructions.C_J || rvcJAL val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt) val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7) val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U val rvcCall = rvcJAL || rvcJALR val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits)) val predict_taken = s2_btb_resp_bits.bht.taken || force_taken val taken = prevRVI && (rviJump || rviJALR || rviBranch && predict_taken) || valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && predict_taken) val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn) val predictJump = prevRVI && rviJump || valid && rvcJump val predictBranch = predict_taken && (prevRVI && rviBranch || valid && rvcBranch) when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) { // The BTB has predicted that the middle of an RVI instruction is // a branch! Flush the BTB and the pipeline. btb.io.flush := true.B fq.io.enq.bits.replay := true.B wrong_path := true.B ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path") } when (!prevTaken) { taken_idx := idx.U after_idx := (idx + 1).U btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn)) btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call, Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch, CFIType.jump))) when (!s2_btb_taken) { when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) { wrong_path := true.B } when (s2_valid && predictReturn) { useRAS := true.B } when (s2_valid && (predictBranch || predictJump)) { val pc = s2_base_pc | (idx*coreInstBytes).U val npc = if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm) else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm) predicted_npc := npc.asUInt } } when (prevRVI && rviBranch || valid && rvcBranch) { btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path btb.io.bht_advance.bits := s2_btb_resp_bits } when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken || predictJump || predictReturn)) { updateBTB := true.B } } if (idx == fetchWidth-1) { when (fq.io.enq.fire) { s2_partial_insn_valid := false.B when (valid && !prevTaken && !rvc) { s2_partial_insn_valid := true.B s2_partial_insn := bits | 0x3.U } } prevTaken || taken } else { scanInsns(idx + 1, valid, bits, prevTaken || taken) } } when (!io.cpu.btb_update.valid) { val fetch_bubble_likely = !fq.io.mask(1) btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U btb.io.btb_update.bits.isValid := true.B btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType btb.io.btb_update.bits.br_pc := s2_base_pc | (taken_idx << log2Ceil(coreInstBytes)) btb.io.btb_update.bits.pc := s2_base_pc } btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes)) val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B) when (useRAS) { predicted_npc := btb.io.ras_head.bits } when (fq.io.enq.fire && (s2_btb_taken || taken)) { s2_partial_insn_valid := false.B } when (!s2_btb_taken) { when (taken) { fq.io.enq.bits.btb.bridx := taken_idx fq.io.enq.bits.btb.taken := true.B fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U when (fq.io.enq.fire) { s2_redirect := true.B } } } assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0)) when (s2_redirect) { s2_partial_insn_valid := false.B } when (io.cpu.req.valid) { wrong_path := false.B } } io.cpu.resp <> fq.io.deq // supply guest physical address to commit stage val gpa_valid = Reg(Bool()) val gpa = Reg(UInt(vaddrBitsExtended.W)) val gpa_is_pte = Reg(Bool()) when (fq.io.enq.fire && s2_tlb_resp.gf.inst) { when (!gpa_valid) { gpa := s2_tlb_resp.gpa gpa_is_pte := s2_tlb_resp.gpa_is_pte } gpa_valid := true.B } when (io.cpu.req.valid) { gpa_valid := false.B } io.cpu.gpa.valid := gpa_valid io.cpu.gpa.bits := gpa io.cpu.gpa_is_pte := gpa_is_pte // performance events io.cpu.perf.acquire := icache.io.perf.acquire io.cpu.perf.tlbMiss := io.ptw.req.fire io.errors := icache.io.errors // gate the clock clock_en_reg := !rocketParams.clockGate.B || io.cpu.might_request || // chicken bit icache.io.keep_clock_enabled || // I$ miss or ITIM access s1_valid || s2_valid || // some fetch in flight !tlb.io.req.ready || // handling TLB miss !fq.io.mask(fq.io.mask.getWidth-1) // queue not full } // leaving gated-clock domain def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1).U) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc) } /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */ trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode } frontend.resetVectorSinkNode := resetVectorNexusNode nPTWPorts += 1 // This should be a None in the case of not having an ITIM address, when we // don't actually use the device that is instantiated in the frontend. private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None } trait HasICacheFrontendModule extends CanHavePTWModule { val outer: HasICacheFrontend ptwPorts += outer.frontend.module.io.ptw } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File HierarchicalElement.scala: package freechips.rocketchip.subsystem import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.interrupts.IntXbar import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType, ClockCrossingType} import freechips.rocketchip.tile.{LookupByHartIdImpl, TraceBundle} import freechips.rocketchip.tilelink.{TLNode, TLIdentityNode, TLXbar, TLBuffer, TLInwardNode, TLOutwardNode} trait HierarchicalElementParams { val baseName: String // duplicated instances shouuld share a base name val uniqueName: String val clockSinkParams: ClockSinkParameters } abstract class InstantiableHierarchicalElementParams[ElementType <: BaseHierarchicalElement] extends HierarchicalElementParams /** An interface for describing the parameteization of how HierarchicalElements are connected to interconnects */ trait HierarchicalElementCrossingParamsLike { /** The type of clock crossing that should be inserted at the element boundary. */ def crossingType: ClockCrossingType /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect master. */ def master: HierarchicalElementPortParamsLike /** Parameters describing the contents and behavior of the point where the element is attached as an interconnect slave. */ def slave: HierarchicalElementPortParamsLike /** The subnetwork location of the device selecting the apparent base address of MMIO devices inside the element */ def mmioBaseAddressPrefixWhere: TLBusWrapperLocation /** Inject a reset management subgraph that effects the element child reset only */ def resetCrossingType: ResetCrossingType /** Keep the element clock separate from the interconnect clock (e.g. even if they are synchronous to one another) */ def forceSeparateClockReset: Boolean } /** An interface for describing the parameterization of how a particular element port is connected to an interconnect */ trait HierarchicalElementPortParamsLike { /** The subnetwork location of the interconnect to which this element port should be connected. */ def where: TLBusWrapperLocation /** Allows port-specific adapters to be injected into the interconnect side of the attachment point. */ def injectNode(context: Attachable)(implicit p: Parameters): TLNode } abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implicit p: Parameters) extends LazyModule()(p) with CrossesToOnlyOneClockDomain { def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement] protected val tlOtherMastersNode = TLIdentityNode() protected val tlMasterXbar = LazyModule(new TLXbar(nameSuffix = Some(s"MasterXbar_$desiredName"))) protected val tlSlaveXbar = LazyModule(new TLXbar(nameSuffix = Some(s"SlaveXbar_$desiredName"))) protected val intXbar = LazyModule(new IntXbar) def masterNode: TLOutwardNode def slaveNode: TLInwardNode /** Helper function to insert additional buffers on master ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. */ def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) /** Helper function to insert additional buffers on slave ports at the boundary of the tile. * * The boundary buffering needed to cut feed-through paths is * microarchitecture specific, so this may need to be overridden * in subclasses of this class. */ def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none) } abstract class BaseHierarchicalElementModuleImp[+L <: BaseHierarchicalElement](val outer: L) extends LazyModuleImp(outer) File RocketTile.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker} import freechips.rocketchip.diplomacy.{ AddressSet, DisableMonitors, BufferParams } import freechips.rocketchip.resources.{ SimpleDevice, Description, ResourceAnchors, ResourceBindings, ResourceBinding, Resource, ResourceAddress, } import freechips.rocketchip.interrupts.IntIdentityNode import freechips.rocketchip.tilelink.{TLIdentityNode, TLBuffer} import freechips.rocketchip.rocket.{ RocketCoreParams, ICacheParams, DCacheParams, BTBParams, HasHellaCache, HasICacheFrontend, ScratchpadSlavePort, HasICacheFrontendModule, Rocket } import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike import freechips.rocketchip.prci.{ClockSinkParameters, RationalCrossing, ClockCrossingType} import freechips.rocketchip.util.{Annotated, InOrderArbiter} import freechips.rocketchip.util.BooleanToAugmentedBoolean case class RocketTileBoundaryBufferParams(force: Boolean = false) case class RocketTileParams( core: RocketCoreParams = RocketCoreParams(), icache: Option[ICacheParams] = Some(ICacheParams()), dcache: Option[DCacheParams] = Some(DCacheParams()), btb: Option[BTBParams] = Some(BTBParams()), dataScratchpadBytes: Int = 0, tileId: Int = 0, beuAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None, clockSinkParams: ClockSinkParameters = ClockSinkParameters(), boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None ) extends InstantiableTileParams[RocketTile] { require(icache.isDefined) require(dcache.isDefined) val baseName = "rockettile" val uniqueName = s"${baseName}_$tileId" def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = { new RocketTile(this, crossing, lookup) } } class RocketTile private( val rocketParams: RocketTileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters) extends BaseTile(rocketParams, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache with HasHellaCache with HasICacheFrontend { // Private constructor ensures altered LazyModule.p is used implicitly def this(params: RocketTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() } val slaveNode = TLIdentityNode() val masterNode = visibilityNode val dtim_adapter = tileParams.dcache.flatMap { d => d.scratch.map { s => LazyModule(new ScratchpadSlavePort(AddressSet.misaligned(s, d.dataScratchpadBytes), lazyCoreParamsView.coreDataBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)) }} dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes)) val bus_error_unit = rocketParams.beuAddr map { a => val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen/8)) intOutwardNode.get := beu.intNode connectTLSlave(beu.node, xBytes) beu } val tile_master_blocker = tileParams.blockerCtrlAddr .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)) .map(bp => LazyModule(new BasicBusBlocker(bp))) tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes)) // TODO: this doesn't block other masters, e.g. RoCCs tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } masterNode :=* tlOtherMastersNode DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode } nDCachePorts += 1 /*core */ + (dtim_adapter.isDefined).toInt + rocketParams.core.vector.map(_.useDCache.toInt).getOrElse(0) val dtimProperty = dtim_adapter.map(d => Map( "sifive,dtim" -> d.device.asProperty)).getOrElse(Nil) val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p)) val beuProperty = bus_error_unit.map(d => Map( "sifive,buserror" -> d.device.asProperty)).getOrElse(Nil) val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) { override def parent = Some(ResourceAnchors.cpus) override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty) } } val vector_unit = rocketParams.core.vector.map(v => LazyModule(v.build(p))) vector_unit.foreach(vu => tlMasterXbar.node :=* vu.atlNode) vector_unit.foreach(vu => tlOtherMastersNode :=* vu.tlNode) ResourceBinding { Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } override lazy val module = new RocketTileModuleImp(this) override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)) case _ => TLBuffer(BufferParams.none) } override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (rocketParams.boundaryBuffers, crossing) match { case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer() case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none) case _ => TLBuffer(BufferParams.none) } } class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer) with HasFpuOpt with HasLazyRoCCModule with HasICacheFrontendModule { Annotated.params(this, outer.rocketParams) val core = Module(new Rocket(outer)(outer.p)) outer.vector_unit.foreach { v => core.io.vector.get <> v.module.io.core v.module.io.tlb <> outer.dcache.module.io.tlb_port } // reset vector is connected in the Frontend to s2_pc core.io.reset_vector := DontCare // Report unrecoverable error conditions; for now the only cause is cache ECC errors outer.reportHalt(List(outer.dcache.module.io.errors)) // Report when the tile has ceased to retire instructions; for now the only cause is clock gating outer.reportCease(outer.rocketParams.core.clockGate.option( !outer.dcache.module.io.cpu.clock_enabled && !outer.frontend.module.io.cpu.clock_enabled && !ptw.io.dpath.clock_enabled && core.io.cease)) outer.reportWFI(Some(core.io.wfi)) outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt beu.module.io.errors.dcache := outer.dcache.module.io.errors beu.module.io.errors.icache := outer.frontend.module.io.errors } core.io.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.get.bundle } // Pass through various external constants and reports that were bundle-bridged into the tile outer.traceSourceNode.bundle <> core.io.trace core.io.traceStall := outer.traceAuxSinkNode.bundle.stall outer.bpwatchSourceNode.bundle <> core.io.bpwatch core.io.hartid := outer.hartIdSinkNode.bundle require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth, s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)") // Connect the core pipeline to other intra-tile modules outer.frontend.module.io.cpu <> core.io.imem dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ?? fpuOpt foreach { fpu => core.io.fpu :<>= fpu.io.waiveAs[FPUCoreIO](_.cp_req, _.cp_resp) } if (fpuOpt.isEmpty) { core.io.fpu := DontCare } outer.vector_unit foreach { v => if (outer.rocketParams.core.vector.get.useDCache) { dcachePorts += v.module.io.dmem } else { v.module.io.dmem := DontCare } } core.io.ptw <> ptw.io.dpath // Connect the coprocessor interfaces if (outer.roccs.size > 0) { cmdRouter.get.io.in <> core.io.rocc.cmd outer.roccs.foreach{ lm => lm.module.io.exception := core.io.rocc.exception lm.module.io.fpu_req.ready := DontCare lm.module.io.fpu_resp.valid := DontCare lm.module.io.fpu_resp.bits.data := DontCare lm.module.io.fpu_resp.bits.exc := DontCare } core.io.rocc.resp <> respArb.get.io.out core.io.rocc.busy <> (cmdRouter.get.io.busy || outer.roccs.map(_.module.io.busy).reduce(_ || _)) core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ || _) (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 <> t._1 } } else { // tie off core.io.rocc.cmd.ready := false.B core.io.rocc.resp.valid := false.B core.io.rocc.resp.bits := DontCare core.io.rocc.busy := DontCare core.io.rocc.interrupt := DontCare } // Dont care mem since not all RoCC need accessing memory core.io.rocc.mem := DontCare // Rocket has higher priority to DTIM than other TileLink clients outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem } // TODO eliminate this redundancy val h = dcachePorts.size val c = core.dcacheArbPorts val o = outer.nDCachePorts require(h == c, s"port list size was $h, core expected $c") require(h == o, s"port list size was $h, outer counted $o") // TODO figure out how to move the below into their respective mix-ins dcacheArb.io.requestor <> dcachePorts.toSeq ptw.io.requestor <> ptwPorts.toSeq } trait HasFpuOpt { this: RocketTileModuleImp => val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p))) fpuOpt.foreach { fpu => val nRoCCFPUPorts = outer.roccs.count(_.usesFPU) val nFPUPorts = nRoCCFPUPorts + outer.rocketParams.core.useVector.toInt if (nFPUPorts > 0) { val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts)) fpu.io.cp_req <> fpArb.io.out_req fpArb.io.out_resp <> fpu.io.cp_resp val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io) for (i <- 0 until nRoCCFPUPorts) { fpArb.io.in_req(i) <> fp_rocc_ios(i).fpu_req fp_rocc_ios(i).fpu_resp <> fpArb.io.in_resp(i) } outer.vector_unit.foreach(vu => { fpArb.io.in_req(nRoCCFPUPorts) <> vu.module.io.fp_req vu.module.io.fp_resp <> fpArb.io.in_resp(nRoCCFPUPorts) }) } else { fpu.io.cp_req.valid := false.B fpu.io.cp_req.bits := DontCare fpu.io.cp_resp.ready := false.B } } } File BundleBridgeNexus.scala: package org.chipsalliance.diplomacy.bundlebridge import chisel3.{chiselTypeOf, ActualDirection, Data, Reg} import chisel3.reflect.DataMirror import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyRawModuleImp} class BundleBridgeNexus[T <: Data]( inputFn: Seq[T] => T, outputFn: (T, Int) => Seq[T], default: Option[() => T] = None, inputRequiresOutput: Boolean = false, override val shouldBeInlined: Boolean = true )( implicit p: Parameters) extends LazyModule { val node = BundleBridgeNexusNode[T](default, inputRequiresOutput) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val defaultWireOpt = default.map(_()) val inputs: Seq[T] = node.in.map(_._1) inputs.foreach { i => require( DataMirror.checkTypeEquivalence(i, inputs.head), s"${node.context} requires all inputs have equivalent Chisel Data types, but got\n$i\nvs\n${inputs.head}" ) } inputs.flatMap(getElements).foreach { elt => DataMirror.directionOf(elt) match { case ActualDirection.Output => () case ActualDirection.Unspecified => () case _ => require(false, s"${node.context} can only be used with Output-directed Bundles") } } val outputs: Seq[T] = if (node.out.size > 0) { val broadcast: T = if (inputs.size >= 1) inputFn(inputs) else defaultWireOpt.get outputFn(broadcast, node.out.size) } else { Nil } val typeName = outputs.headOption.map(_.typeName).getOrElse("NoOutput") override def desiredName = s"BundleBridgeNexus_$typeName" node.out.map(_._1).foreach { o => require( DataMirror.checkTypeEquivalence(o, outputs.head), s"${node.context} requires all outputs have equivalent Chisel Data types, but got\n$o\nvs\n${outputs.head}" ) } require( outputs.size == node.out.size, s"${node.context} outputFn must generate one output wire per edgeOut, but got ${outputs.size} vs ${node.out.size}" ) node.out.zip(outputs).foreach { case ((out, _), bcast) => out := bcast } } } object BundleBridgeNexus { def safeRegNext[T <: Data](x: T): T = { val reg = Reg(chiselTypeOf(x)) reg := x reg } def requireOne[T <: Data](registered: Boolean)(seq: Seq[T]): T = { require(seq.size == 1, "BundleBroadcast default requires one input") if (registered) safeRegNext(seq.head) else seq.head } def orReduction[T <: Data](registered: Boolean)(seq: Seq[T]): T = { val x = seq.reduce((a, b) => (a.asUInt | b.asUInt).asTypeOf(seq.head)) if (registered) safeRegNext(x) else x } def fillN[T <: Data](registered: Boolean)(x: T, n: Int): Seq[T] = Seq.fill(n) { if (registered) safeRegNext(x) else x } def apply[T <: Data]( inputFn: Seq[T] => T = orReduction[T](false) _, outputFn: (T, Int) => Seq[T] = fillN[T](false) _, default: Option[() => T] = None, inputRequiresOutput: Boolean = false, shouldBeInlined: Boolean = true )( implicit p: Parameters ): BundleBridgeNexusNode[T] = { val nexus = LazyModule(new BundleBridgeNexus[T](inputFn, outputFn, default, inputRequiresOutput, shouldBeInlined)) nexus.node } }
module RocketTile_7( // @[RocketTile.scala:141:7] input clock, // @[RocketTile.scala:141:7] input reset, // @[RocketTile.scala:141:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input [2:0] auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] broadcast_2_auto_in_0_action; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_valid_0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _core_io_imem_might_request; // @[RocketTile.scala:147:20] wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_taken; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_mask; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bridx; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_prediction_target; // @[RocketTile.scala:147:20] wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_btb_update_bits_prediction_bht_history; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bht_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_target; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_prediction_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20] wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20] wire _core_io_imem_progress; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20] wire [6:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20] wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_no_resp; // @[RocketTile.scala:147:20] wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20] wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20] wire _core_io_dmem_keep_clock_enabled; // @[RocketTile.scala:147:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_ptw_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_status_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sd; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_mpp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spvp; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spv; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_gstatus_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sd; // @[RocketTile.scala:147:20] wire [22:0] _core_io_ptw_gstatus_zero2; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mbe; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sbe; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_sxl; // @[RocketTile.scala:147:20] wire [7:0] _core_io_ptw_gstatus_zero1; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_mpp; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_vs; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_ube; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_upie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_hie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_uie; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_value; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_hartid; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_time; // @[RocketTile.scala:147:20] wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20] wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20] wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20] wire _core_io_fpu_valid; // @[RocketTile.scala:147:20] wire _core_io_fpu_killx; // @[RocketTile.scala:147:20] wire _core_io_fpu_killm; // @[RocketTile.scala:147:20] wire _core_io_fpu_keep_clock_enabled; // @[RocketTile.scala:147:20] wire _core_io_wfi; // @[RocketTile.scala:147:20] wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_0_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_0_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sd; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sd; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_1_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_1_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19] wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19] wire _ptw_io_mem_req_bits_dv; // @[PTW.scala:802:19] wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_miss; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_hit; // @[PTW.scala:802:19] wire _ptw_io_dpath_clock_enabled; // @[PTW.scala:802:19] wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25] wire [6:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_resp; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_keep_clock_enabled; // @[HellaCache.scala:292:25] wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62] wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62] wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62] wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ldst; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap12; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap23; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagIn; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagOut; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fromint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_toint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fastpipe; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fma; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_div; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_sqrt; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wflags; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_vec; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62] wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_cfiType; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28] wire [38:0] _frontend_io_cpu_resp_bits_btb_target; // @[Frontend.scala:393:28] wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28] wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bht_value; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28] wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_valid; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_gpa_bits; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_is_pte; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_npc; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_acquire; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_tlbMiss; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28] wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack_cause_raw; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_uncached; // @[HellaCache.scala:278:43] wire [31:0] _dcache_io_cpu_s2_paddr; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala:278:43] wire [6:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43] wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_s2_gpa; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_acquire; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_tlbMiss; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_blocked; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[RocketTile.scala:141:7] wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[RocketTile.scala:141:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[RocketTile.scala:141:7] wire [2:0] auto_hartid_in_0 = auto_hartid_in; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_cease_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_halt_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[RocketTile.scala:141:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_in_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_out_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonOut_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonIn_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [31:0] auto_reset_vector_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorIn = 32'h10000; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire wfiNodeOut_0; // @[MixedNode.scala:542:17] wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[RocketTile.scala:141:7] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[RocketTile.scala:141:7] wire traceSourceNodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [2:0] traceSourceNodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17] wire [2:0] hartidIn = auto_hartid_in_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] wire auto_wfi_out_0_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] wire [2:0] auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] wire [2:0] hartidOut; // @[MixedNode.scala:542:17] wire [2:0] broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire [2:0] broadcast_nodeOut; // @[MixedNode.scala:542:17] wire [2:0] broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire [2:0] hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] wire broadcast_2_nodeIn_0_valid_0 = broadcast_2_auto_in_0_valid_0; // @[MixedNode.scala:551:17] wire [2:0] bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire [2:0] broadcast_2_nodeIn_0_action = broadcast_2_auto_in_0_action; // @[MixedNode.scala:551:17] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] tlOtherMastersNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] tlOtherMastersNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_b_ready = tlOtherMastersNodeOut_b_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_valid = tlOtherMastersNodeOut_c_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_valid = tlOtherMastersNodeOut_e_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17] assign buffer_auto_in_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] assign auto_trace_source_out_insns_0_valid_0 = traceSourceNodeOut_insns_0_valid; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr_0 = traceSourceNodeOut_insns_0_iaddr; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn_0 = traceSourceNodeOut_insns_0_insn; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv_0 = traceSourceNodeOut_insns_0_priv; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception_0 = traceSourceNodeOut_insns_0_exception; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt_0 = traceSourceNodeOut_insns_0_interrupt; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause_0 = traceSourceNodeOut_insns_0_cause; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval_0 = traceSourceNodeOut_insns_0_tval; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[RocketTile.scala:141:7] assign broadcast_2_auto_in_0_valid_0 = bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] assign broadcast_2_auto_in_0_action = bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4; // @[MixedNode.scala:551:17] assign auto_wfi_out_0_0 = wfiNodeOut_0; // @[RocketTile.scala:141:7] reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] assign wfiNodeOut_0 = wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] always @(posedge clock) begin // @[RocketTile.scala:141:7] if (reset) // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= 1'h0; // @[Interrupts.scala:131:36] else // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20] always @(posedge) TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c_7 tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready), .auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid), .auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param), .auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size), .auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied), .auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_a_ready (widget_auto_anon_out_a_ready), .auto_anon_in_0_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_valid (widget_auto_anon_out_b_valid), .auto_anon_in_0_b_bits_opcode (widget_auto_anon_out_b_bits_opcode), .auto_anon_in_0_b_bits_param (widget_auto_anon_out_b_bits_param), .auto_anon_in_0_b_bits_size (widget_auto_anon_out_b_bits_size), .auto_anon_in_0_b_bits_source (widget_auto_anon_out_b_bits_source), .auto_anon_in_0_b_bits_address (widget_auto_anon_out_b_bits_address), .auto_anon_in_0_b_bits_mask (widget_auto_anon_out_b_bits_mask), .auto_anon_in_0_b_bits_data (widget_auto_anon_out_b_bits_data), .auto_anon_in_0_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt), .auto_anon_in_0_c_ready (widget_auto_anon_out_c_ready), .auto_anon_in_0_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_valid (widget_auto_anon_out_d_valid), .auto_anon_in_0_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (widget_auto_anon_out_d_bits_param), .auto_anon_in_0_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_anon_in_0_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_anon_in_0_d_bits_sink (widget_auto_anon_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_anon_in_0_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_e_ready (widget_auto_anon_out_e_ready), .auto_anon_in_0_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9] .auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid), .auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_anon_out_b_ready (tlOtherMastersNodeIn_b_ready), .auto_anon_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17] .auto_anon_out_c_valid (tlOtherMastersNodeIn_c_valid), .auto_anon_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode), .auto_anon_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param), .auto_anon_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size), .auto_anon_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source), .auto_anon_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address), .auto_anon_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data), .auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready), .auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17] .auto_anon_out_e_valid (tlOtherMastersNodeIn_e_valid), .auto_anon_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink) ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u_7 tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i4_o1_7 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3), .auto_anon_out_4 (intSinkNodeIn_4) ); // @[HierarchicalElement.scala:57:37] DCache_7 dcache ( // @[HellaCache.scala:278:43] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_cpu_req_ready (_dcache_io_cpu_req_ready), .io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[HellaCache.scala:292:25] .io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[HellaCache.scala:292:25] .io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[HellaCache.scala:292:25] .io_cpu_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), // @[HellaCache.scala:292:25] .io_cpu_req_bits_size (_dcacheArb_io_mem_req_bits_size), // @[HellaCache.scala:292:25] .io_cpu_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[HellaCache.scala:292:25] .io_cpu_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), // @[HellaCache.scala:292:25] .io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[HellaCache.scala:292:25] .io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[HellaCache.scala:292:25] .io_cpu_s1_data_mask (8'h0), // @[RocketTile.scala:147:20] .io_cpu_s2_nack (_dcache_io_cpu_s2_nack), .io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), .io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached), .io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr), .io_cpu_resp_valid (_dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), .io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), .io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), .io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next (_dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa), .io_cpu_ordered (_dcache_io_cpu_ordered), .io_cpu_store_pending (_dcache_io_cpu_store_pending), .io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire), .io_cpu_perf_release (_dcache_io_cpu_perf_release), .io_cpu_perf_grant (_dcache_io_cpu_perf_grant), .io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), .io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked), .io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), .io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), .io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), .io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), .io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), .io_cpu_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled), // @[HellaCache.scala:292:25] .io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_dcache_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_0_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_0_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[HellaCache.scala:278:43] Frontend_7 frontend ( // @[Frontend.scala:393:28] .clock (clock), .reset (reset), .auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid), .auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address), .auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .io_cpu_might_request (_core_io_imem_might_request), // @[RocketTile.scala:147:20] .io_cpu_req_valid (_core_io_imem_req_valid), // @[RocketTile.scala:147:20] .io_cpu_req_bits_pc (_core_io_imem_req_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_req_bits_speculative (_core_io_imem_req_bits_speculative), // @[RocketTile.scala:147:20] .io_cpu_sfence_valid (_core_io_imem_sfence_valid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_addr (_core_io_imem_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_asid (_core_io_imem_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hv (_core_io_imem_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hg (_core_io_imem_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_cpu_resp_ready (_core_io_imem_resp_ready), // @[RocketTile.scala:147:20] .io_cpu_resp_valid (_frontend_io_cpu_resp_valid), .io_cpu_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), .io_cpu_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), .io_cpu_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), .io_cpu_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), .io_cpu_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), .io_cpu_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), .io_cpu_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), .io_cpu_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), .io_cpu_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), .io_cpu_resp_bits_data (_frontend_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), .io_cpu_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), .io_cpu_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), .io_cpu_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), .io_cpu_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), .io_cpu_gpa_valid (_frontend_io_cpu_gpa_valid), .io_cpu_gpa_bits (_frontend_io_cpu_gpa_bits), .io_cpu_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), .io_cpu_btb_update_valid (_core_io_imem_btb_update_valid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_target (_core_io_imem_btb_update_bits_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), // @[RocketTile.scala:147:20] .io_cpu_bht_update_valid (_core_io_imem_bht_update_valid), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), // @[RocketTile.scala:147:20] .io_cpu_flush_icache (_core_io_imem_flush_icache), // @[RocketTile.scala:147:20] .io_cpu_npc (_frontend_io_cpu_npc), .io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire), .io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), .io_cpu_progress (_core_io_imem_progress), // @[RocketTile.scala:147:20] .io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_frontend_io_ptw_req_valid), .io_ptw_req_bits_valid (_frontend_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_1_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[PTW.scala:802:19] .io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_1_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[Frontend.scala:393:28] TLFragmenter_7 fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset) ); // @[Fragmenter.scala:345:34] FPU_7 fpuOpt ( // @[RocketTile.scala:242:62] .clock (clock), .reset (reset), .io_hartid (_core_io_fpu_hartid), // @[RocketTile.scala:147:20] .io_time (_core_io_fpu_time), // @[RocketTile.scala:147:20] .io_inst (_core_io_fpu_inst), // @[RocketTile.scala:147:20] .io_fromint_data (_core_io_fpu_fromint_data), // @[RocketTile.scala:147:20] .io_fcsr_rm (_core_io_fpu_fcsr_rm), // @[RocketTile.scala:147:20] .io_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), .io_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), .io_store_data (_fpuOpt_io_store_data), .io_toint_data (_fpuOpt_io_toint_data), .io_ll_resp_val (_core_io_fpu_ll_resp_val), // @[RocketTile.scala:147:20] .io_ll_resp_type (_core_io_fpu_ll_resp_type), // @[RocketTile.scala:147:20] .io_ll_resp_tag (_core_io_fpu_ll_resp_tag), // @[RocketTile.scala:147:20] .io_ll_resp_data (_core_io_fpu_ll_resp_data), // @[RocketTile.scala:147:20] .io_valid (_core_io_fpu_valid), // @[RocketTile.scala:147:20] .io_fcsr_rdy (_fpuOpt_io_fcsr_rdy), .io_nack_mem (_fpuOpt_io_nack_mem), .io_illegal_rm (_fpuOpt_io_illegal_rm), .io_killx (_core_io_fpu_killx), // @[RocketTile.scala:147:20] .io_killm (_core_io_fpu_killm), // @[RocketTile.scala:147:20] .io_dec_ldst (_fpuOpt_io_dec_ldst), .io_dec_wen (_fpuOpt_io_dec_wen), .io_dec_ren1 (_fpuOpt_io_dec_ren1), .io_dec_ren2 (_fpuOpt_io_dec_ren2), .io_dec_ren3 (_fpuOpt_io_dec_ren3), .io_dec_swap12 (_fpuOpt_io_dec_swap12), .io_dec_swap23 (_fpuOpt_io_dec_swap23), .io_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), .io_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), .io_dec_fromint (_fpuOpt_io_dec_fromint), .io_dec_toint (_fpuOpt_io_dec_toint), .io_dec_fastpipe (_fpuOpt_io_dec_fastpipe), .io_dec_fma (_fpuOpt_io_dec_fma), .io_dec_div (_fpuOpt_io_dec_div), .io_dec_sqrt (_fpuOpt_io_dec_sqrt), .io_dec_wflags (_fpuOpt_io_dec_wflags), .io_dec_vec (_fpuOpt_io_dec_vec), .io_sboard_set (_fpuOpt_io_sboard_set), .io_sboard_clr (_fpuOpt_io_sboard_clr), .io_sboard_clra (_fpuOpt_io_sboard_clra), .io_keep_clock_enabled (_core_io_fpu_keep_clock_enabled) // @[RocketTile.scala:147:20] ); // @[RocketTile.scala:242:62] HellaCacheArbiter_7 dcacheArb ( // @[HellaCache.scala:292:25] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[PTW.scala:802:19] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[PTW.scala:802:19] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[PTW.scala:802:19] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[PTW.scala:802:19] .io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), .io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), .io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), .io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), .io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), .io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), .io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), .io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), .io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), .io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered), .io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending), .io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), .io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release), .io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant), .io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), .io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), .io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), .io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), .io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), .io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), .io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), .io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid (_core_io_dmem_req_valid), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_addr (_core_io_dmem_req_bits_addr), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_tag (_core_io_dmem_req_bits_tag), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_cmd (_core_io_dmem_req_bits_cmd), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_size (_core_io_dmem_req_bits_size), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_signed (_core_io_dmem_req_bits_signed), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dprv (_core_io_dmem_req_bits_dprv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_dv (_core_io_dmem_req_bits_dv), // @[RocketTile.scala:147:20] .io_requestor_1_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), // @[RocketTile.scala:147:20] .io_requestor_1_s1_kill (_core_io_dmem_s1_kill), // @[RocketTile.scala:147:20] .io_requestor_1_s1_data_data (_core_io_dmem_s1_data_data), // @[RocketTile.scala:147:20] .io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), .io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), .io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), .io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), .io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), .io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), .io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), .io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), .io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), .io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), .io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), .io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), .io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), .io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), .io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), .io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), .io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), .io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next), .io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), .io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), .io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), .io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), .io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), .io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), .io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), .io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered), .io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending), .io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), .io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release), .io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant), .io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), .io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), .io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), .io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), .io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), .io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), .io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), .io_requestor_1_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), // @[RocketTile.scala:147:20] .io_mem_req_ready (_dcache_io_cpu_req_ready), // @[HellaCache.scala:278:43] .io_mem_req_valid (_dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), .io_mem_req_bits_size (_dcacheArb_io_mem_req_bits_size), .io_mem_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), .io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), .io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), .io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), .io_mem_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), .io_mem_s1_kill (_dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data), .io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[HellaCache.scala:278:43] .io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[HellaCache.scala:278:43] .io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[HellaCache.scala:278:43] .io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[HellaCache.scala:278:43] .io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[HellaCache.scala:278:43] .io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[HellaCache.scala:278:43] .io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[HellaCache.scala:278:43] .io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[HellaCache.scala:278:43] .io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[HellaCache.scala:278:43] .io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[HellaCache.scala:278:43] .io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[HellaCache.scala:278:43] .io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[HellaCache.scala:278:43] .io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[HellaCache.scala:278:43] .io_mem_replay_next (_dcache_io_cpu_replay_next), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[HellaCache.scala:278:43] .io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[HellaCache.scala:278:43] .io_mem_ordered (_dcache_io_cpu_ordered), // @[HellaCache.scala:278:43] .io_mem_store_pending (_dcache_io_cpu_store_pending), // @[HellaCache.scala:278:43] .io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[HellaCache.scala:278:43] .io_mem_perf_release (_dcache_io_cpu_perf_release), // @[HellaCache.scala:278:43] .io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[HellaCache.scala:278:43] .io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[HellaCache.scala:278:43] .io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:278:43] .io_mem_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled) ); // @[HellaCache.scala:292:25] PTW_7 ptw ( // @[PTW.scala:802:19] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_dcache_io_ptw_req_valid), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[HellaCache.scala:278:43] .io_requestor_0_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[HellaCache.scala:278:43] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), .io_requestor_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), .io_requestor_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), .io_requestor_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), .io_requestor_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), .io_requestor_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), .io_requestor_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), .io_requestor_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), .io_requestor_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), .io_requestor_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), .io_requestor_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), .io_requestor_0_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), .io_requestor_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), .io_requestor_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), .io_requestor_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), .io_requestor_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), .io_requestor_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), .io_requestor_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), .io_requestor_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), .io_requestor_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), .io_requestor_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), .io_requestor_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), .io_requestor_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), .io_requestor_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), .io_requestor_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), .io_requestor_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), .io_requestor_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), .io_requestor_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), .io_requestor_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), .io_requestor_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), .io_requestor_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), .io_requestor_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), .io_requestor_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), .io_requestor_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), .io_requestor_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), .io_requestor_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), .io_requestor_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), .io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), .io_requestor_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), .io_requestor_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), .io_requestor_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), .io_requestor_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), .io_requestor_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), .io_requestor_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), .io_requestor_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), .io_requestor_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), .io_requestor_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), .io_requestor_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), .io_requestor_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), .io_requestor_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), .io_requestor_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), .io_requestor_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), .io_requestor_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), .io_requestor_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value), .io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready), .io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_valid (_frontend_io_ptw_req_bits_valid), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[Frontend.scala:393:28] .io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[Frontend.scala:393:28] .io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), .io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), .io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), .io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), .io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), .io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), .io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), .io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), .io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), .io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), .io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), .io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), .io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), .io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), .io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), .io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), .io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), .io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), .io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), .io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), .io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), .io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), .io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), .io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), .io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), .io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug), .io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease), .io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi), .io_requestor_1_status_isa (_ptw_io_requestor_1_status_isa), .io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv), .io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv), .io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv), .io_requestor_1_status_v (_ptw_io_requestor_1_status_v), .io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd), .io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv), .io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva), .io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr), .io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw), .io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm), .io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr), .io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum), .io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv), .io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs), .io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp), .io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp), .io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie), .io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie), .io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie), .io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie), .io_requestor_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), .io_requestor_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), .io_requestor_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), .io_requestor_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), .io_requestor_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), .io_requestor_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), .io_requestor_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), .io_requestor_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), .io_requestor_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), .io_requestor_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), .io_requestor_1_gstatus_v (_ptw_io_requestor_1_gstatus_v), .io_requestor_1_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), .io_requestor_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), .io_requestor_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), .io_requestor_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), .io_requestor_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), .io_requestor_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), .io_requestor_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), .io_requestor_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), .io_requestor_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), .io_requestor_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), .io_requestor_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), .io_requestor_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), .io_requestor_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), .io_requestor_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), .io_requestor_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), .io_requestor_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), .io_requestor_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), .io_requestor_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), .io_requestor_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), .io_requestor_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), .io_requestor_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), .io_requestor_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), .io_requestor_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), .io_requestor_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), .io_requestor_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), .io_requestor_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), .io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), .io_requestor_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), .io_requestor_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), .io_requestor_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), .io_requestor_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), .io_requestor_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), .io_requestor_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), .io_requestor_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), .io_requestor_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), .io_requestor_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), .io_requestor_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), .io_requestor_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), .io_requestor_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), .io_requestor_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), .io_requestor_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), .io_requestor_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), .io_requestor_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value), .io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[HellaCache.scala:292:25] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[HellaCache.scala:292:25] .io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[HellaCache.scala:292:25] .io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[HellaCache.scala:292:25] .io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[HellaCache.scala:292:25] .io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[HellaCache.scala:292:25] .io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[HellaCache.scala:292:25] .io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[HellaCache.scala:292:25] .io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[HellaCache.scala:292:25] .io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[HellaCache.scala:292:25] .io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[HellaCache.scala:292:25] .io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[HellaCache.scala:292:25] .io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[HellaCache.scala:292:25] .io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[HellaCache.scala:292:25] .io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[HellaCache.scala:292:25] .io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[HellaCache.scala:292:25] .io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[RocketTile.scala:147:20] .io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[RocketTile.scala:147:20] .io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_dpath_status_debug (_core_io_ptw_status_debug), // @[RocketTile.scala:147:20] .io_dpath_status_cease (_core_io_ptw_status_cease), // @[RocketTile.scala:147:20] .io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[RocketTile.scala:147:20] .io_dpath_status_isa (_core_io_ptw_status_isa), // @[RocketTile.scala:147:20] .io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[RocketTile.scala:147:20] .io_dpath_status_dv (_core_io_ptw_status_dv), // @[RocketTile.scala:147:20] .io_dpath_status_prv (_core_io_ptw_status_prv), // @[RocketTile.scala:147:20] .io_dpath_status_v (_core_io_ptw_status_v), // @[RocketTile.scala:147:20] .io_dpath_status_sd (_core_io_ptw_status_sd), // @[RocketTile.scala:147:20] .io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[RocketTile.scala:147:20] .io_dpath_status_gva (_core_io_ptw_status_gva), // @[RocketTile.scala:147:20] .io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[RocketTile.scala:147:20] .io_dpath_status_tw (_core_io_ptw_status_tw), // @[RocketTile.scala:147:20] .io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[RocketTile.scala:147:20] .io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[RocketTile.scala:147:20] .io_dpath_status_sum (_core_io_ptw_status_sum), // @[RocketTile.scala:147:20] .io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[RocketTile.scala:147:20] .io_dpath_status_fs (_core_io_ptw_status_fs), // @[RocketTile.scala:147:20] .io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[RocketTile.scala:147:20] .io_dpath_status_spp (_core_io_ptw_status_spp), // @[RocketTile.scala:147:20] .io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[RocketTile.scala:147:20] .io_dpath_status_spie (_core_io_ptw_status_spie), // @[RocketTile.scala:147:20] .io_dpath_status_mie (_core_io_ptw_status_mie), // @[RocketTile.scala:147:20] .io_dpath_status_sie (_core_io_ptw_status_sie), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spvp (_core_io_ptw_hstatus_spvp), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spv (_core_io_ptw_hstatus_spv), // @[RocketTile.scala:147:20] .io_dpath_hstatus_gva (_core_io_ptw_hstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_debug (_core_io_ptw_gstatus_debug), // @[RocketTile.scala:147:20] .io_dpath_gstatus_cease (_core_io_ptw_gstatus_cease), // @[RocketTile.scala:147:20] .io_dpath_gstatus_wfi (_core_io_ptw_gstatus_wfi), // @[RocketTile.scala:147:20] .io_dpath_gstatus_isa (_core_io_ptw_gstatus_isa), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dprv (_core_io_ptw_gstatus_dprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dv (_core_io_ptw_gstatus_dv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_prv (_core_io_ptw_gstatus_prv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_v (_core_io_ptw_gstatus_v), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sd (_core_io_ptw_gstatus_sd), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero2 (_core_io_ptw_gstatus_zero2), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpv (_core_io_ptw_gstatus_mpv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_gva (_core_io_ptw_gstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mbe (_core_io_ptw_gstatus_mbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sbe (_core_io_ptw_gstatus_sbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sxl (_core_io_ptw_gstatus_sxl), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero1 (_core_io_ptw_gstatus_zero1), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tsr (_core_io_ptw_gstatus_tsr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tw (_core_io_ptw_gstatus_tw), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tvm (_core_io_ptw_gstatus_tvm), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mxr (_core_io_ptw_gstatus_mxr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sum (_core_io_ptw_gstatus_sum), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mprv (_core_io_ptw_gstatus_mprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_fs (_core_io_ptw_gstatus_fs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpp (_core_io_ptw_gstatus_mpp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_vs (_core_io_ptw_gstatus_vs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spp (_core_io_ptw_gstatus_spp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpie (_core_io_ptw_gstatus_mpie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_ube (_core_io_ptw_gstatus_ube), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spie (_core_io_ptw_gstatus_spie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_upie (_core_io_ptw_gstatus_upie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mie (_core_io_ptw_gstatus_mie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_hie (_core_io_ptw_gstatus_hie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sie (_core_io_ptw_gstatus_sie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_uie (_core_io_ptw_gstatus_uie), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[RocketTile.scala:147:20] .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), .io_dpath_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), // @[RocketTile.scala:147:20] .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[PTW.scala:802:19] Rocket_7 core ( // @[RocketTile.scala:147:20] .clock (clock), .reset (reset), .io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17] .io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17] .io_imem_might_request (_core_io_imem_might_request), .io_imem_req_valid (_core_io_imem_req_valid), .io_imem_req_bits_pc (_core_io_imem_req_bits_pc), .io_imem_req_bits_speculative (_core_io_imem_req_bits_speculative), .io_imem_sfence_valid (_core_io_imem_sfence_valid), .io_imem_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), .io_imem_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), .io_imem_sfence_bits_addr (_core_io_imem_sfence_bits_addr), .io_imem_sfence_bits_asid (_core_io_imem_sfence_bits_asid), .io_imem_sfence_bits_hv (_core_io_imem_sfence_bits_hv), .io_imem_sfence_bits_hg (_core_io_imem_sfence_bits_hg), .io_imem_resp_ready (_core_io_imem_resp_ready), .io_imem_resp_valid (_frontend_io_cpu_resp_valid), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), // @[Frontend.scala:393:28] .io_imem_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), // @[Frontend.scala:393:28] .io_imem_resp_bits_data (_frontend_io_cpu_resp_bits_data), // @[Frontend.scala:393:28] .io_imem_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), // @[Frontend.scala:393:28] .io_imem_gpa_valid (_frontend_io_cpu_gpa_valid), // @[Frontend.scala:393:28] .io_imem_gpa_bits (_frontend_io_cpu_gpa_bits), // @[Frontend.scala:393:28] .io_imem_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), // @[Frontend.scala:393:28] .io_imem_btb_update_valid (_core_io_imem_btb_update_valid), .io_imem_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), .io_imem_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), .io_imem_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), .io_imem_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), .io_imem_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), .io_imem_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), .io_imem_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), .io_imem_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), .io_imem_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), .io_imem_btb_update_bits_target (_core_io_imem_btb_update_bits_target), .io_imem_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), .io_imem_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), .io_imem_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), .io_imem_bht_update_valid (_core_io_imem_bht_update_valid), .io_imem_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), .io_imem_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), .io_imem_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), .io_imem_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), .io_imem_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), .io_imem_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), .io_imem_flush_icache (_core_io_imem_flush_icache), .io_imem_npc (_frontend_io_cpu_npc), // @[Frontend.scala:393:28] .io_imem_perf_acquire (_frontend_io_cpu_perf_acquire), // @[Frontend.scala:393:28] .io_imem_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[Frontend.scala:393:28] .io_imem_progress (_core_io_imem_progress), .io_dmem_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[HellaCache.scala:292:25] .io_dmem_req_valid (_core_io_dmem_req_valid), .io_dmem_req_bits_addr (_core_io_dmem_req_bits_addr), .io_dmem_req_bits_tag (_core_io_dmem_req_bits_tag), .io_dmem_req_bits_cmd (_core_io_dmem_req_bits_cmd), .io_dmem_req_bits_size (_core_io_dmem_req_bits_size), .io_dmem_req_bits_signed (_core_io_dmem_req_bits_signed), .io_dmem_req_bits_dprv (_core_io_dmem_req_bits_dprv), .io_dmem_req_bits_dv (_core_io_dmem_req_bits_dv), .io_dmem_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), .io_dmem_s1_kill (_core_io_dmem_s1_kill), .io_dmem_s1_data_data (_core_io_dmem_s1_data_data), .io_dmem_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[HellaCache.scala:292:25] .io_dmem_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_dmem_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[HellaCache.scala:292:25] .io_dmem_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[HellaCache.scala:292:25] .io_dmem_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_dmem_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_dmem_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[HellaCache.scala:292:25] .io_dmem_ordered (_dcacheArb_io_requestor_1_ordered), // @[HellaCache.scala:292:25] .io_dmem_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[HellaCache.scala:292:25] .io_dmem_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[HellaCache.scala:292:25] .io_dmem_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[HellaCache.scala:292:25] .io_dmem_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[HellaCache.scala:292:25] .io_dmem_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_dmem_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dmem_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), .io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode), .io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_core_io_ptw_sfence_valid), .io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), .io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), .io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), .io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), .io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), .io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), .io_ptw_status_debug (_core_io_ptw_status_debug), .io_ptw_status_cease (_core_io_ptw_status_cease), .io_ptw_status_wfi (_core_io_ptw_status_wfi), .io_ptw_status_isa (_core_io_ptw_status_isa), .io_ptw_status_dprv (_core_io_ptw_status_dprv), .io_ptw_status_dv (_core_io_ptw_status_dv), .io_ptw_status_prv (_core_io_ptw_status_prv), .io_ptw_status_v (_core_io_ptw_status_v), .io_ptw_status_sd (_core_io_ptw_status_sd), .io_ptw_status_mpv (_core_io_ptw_status_mpv), .io_ptw_status_gva (_core_io_ptw_status_gva), .io_ptw_status_tsr (_core_io_ptw_status_tsr), .io_ptw_status_tw (_core_io_ptw_status_tw), .io_ptw_status_tvm (_core_io_ptw_status_tvm), .io_ptw_status_mxr (_core_io_ptw_status_mxr), .io_ptw_status_sum (_core_io_ptw_status_sum), .io_ptw_status_mprv (_core_io_ptw_status_mprv), .io_ptw_status_fs (_core_io_ptw_status_fs), .io_ptw_status_mpp (_core_io_ptw_status_mpp), .io_ptw_status_spp (_core_io_ptw_status_spp), .io_ptw_status_mpie (_core_io_ptw_status_mpie), .io_ptw_status_spie (_core_io_ptw_status_spie), .io_ptw_status_mie (_core_io_ptw_status_mie), .io_ptw_status_sie (_core_io_ptw_status_sie), .io_ptw_hstatus_spvp (_core_io_ptw_hstatus_spvp), .io_ptw_hstatus_spv (_core_io_ptw_hstatus_spv), .io_ptw_hstatus_gva (_core_io_ptw_hstatus_gva), .io_ptw_gstatus_debug (_core_io_ptw_gstatus_debug), .io_ptw_gstatus_cease (_core_io_ptw_gstatus_cease), .io_ptw_gstatus_wfi (_core_io_ptw_gstatus_wfi), .io_ptw_gstatus_isa (_core_io_ptw_gstatus_isa), .io_ptw_gstatus_dprv (_core_io_ptw_gstatus_dprv), .io_ptw_gstatus_dv (_core_io_ptw_gstatus_dv), .io_ptw_gstatus_prv (_core_io_ptw_gstatus_prv), .io_ptw_gstatus_v (_core_io_ptw_gstatus_v), .io_ptw_gstatus_sd (_core_io_ptw_gstatus_sd), .io_ptw_gstatus_zero2 (_core_io_ptw_gstatus_zero2), .io_ptw_gstatus_mpv (_core_io_ptw_gstatus_mpv), .io_ptw_gstatus_gva (_core_io_ptw_gstatus_gva), .io_ptw_gstatus_mbe (_core_io_ptw_gstatus_mbe), .io_ptw_gstatus_sbe (_core_io_ptw_gstatus_sbe), .io_ptw_gstatus_sxl (_core_io_ptw_gstatus_sxl), .io_ptw_gstatus_zero1 (_core_io_ptw_gstatus_zero1), .io_ptw_gstatus_tsr (_core_io_ptw_gstatus_tsr), .io_ptw_gstatus_tw (_core_io_ptw_gstatus_tw), .io_ptw_gstatus_tvm (_core_io_ptw_gstatus_tvm), .io_ptw_gstatus_mxr (_core_io_ptw_gstatus_mxr), .io_ptw_gstatus_sum (_core_io_ptw_gstatus_sum), .io_ptw_gstatus_mprv (_core_io_ptw_gstatus_mprv), .io_ptw_gstatus_fs (_core_io_ptw_gstatus_fs), .io_ptw_gstatus_mpp (_core_io_ptw_gstatus_mpp), .io_ptw_gstatus_vs (_core_io_ptw_gstatus_vs), .io_ptw_gstatus_spp (_core_io_ptw_gstatus_spp), .io_ptw_gstatus_mpie (_core_io_ptw_gstatus_mpie), .io_ptw_gstatus_ube (_core_io_ptw_gstatus_ube), .io_ptw_gstatus_spie (_core_io_ptw_gstatus_spie), .io_ptw_gstatus_upie (_core_io_ptw_gstatus_upie), .io_ptw_gstatus_mie (_core_io_ptw_gstatus_mie), .io_ptw_gstatus_hie (_core_io_ptw_gstatus_hie), .io_ptw_gstatus_sie (_core_io_ptw_gstatus_sie), .io_ptw_gstatus_uie (_core_io_ptw_gstatus_uie), .io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask), .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[PTW.scala:802:19] .io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), .io_ptw_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), .io_ptw_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), .io_ptw_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), .io_ptw_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), .io_ptw_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), .io_ptw_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), .io_ptw_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), .io_ptw_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), .io_ptw_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), .io_ptw_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), .io_ptw_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), .io_ptw_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), .io_ptw_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), .io_ptw_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), .io_ptw_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[PTW.scala:802:19] .io_fpu_hartid (_core_io_fpu_hartid), .io_fpu_time (_core_io_fpu_time), .io_fpu_inst (_core_io_fpu_inst), .io_fpu_fromint_data (_core_io_fpu_fromint_data), .io_fpu_fcsr_rm (_core_io_fpu_fcsr_rm), .io_fpu_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), // @[RocketTile.scala:242:62] .io_fpu_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), // @[RocketTile.scala:242:62] .io_fpu_store_data (_fpuOpt_io_store_data), // @[RocketTile.scala:242:62] .io_fpu_toint_data (_fpuOpt_io_toint_data), // @[RocketTile.scala:242:62] .io_fpu_ll_resp_val (_core_io_fpu_ll_resp_val), .io_fpu_ll_resp_type (_core_io_fpu_ll_resp_type), .io_fpu_ll_resp_tag (_core_io_fpu_ll_resp_tag), .io_fpu_ll_resp_data (_core_io_fpu_ll_resp_data), .io_fpu_valid (_core_io_fpu_valid), .io_fpu_fcsr_rdy (_fpuOpt_io_fcsr_rdy), // @[RocketTile.scala:242:62] .io_fpu_nack_mem (_fpuOpt_io_nack_mem), // @[RocketTile.scala:242:62] .io_fpu_illegal_rm (_fpuOpt_io_illegal_rm), // @[RocketTile.scala:242:62] .io_fpu_killx (_core_io_fpu_killx), .io_fpu_killm (_core_io_fpu_killm), .io_fpu_dec_ldst (_fpuOpt_io_dec_ldst), // @[RocketTile.scala:242:62] .io_fpu_dec_wen (_fpuOpt_io_dec_wen), // @[RocketTile.scala:242:62] .io_fpu_dec_ren1 (_fpuOpt_io_dec_ren1), // @[RocketTile.scala:242:62] .io_fpu_dec_ren2 (_fpuOpt_io_dec_ren2), // @[RocketTile.scala:242:62] .io_fpu_dec_ren3 (_fpuOpt_io_dec_ren3), // @[RocketTile.scala:242:62] .io_fpu_dec_swap12 (_fpuOpt_io_dec_swap12), // @[RocketTile.scala:242:62] .io_fpu_dec_swap23 (_fpuOpt_io_dec_swap23), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), // @[RocketTile.scala:242:62] .io_fpu_dec_fromint (_fpuOpt_io_dec_fromint), // @[RocketTile.scala:242:62] .io_fpu_dec_toint (_fpuOpt_io_dec_toint), // @[RocketTile.scala:242:62] .io_fpu_dec_fastpipe (_fpuOpt_io_dec_fastpipe), // @[RocketTile.scala:242:62] .io_fpu_dec_fma (_fpuOpt_io_dec_fma), // @[RocketTile.scala:242:62] .io_fpu_dec_div (_fpuOpt_io_dec_div), // @[RocketTile.scala:242:62] .io_fpu_dec_sqrt (_fpuOpt_io_dec_sqrt), // @[RocketTile.scala:242:62] .io_fpu_dec_wflags (_fpuOpt_io_dec_wflags), // @[RocketTile.scala:242:62] .io_fpu_dec_vec (_fpuOpt_io_dec_vec), // @[RocketTile.scala:242:62] .io_fpu_sboard_set (_fpuOpt_io_sboard_set), // @[RocketTile.scala:242:62] .io_fpu_sboard_clr (_fpuOpt_io_sboard_clr), // @[RocketTile.scala:242:62] .io_fpu_sboard_clra (_fpuOpt_io_sboard_clra), // @[RocketTile.scala:242:62] .io_fpu_keep_clock_enabled (_core_io_fpu_keep_clock_enabled), .io_trace_insns_0_valid (traceSourceNodeOut_insns_0_valid), .io_trace_insns_0_iaddr (traceSourceNodeOut_insns_0_iaddr), .io_trace_insns_0_insn (traceSourceNodeOut_insns_0_insn), .io_trace_insns_0_priv (traceSourceNodeOut_insns_0_priv), .io_trace_insns_0_exception (traceSourceNodeOut_insns_0_exception), .io_trace_insns_0_interrupt (traceSourceNodeOut_insns_0_interrupt), .io_trace_insns_0_cause (traceSourceNodeOut_insns_0_cause), .io_trace_insns_0_tval (traceSourceNodeOut_insns_0_tval), .io_trace_time (traceSourceNodeOut_time), .io_bpwatch_0_valid_0 (bpwatchSourceNodeOut_0_valid_0), .io_bpwatch_0_action (bpwatchSourceNodeOut_0_action), .io_wfi (_core_io_wfi) ); // @[RocketTile.scala:147:20] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7] assign auto_wfi_out_0 = auto_wfi_out_0_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_valid = auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr = auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn = auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv = auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception = auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt = auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause = auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval = auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }
module IssueSlot_30( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_273( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_17 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_19( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_27 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SinkA.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class PutBufferAEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val mask = UInt((params.inner.bundle.dataBits/8).W) val corrupt = Bool() } class PutBufferPop(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val index = UInt(params.putBits.W) val last = Bool() } class SinkA(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Decoupled(new FullRequest(params)) val a = Flipped(Decoupled(new TLBundleA(params.inner.bundle))) // for use by SourceD: val pb_pop = Flipped(Decoupled(new PutBufferPop(params))) val pb_beat = new PutBufferAEntry(params) }) // No restrictions on the type of buffer val a = params.micro.innerBuf.a(io.a) val putbuffer = Module(new ListBuffer(ListBufferParameters(new PutBufferAEntry(params), params.putLists, params.putBeats, false))) val lists = RegInit((0.U(params.putLists.W))) val lists_set = WireInit(init = 0.U(params.putLists.W)) val lists_clr = WireInit(init = 0.U(params.putLists.W)) lists := (lists | lists_set) & ~lists_clr val free = !lists.andR val freeOH = ~(leftOR(~lists) << 1) & ~lists val freeIdx = OHToUInt(freeOH) val first = params.inner.first(a) val hasData = params.inner.hasData(a.bits) // We need to split the A input to three places: // If it is the first beat, it must go to req // If it has Data, it must go to the putbuffer // If it has Data AND is the first beat, it must claim a list val req_block = first && !io.req.ready val buf_block = hasData && !putbuffer.io.push.ready val set_block = hasData && first && !free params.ccover(a.valid && req_block, "SINKA_REQ_STALL", "No MSHR available to sink request") params.ccover(a.valid && buf_block, "SINKA_BUF_STALL", "No space in putbuffer for beat") params.ccover(a.valid && set_block, "SINKA_SET_STALL", "No space in putbuffer for request") a.ready := !req_block && !buf_block && !set_block io.req.valid := a.valid && first && !buf_block && !set_block putbuffer.io.push.valid := a.valid && hasData && !req_block && !set_block when (a.valid && first && hasData && !req_block && !buf_block) { lists_set := freeOH } val (tag, set, offset) = params.parseAddress(a.bits.address) val put = Mux(first, freeIdx, RegEnable(freeIdx, first)) io.req.bits.prio := VecInit(1.U(3.W).asBools) io.req.bits.control:= false.B io.req.bits.opcode := a.bits.opcode io.req.bits.param := a.bits.param io.req.bits.size := a.bits.size io.req.bits.source := a.bits.source io.req.bits.offset := offset io.req.bits.set := set io.req.bits.tag := tag io.req.bits.put := put putbuffer.io.push.bits.index := put putbuffer.io.push.bits.data.data := a.bits.data putbuffer.io.push.bits.data.mask := a.bits.mask putbuffer.io.push.bits.data.corrupt := a.bits.corrupt // Grant access to pop the data putbuffer.io.pop.bits := io.pb_pop.bits.index putbuffer.io.pop.valid := io.pb_pop.fire io.pb_pop.ready := putbuffer.io.valid(io.pb_pop.bits.index) io.pb_beat := putbuffer.io.data when (io.pb_pop.fire && io.pb_pop.bits.last) { lists_clr := UIntToOH(io.pb_pop.bits.index, params.putLists) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module SinkA( // @[SinkA.scala:38:7] input clock, // @[SinkA.scala:38:7] input reset, // @[SinkA.scala:38:7] input io_req_ready, // @[SinkA.scala:40:14] output io_req_valid, // @[SinkA.scala:40:14] output [2:0] io_req_bits_opcode, // @[SinkA.scala:40:14] output [2:0] io_req_bits_param, // @[SinkA.scala:40:14] output [2:0] io_req_bits_size, // @[SinkA.scala:40:14] output [6:0] io_req_bits_source, // @[SinkA.scala:40:14] output [12:0] io_req_bits_tag, // @[SinkA.scala:40:14] output [5:0] io_req_bits_offset, // @[SinkA.scala:40:14] output [5:0] io_req_bits_put, // @[SinkA.scala:40:14] output [9:0] io_req_bits_set, // @[SinkA.scala:40:14] output io_a_ready, // @[SinkA.scala:40:14] input io_a_valid, // @[SinkA.scala:40:14] input [2:0] io_a_bits_opcode, // @[SinkA.scala:40:14] input [2:0] io_a_bits_param, // @[SinkA.scala:40:14] input [2:0] io_a_bits_size, // @[SinkA.scala:40:14] input [6:0] io_a_bits_source, // @[SinkA.scala:40:14] input [31:0] io_a_bits_address, // @[SinkA.scala:40:14] input [15:0] io_a_bits_mask, // @[SinkA.scala:40:14] input [127:0] io_a_bits_data, // @[SinkA.scala:40:14] input io_a_bits_corrupt, // @[SinkA.scala:40:14] output io_pb_pop_ready, // @[SinkA.scala:40:14] input io_pb_pop_valid, // @[SinkA.scala:40:14] input [5:0] io_pb_pop_bits_index, // @[SinkA.scala:40:14] input io_pb_pop_bits_last, // @[SinkA.scala:40:14] output [127:0] io_pb_beat_data, // @[SinkA.scala:40:14] output [15:0] io_pb_beat_mask, // @[SinkA.scala:40:14] output io_pb_beat_corrupt // @[SinkA.scala:40:14] ); wire io_pb_pop_ready_0; // @[SinkA.scala:105:40] wire _putbuffer_io_push_ready; // @[SinkA.scala:51:25] wire [39:0] _putbuffer_io_valid; // @[SinkA.scala:51:25] reg [39:0] lists; // @[SinkA.scala:52:22] wire [39:0] _freeOH_T_22 = ~lists; // @[SinkA.scala:52:22, :59:25] wire [38:0] _freeOH_T_3 = _freeOH_T_22[38:0] | {_freeOH_T_22[37:0], 1'h0}; // @[package.scala:253:{43,53}] wire [38:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[36:0], 2'h0}; // @[package.scala:253:{43,53}] wire [38:0] _freeOH_T_9 = _freeOH_T_6 | {_freeOH_T_6[34:0], 4'h0}; // @[package.scala:253:{43,48,53}] wire [38:0] _freeOH_T_12 = _freeOH_T_9 | {_freeOH_T_9[30:0], 8'h0}; // @[package.scala:253:{43,53}] wire [38:0] _freeOH_T_15 = _freeOH_T_12 | {_freeOH_T_12[22:0], 16'h0}; // @[package.scala:253:{43,48,53}] wire [39:0] _GEN = {~(_freeOH_T_15 | {_freeOH_T_15[6:0], 32'h0}), 1'h1} & _freeOH_T_22; // @[package.scala:253:{43,48,53}] wire [30:0] _freeIdx_T_1 = {24'h0, _GEN[39:33]} | _GEN[31:1]; // @[OneHot.scala:31:18, :32:28] wire [14:0] _freeIdx_T_3 = _freeIdx_T_1[30:16] | _freeIdx_T_1[14:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [6:0] _freeIdx_T_5 = _freeIdx_T_3[14:8] | _freeIdx_T_3[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _freeIdx_T_7 = _freeIdx_T_5[6:4] | _freeIdx_T_5[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [5:0] freeIdx = {|(_GEN[39:32]), |(_freeIdx_T_1[30:15]), |(_freeIdx_T_3[14:7]), |(_freeIdx_T_5[6:3]), |(_freeIdx_T_7[2:1]), _freeIdx_T_7[2] | _freeIdx_T_7[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] reg [1:0] first_counter; // @[Edges.scala:229:27] wire first = first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire req_block = first & ~io_req_ready; // @[Edges.scala:231:25] wire buf_block = ~(io_a_bits_opcode[2]) & ~_putbuffer_io_push_ready; // @[Edges.scala:92:{28,37}] wire set_block = ~(io_a_bits_opcode[2]) & first & (&lists); // @[Edges.scala:92:{28,37}, :231:25] wire io_a_ready_0 = ~req_block & ~buf_block & ~set_block; // @[SinkA.scala:70:25, :71:27, :72:{27,36}, :78:{14,25,28,39,42}] wire _io_req_valid_T = io_a_valid & first; // @[Edges.scala:231:25] reg [5:0] put_r; // @[SinkA.scala:84:42] wire [5:0] put = first ? freeIdx : put_r; // @[OneHot.scala:32:10] wire putbuffer_io_pop_valid = io_pb_pop_ready_0 & io_pb_pop_valid; // @[Decoupled.scala:51:35] wire [39:0] _io_pb_pop_ready_T = _putbuffer_io_valid >> io_pb_pop_bits_index; // @[SinkA.scala:51:25, :105:40] assign io_pb_pop_ready_0 = _io_pb_pop_ready_T[0]; // @[SinkA.scala:105:40] wire [63:0] _lists_clr_T = 64'h1 << io_pb_pop_bits_index; // @[OneHot.scala:65:12] wire [12:0] _first_beats1_decode_T = 13'h3F << io_a_bits_size; // @[package.scala:243:71] always @(posedge clock) begin // @[SinkA.scala:38:7] if (reset) begin // @[SinkA.scala:38:7] lists <= 40'h0; // @[SinkA.scala:52:22] first_counter <= 2'h0; // @[Edges.scala:229:27] end else begin // @[SinkA.scala:38:7] lists <= (lists | (_io_req_valid_T & ~(io_a_bits_opcode[2]) & ~req_block & ~buf_block ? _GEN : 40'h0)) & ~(putbuffer_io_pop_valid & io_pb_pop_bits_last ? _lists_clr_T[39:0] : 40'h0); // @[OneHot.scala:65:{12,27}] if (io_a_ready_0 & io_a_valid) // @[Decoupled.scala:51:35] first_counter <= first ? (io_a_bits_opcode[2] ? 2'h0 : ~(_first_beats1_decode_T[5:4])) : first_counter - 2'h1; // @[package.scala:243:{46,71,76}] end if (first) // @[Edges.scala:231:25] put_r <= freeIdx; // @[OneHot.scala:32:10] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_52( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_453( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_197 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_137( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule